Design-Silicon Timing Correlation A Data Mining Perspective Λ

Transcription

1 221 Design-Silicon Tiing Correlation A Data Mining Perspective Λ i-c Wang Univ of CA - Santa Barbara licwang@eceucsbedu Pouria Bastani Univ of CA - Santa Barbara bastanip@eceucsbedu Magdy S Abadir Freescale Seiconductor, Inc MAbadir@freescaleco ABSTRACT In the post-silicon stage, tiing inforation can be etracted fro two sources: (1) on-chip onitors and (2) delay testing In the past, delay test data has been overlooked in the correlation study In this paper, we take path delay testing as an eaple to illustrate how test data can be incorporated in the overall design-silicon correlation effort We describe a path-based ethodology that correlates easured path delays fro the good chips, to the path delays predicted by tiing analysis We discuss how statistical data ining can be eployed for etracting inforation and show eperiental results to deonstrate the potential of the proposed ethodology Categories and Subect Descriptors: B82 [Hardware]: Perforance and reliability General Ters: Algoriths, Perforance and Reliability Keywords: Statistical Tiing, earning, Correlation, Tiing, Test 1 INTRODUCTION As feature sizes of device and interconnect continues to shrink, design behavior becoes ore sensitive to process and environental variations and uncertainties Consequently, pre-silicon odeling and siulation alone ay not be sufficient to answer all designrelated questions For soe questions left unanswered, a coon practice is to analyze the behavior of first-silicon chip saples For eaple, it is difficult to predict the actual speed-liiting paths in a high-perforance processor Hence, speed-path identification is usually done by analyzing silicon saples These paths are often different fro the critical paths estiated by a tiing analyzer [1] During a design process, there can be any effects not odeled and siulated accurately Each effect ay or ay not significantly ipact silicon behavior One coonly-asked question is aong those effects which ones cannot be ignored The answer to a question of such can be design dependent, design ethodology dependent, and process technology dependent In the past, the agnitude of isatch between siulated behavior and actual behavior is relatively sall Unless our design goal is Λ This work is supported in part by National Science Foundation, Grant No and Seiconductor Research Corporation, proect task Perission to ake digital or hard copies of all or part of this work for personal or classroo use is granted without fee provided that copies are not ade or distributed for profit or coercial advantage and that copies bear this notice and the full citation on the first page To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific perission and/or a fee DAC 27, June 4 8, 27, San Diego, California, USA Copyright 27 ACM /7/6 $5 to push for etreely high perforance, the iscorrelation is often not analyzed in detail A coon practice is to classify a chip as defective if its behavior is far fro the nor Then, we utilize various diagnosis ethods to pin-point the potential locations that ay cause the unepected behavior, followed by a rather tedious silicon debug process to uncover the root cause(s) Historically, unepected chip behavior is assued to be ostly due to anufacturing defects Hence, diagnosis and silicon debug ethods are optiized to look for defects These ethods analyze chips individually and the analysis is carried out on (suspected) failing chips only Diagnosis and silicon debug [2] [3] [4] [5] can be seen as the traditional ways to etract inforation fro silicon If our goal is to etract design-related inforation, a typical approach is to look for systeatic failures For eaple, a weak gate ay cause a collection of chips to fail tiing in a siilar way Diagnosis and debug on a few of these chips individually ay uncover the location(s) of the weak gate and consequently help to iprove the current design For helping design, analyzing failure data akes sense if (1) we have a collection of failing chips that fail in systeatic ways and (2) we can afford to fi the current design Fro this perspective, diagnosis and silicon debug can be used to recover significant yield loss due to systeatic design errors This is feasible if we can afford the cost associated with (1) silicon debug that is usually a tedious process involving the use of epensive equipent and (2) design respin that can be overly epensive in soe cases # of chips Good chip data Data fro arginal chips failure data 1/Fa Figure 1: Three categories of chips to analyze For studying design-silicon correlation, failure data should not be the only place to look for inforation Figure 1 illustrates three categories of chips that ay be analyzed When analyzing a collection of supposedly good (and arginal) chips, the data can be inherently statistical due to process and environental variations and uncertainties Moreover, the nuber of chips to be analyzed can be large and it would be ore effective to analyze their behavior collectively rather than individually In this case, traditional diagnosis and debug ethods can be ineffective When analyzing failing chips, the obective is clear, that is to identify the cause(s) of the failures When analyzing good and arginal chips, the obective can vary For eaple, the goal can be to validate certain assuptions in a tiing odel One coon approach is to place on-chip onitors in various locations of a die For ea- Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 384

2 ple, process onitors are for checking certain low-level paraeters such as eff, V th On-chip voltage onitors can be used to check IR drop Test structures, such as ring oscillators, have been used to onitor integrated circuit perforance for any years [6, 7] Test structures are priarily designed to provide a easure of perforance, power and variability of the current design process The data easured fro test structures relates these easures to the properties of low level device paraeters, in particular to MOSFETs and to parasitic delay eleents [8, 9] Ring oscillators have several beneficial features They take up inial area and can be placed in sall open spaces in a design They can be directly easurable by a test probe to iniize test easureent error Because ring oscillators are siple circuitry, there are aspects of design that cannot be studied by the ethodology For eaple, argins are often added at various stages of a tiing analysis flow The ipact of these decisions on silicon tiing usually cannot be easured by using only on-chip onitors In addition to on-chip onitors, delay testing can also be used to study silicon tiing behavior For studying silicon behavior, a separate testing ethodology is often required in order to support the collection of test data that contain the required inforation for the analysis This delay testing ethodology is different fro the one used in production testing As illustrated in Figure 2, this ethodology is to test for inforation Tests are usually ore coprehensive and provide higher resolution In contrast, a production delay testing ethodology is often optiized for cost and for defect-screening capability The size of the test pattern set is an iportant consideration The nuber of test clocks ay be strictly liited Design Manufacturing Saple chips Volue production testing Inforative testing Good chips Bad chips Data for further analysis Figure 2: Inforative testing is different fro production testing For eaple, consider production delay testing where a test clock is pre-deterined A chip is defective if its delay on any test pattern eceeds this clock In testing for inforation, test clock can be a prograable value The goal can be to estiate the failing frequency of each test pattern targeting a specific critical path Tiing odel and siulation ow level paraeters SYSTEM EVE difference Correlation analysis Correlation analysis difference DEVICE EVE Observed behavior in test Correlation analysis Measured data fro onchip onitors Figure 3: Three types of correlation analysis Figure 3 gives an overall picture of design-silicon tiing correlation that includes three types of correlation analysis At the lowlevel, a ethodology can be based on on-chip onitors The targets of the analysis can be the within-die variations of device paraeters, voltage, and teperature These variations are usually large and considered as iportant factors to ipact tiing At the high-level, the ethodology is based on delay testing This type of correlation analysis has been overlooked in the past priarily due to the fact that delay testing traditionally is optiized for cost and for defect screening Because using it for correlation analysis is rather new, the rest of the paper will focus on this type of analysis In particular, the analysis will be based on the differences between predicted path delays fro a tiing analysis tool and easured path delays on a set of silicon saples We focus on such a path-based analysis approach to avoid the coplication of dealing with noises such as cross-coupling effects Therefore, for a path to be included in the analysis, we require a test pattern that sensitizes only the path Figure 3 shows a third type of correlation analysis that tries to correlate the results between the high-level analysis and the lowlevel analysis The developent of this type of ethodology needs to wait until the high-level and low-level ethodologies are fully developed However, in this paper when we discuss the high-level analysis, we will also show that the effectiveness of the analysis can be independent of the low-level paraeter shifts 2 AN INDUSTRIA EXPERIMENT This section describes an industrial eperient that studied the correlation between structural path delay testing (PDT) and a noinal static tiing analyzer (STA) The STA is capable of producing a critical path report This is a list of paths that the tool has deterined having the least aount of tiing slack with respect to a tiing requireent For late-ode analysis, the tiing requireent is usually a setup-tie constraint Fro the critical path report, the individual cell delays, net delays, clock skew, setup-tie and slack for the listed critical paths can be deterined Each path can be epressed as an equation: STA delay =X c i +X n + setup = clock + skew slack (1) c i are the cell delays (including the launch flip-flop s delay), n are the net delays, clock is the clock period, and skew is the clock skew Structural path delay tests are generated to target paths fro the STA s critical path report The tester is prograed to search for an individual path delay test s aiu passing frequency This easured path delay can be epressed as another equation: PDT delay =X ^c i +X ^n + setup ^ = easured + skew ^ (2) In the above equation, the variables with hats are the actual delays that cannot be directly easured What we easured fro the tester was, easured the iniu passing period (reciprocal of the aiu passing frequency) Note there is no slack variable, because at the iniu passing period, we assue the slack is zero Although we cannot directly easure soe of these delay variables, in order to eplain the difference (STA delay PDT delay ) on all paths, we ake soe siple assuptions ff c Λ X ci = X P P ^c i ff n Λ n i = ^n i (3) ff s Λ setup = setup skew = ^ skew Essentially, for each chip we assue three constants ff c;ff n;ff s that can be thought as the correction factors for the luped cell, luped net and setup delays These coefficients give a sense of where the isatch between pre-silicon and post-silicon tiing lies individually on each chip In particular, ff c tracks the isatch of cell characterization, ff n tracks the isatch of the interconnect etraction and ff s tracks the pessiis of the setup tie constraint of the flip flop Due to the resolution of the testing, we decided not to have a correction factor on the skew We solve for the coefficients individually for each chip This is an over-constrained syste of equations as the nuber of paths is greater than the nuber of isatch coefficients This overconstrained syste of equations can be solved in a least-square anner using Singular Value Decoposition to find the best fit 21 Results on 24 icroprocessor chips The eperient was done based on 495 critical paths These are latch-to-latch paths without passing through ebedded eories Results were collected on 24 packaged chips belonging to Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 385

3 two wafer lots anufactured several onths apart These chips are industrial high-perforance icroprocessors Noralized Occurrences ot ot Cell Delay Misatch Noralized Occurrences ot ot Net Delay Misatch (a) ff c histogra (b) ff n histogra Figure 4: Histogras of isatch coefficients ff c, ff n Figure 4 presents the distributions of ff c and ff n fro the two lots ff s distributions are siilar to ff c distributions and hence, are not shown The ff c and ff n results clearly show that STA are overly pessiistic, ie all coefficients are less than one This ay be partially because the chips were anufactured at a later point of the process, and the cell characterizations were done at an earlier point Unlike Figure 4-(a), the two distributions in Figure 4-(b) are separated apart This indicates that net delays are ore sensitive to the lot shift The analysis is inconclusive because without proper tools and ethodologies, we couldn t perfor ore detailed study We note that equation 3 lups all the effects into three paraeters and these paraeters are estiated on each chip individually This is a very rough analysis We would need a ore sophisticated ethod to study the data further 3 MODE-BASED EARNING Siulated data difference Measured data learning Model M( p 1,p 2,,p n ) Figure 5: Model-based learning If we have soe idea on the aor causes for the difference behavior, we ay utilize a odel-based learning approach to validate the idea A odel M(p 1,p 2, :::, p n) based on a set of n paraeters is assued in the learning The goal of learning is to quantify the values of these paraeters based on the difference data For eaple, in [1] the authors assue that the difference between predicted path delays and easured path delays is ainly due to un-odeled effect fro within-die delay variation A grid-based odel was used and the unknown paraeters to estiate becae spatial delay correlations (within grid and across grids) [12] The authors proposed a Bayesian based inference technique to quantify these paraeters [13] Because the odel and the nuber of paraeters are fied in advance, odel-based learning can be seen as a way of paraetric learning [11] The advantage is that we can begin by assuing a odel that has a link to soe physical interpretation The liitations are twofold First, there are aspects in the behavior difference that ay not be eplainable through a clearly defined odel Second, if a odel is too cople, we ay not have enough test data to quantify the values of all paraeters with high confidence The liitations otivate us to take a non-paraetric learning approach where no fied odel is assued in advance In this case, the goal is no longer to estiate the values of certain paraeters In the following, we will forulate a new goal 4 IMPORTANCE RANKING Suppose we have a tiing odel ade up of n delay entities where each entity consists of a nuber of delay eleents Suppose in total there are l delay eleents To clarify, a delay entity is an abstract ter that can be fleibly defined by a user Figure 6 illustrates the difference between a delay entity and a delay eleent For eaple, an entity can be a standard cell (ie Nand, Nor, etc) In a tiing odel, a standard cell consists of ultiple pin-to-pin delays These delays are delay eleents in the entity An entity can also be a group of routing patterns for nets For eaple, after delay calculation, the delay of each net is added into the odel Then, each net delay becoes a delay eleent of the entity Delay Entity Cells Groups of Nets Delay Eleent Pin to Pin Delay e i e i Individual Wire Delay Figure 6: Delay entity Vs delay eleent Suppose we are given a set Q of l delay eleents, fe 1;:::;e l g and a set of critical paths fp 1;:::;p g, that are ade up of those delay eleents In siulation, the delay of each path p i is a function T i(q) In our case, T i is the estiated tiing produced by a tiing analysis tool et T =[T i(:);:::;t (:)] In test, suppose that path delays are easured on k saple chips The result is a k atri D = D ~ 1;:::; D ~ Each D ~ i is a colun vector [d 1i;:::;d i] T Each d i is the delay of path on chip i Assue we have fully characterized each entity to the best we could Also assue that on silicon there is a systeatic deviation in the delays of each entity Our goal is to analyze fq, T, Dg and rank delay entities in ters of their deviations 41 Feature ranking in binary classification To rank delay entities, we propose a ethodology consisting of the following steps: (1) We convert the dataset into a binary classification proble (2) We apply a learning algorith for binary classification on the dataset to build a learned odel (3) Fro the learned odel, we obtain the iportance of each feature as a value Here, a feature in the learned odel refers to a delay entity (4) We use the feature iportance values to rank entities To siplify the discussion, assue that we are using a noinal static tiing analysis tool Therefore, T is a vector of estiated path delays et D ave= [D 1;:::;D ] be the average path delays easured on k chips based on the data atri D The difference is a vector Y =T D ave =[y 1, :::, y ] Each path p i consists of a set of q delay eleents fe i1, :::, e iq g Recall that these eleents coe fro n delay entities et ~ i =[d 1;:::;d n] Each d is the su of all delays in fe i1 ;:::;e iq g where these delays coe fro the entity d =if no delays coe fro the entity In this way, each path is represented as a vector of n delays The input dataset becoes S=f(~ 1;y 1), :::, (~ ;y )g Paths p1 p2 p Entities d1 d2 dn-1 dn Delay ps ps p1 p2 Avg Delay 997ps 81ps ps p 69ps p 91ps (+1) Estiated Delay Measured Delay Delay Difference p1 p2 Delay -74ps (-1) 4ps (+1) Figure 7: Converting to a binary classification proble The first step in our ethodology is to convert the dataset into a binary classification proble Given a threshold threshold, we Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 386

4 define ^y i = 1 if y i» threshold and otherwise ^y i =+1This produces a new dataset ^S=f(~ 1; ^y 1), :::, (~ ; ^y )g, asshownin Figure 7 for threshold = 42 Support vector classifier Given ^S, we then apply a learning algorith to build a binary classifier Then, we analyze the structure of this classifier to quantify the iportance of each entity There are soe classifiers whose structures allow the iportance of variables to be evaluated easily and others that do not This work eaines one classifier that belongs to the forer, the Support Vector Machine (SVM) classifier Given ^S ρ ( ~ X ^Y ), SVM ipleents a faily of algoriths that can work with a variety of kernel functions [14] We only use the linear kernel K(~ i;~ ) = (~ i ~ ) which is siply the dot product of the two vectors With a linear kernel, the SVM classifier is a hyperplane ~w ~ +b If the two-class data are linearly separable, ~w; b can be obtained fro solving the optiization proble: iniize( ~w ~w)subect to ^y i(( ~w ~ i)+b) 1;i=1;:::; (4) This is a hard-argin algorith that finds the aiu-argin hyperplane The argin q fro the resulting hyperplane ~w Λ ~ + b to its nearest point is 1= ( ~w Λ ~w Λ ),where ~w Λ is the optial solution to equation (4) The optiization proble can be solved in its dual for using agrange P ethod [14]: aiize yiyffiff(~i ~) P i=1 ffi 1 P 2 i=1 =1 X subect to ( i=1 y iff i)=and ff i (5) where ff i;ff are agrange ultipliers Solving the proble results in P optial solution ~ff Λ The solution to the prial becoes ~w Λ = i=1 yiffλ i ~ ithevalueb is then decided based on the optial prial solution ~w Λ Figure 8 illustrate the relation between ~ff Λ and ~w Λ We notice that each ff is associated with a path and each w is associated with a delay entity Path 1 Path 2 Path agrange Class α 1 α 2 y2 21 M M M α y y 1 w Delay Entities w M M w n 1n 2n M n Figure 8: Illustration of ~ff Λ and ~w Λ If ^S is not linearly separable, in the prial forulation, we can introduce slack variables ο i, i = P 1;:::; and the iniization obective becoes ( ~w ~w) +C i=1 (οi)2 C constrains the agrange ultiplier, ie C ff i This becoes a soft-argin algorith [14] and the approach to solve it is siilar to the linearly separable case describe above It is interesting to note that in the optial solution ~ff Λ =(ff Λ 1, :::, ff Λ ), soeff Λ i =Ifff Λ i =, then essentially ~ i (path i) hasno ipact on the construction of the classifier Hence, ~w Λ depends only on the paths whose ff values are not zero In our ethodology, we therefore use w Λ to rank cell s 43 Intuition behind using w Λ We observe that w Λ does not directly easure the delay deviation of entity Note that the value of the agrange ultiplier ff Λ i easures the iportance of the vector ~ i (of path i) in constructing the classifier A large ff Λ i indicates that the vector ~ i is a strong constraint for the resulting hyperplane i is the aount of estiated delay contributed fro cell s to path p i Hence, i > and ff Λ i > In addition, y i 2f 1; 1g y i = 1 eans that STA under-estiates the path delay y i =1 eans that STA over-estiates Hence, the sign of each y iff Λ i i is decided by the sign of y i Therefore, each y iff Λ i i is a easure of the iportance of cell s in contributing to the over-estiation or under-estiation w Λ is the su of this iportance over all paths and hence, is a easure of the overall iportance of cell s i in contributing to the over-estiation or under-estiation 5 EXPERIMENTS In this section we discuss the eperients to validate the effectiveness of the above iportance ranking ethodology Recall that our obective is to rank delay entities based on their deviations fro the odeled delay values It is iportant to note that the ranking ethodology above does not easure these deviations directly In this section, we will describe a linear uncertainty odel for the delay deviations Then, we will copare the iportance ranking to the assued true ranking based on this uncertainty odel 51 The linear uncertainty odel To siplify the discussion, we assue for now that a delay entity is a standard cell and delay eleents are pin-to-pin delays in the cell ater in Section 55, we will show that our fraework can be easily etended to include analysis on net delays Assue that the l delay eleents coe fro n standard cells, fs 1;:::;s ng We also assue that the actual delay of e i, (of a standard cell s ) on the silicon can be represented as: ^e i = ean i +eancell +ean pin i +std i ±std cell ±std pin i +ffl i (6) where ean i is the estiated ean delay, std i is a Gaussian rando variable with ean zero, which represents the estiated standard deviation ean cell represents the ean delay deviation for every pin-to-pin delay of the cell ean pin i represents the additional ean delay deviation for e i only std cell and std pin i are the deviations on the standard deviation, which both are Gaussian variables with ean zero Notice that std cell and std pin i can be used to result in reduced delay variation ffl i is a zero-ean Gaussian variable which can be used to odel noise such as easureent error We assue that in the tiing odel, e i is characterized only as e i = ean i +std i Because std cell, std pin i,andffl i are assued to be Gaussian with ean zero, we can also refer the as the standard deviation values Given a cell s, we have two types of uncertainty, Uncer ean(s )=ean cell and Uncer std (s )=std cell In the eperients, we randoly select the values for ean cell, ean pin i, std cell, std pin i,andffl i to perturb the statistical delay library Then, we perfor Monte Carlo siulation based on the perturbed library to produce the results of k saples We use the results as if they coe fro easureent on k saple chips Fro the perturbed library, we can obtain the assued true ranking based on the actual deviation values used to perturb the library In the following we discuss results based on ean cell Results on are oitted because they show siilar trends std cell 52 Eperiental setup We took a cell library of 13 cells characterized based on a 9n technology The characterization gives each pin-to-pin delay e i,a ean delay value ean i and a standard deviation std i In this baseline study, we select (= 5) rando paths Each path consists of 2 to 25 delay eleents These paths are analyzed through a statistical static tiing analysis (SSTA) tool [15] to obtain a ean and standard deviation for each path delay The cell library is then Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 387

5 perturbed using the linear uncertainty odel Then, we perfor Monte-Carlo siulation to produce k = 1 saples If our obective is to rank cells based on ean cell, then the initial dataset is converted into easured ean path delays If the obective is to rank cells based on std cell, standard deviation of each path delay is calculated based on k saples In both cases, we use the ethod described before to produce the difference dataset S=f(~ 1;y 1), :::, (~ ;y )g Then, a value threshold is selected to convert S into a binary classification dataset ^S The dataset ^S is analyzed using SVM and the weight vector ~w Λ is calculated Fro the values of w Λ, we obtain a ranking This rankings is then copared to the true ranking that is based on either ean cell (or ean cell ) orstd cell (or std cell ) 53 Correlation between w Λ and ean cell ean cell is sapled fro a Gaussian distribution N(μ; ff 2 ) where μ =and ff = :2 a where a is the average of all ean delays in the cell Hence, we want ean cell to be roughly between 3 ±2% of a In a siilar way, individually we add ean pin i to the pin-to-pin delay i, which is roughly between ±1% of ean i The std cell, std pin i, ffl i have no ipact because we focus ranking on ean cell Therefore, their nubers are arbitrarily assigned For eaple, we let std cell be a rando variable whose ±3ff is ±2% of a, std pin i be a rando variable whose ±3ff is ±2% of ean pin i, and ffl i be a rando variable whose ±3ff is ±5% of a # of cells Pico-seconds (a) Histogra of ean cell Figure 9: ean cell # of paths Pico-seconds threshold = to split into 2 classes (b) Path delay differences and path delay differences Figure 9-(a) shows the histogra of ean cell, = 1 :::13, in ters of their actual values in picoseconds Figure 9-(b) shows the histogra of path delay differences, ie y 1;:::;y 5 Wefirst select threshold =to split the distribution in the iddle so that ^y i =+1if y i and otherwise ^y i = 1 The new dataset is then given to SVM to calculate ~w Λ Noralized ean Cell Grouped = y line argest positive argest negative Noralized sv w * Figure 1: Correlation on noralized w Λ and ean cell Net, we noralize the values of ean cell and w Λ into the sae range [; 1] Then, we do an X-Y scatter plot for every point using the noralized ean cell as the Y value and noralized w Λ as the X value Figure 1 shows the scatter plot It is interesting to notice in Figure 1 that on the top right there is one outlier cell and then a gap followed by three cells clustering When we copare this figure to figure 9-(a), we can see that on the right (positive) side of the histogra there is one high ean cell and then there is a gap followed by three cells with very siilar ean cell If we copare the (botto) lefts of both figures, the cells are grouped very closely together in both figures and there is no cell as a clear outlier True Ranking Cells with largest positive uncertainty = y line Cells with largest negative uncertainty Ranking based on sv w * Figure 11: SVM w Λ ranking vs true ranking For each cell s, we obtain its SVM ranking based on w Λ and true ranking based on ean cell et the be SV M and true We then do an X-Y scatter plot for every point (SV M ;true ) Figure 11-(a) shows the ranking correlation result We observe good correlation between the two rankings, especially on those cells with the largest uncertainties Notice that there are two highly correlated ends The cells with saller SV M and true (botto left) have large negative uncertainties and the cells with larger SV M and true (top right) have large positive uncertainties 54 Ipact of systeatic eff shift In this section, our goal is to show that a systeatic process shift on a low-level paraeter such as eff would not degrade the effectiveness of the proposed ranking ethod This is a desired feature because our ethodology analyze design-silicon correlation at the high level of Figure 3 As eplained before, one can also utilize onchip onitors to study the correlation at the low level, ie SPICE paraeter level Therefore, we desire our ethodology to be applicable independently of a low-level correlation ethodology We siulate the effect of a 1% systeatic shift in eff and observe its ipact on the ranking accuracy Recall that we use a standard cell library that was characterized with 9n technology We re-characterized the library with 99n technology and then inected the sae aount of the deviations as that in the baseline study This new and perturbed library is then used in Monte Carlo siulation to produce the easured path delays Note that the predicted delays are still based on the original 9n statistical tiing library Figure 12-(a) shows the path delay distributions fro the predicted SSTA results based on the 9n library and the easured path delay results based on the perturbed 99n library A clear shift is visible Figure 12-(b) shows the correlation between ean cell and w Λ Because of the shift, we see that the y-ais in Figure 12-(b) shifts left Copared the result to that shown in Figure 1, we see that ecept for the shift of the ais, the low-level paraeter does not degrade the effectiveness of the ethod Nuber of paths SSTA Measured picoseconds (a) SSTA/Measured path delays (b) w Λ Vs ean cell Figure 12: Ipact of eff on the proposed ethod Noralized ean Cell = y line argest positive Noralized sv w * argest negative 55 Including net delays in the ranking As described in Section 4, the definition of a delay entity is artificial Once this definition is given, the proposed ethodology ranks Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 388

6 entities according to their iportance In the above eperients, we siply let an entity be a cell in a library We can easily etend the definition of entity to include net delays As shown in Figure 6, a net entity should include a set of nets whose routing patterns can be deeed as siilar For eaple, a group of patterns can be defined as siilar if their lithographic effects are siilar As far as our ethodology concerns, the definition of this siilarity is given by the user In the eperient described below, we take the liberty to group nets into 1 entities The assuption is that there is a systeatic tiing uncertainty on every net that belong to the sae entity Then, we would like to rank both cell and net entities together For this eperient we need odify equation 6 In addition to ean cell and ean pin for a cell entity, we include ean sys and ean ind,wheresys stands for a systeatic shift on the net delays within the net entity and ind stands for individual shift on each net delay Note that 13 cell entities and 1 net entities together give us 23 entities to rank Again, we use ±2% on the systeatic shifts and ±1% on the individual shifts as before In the following, we use ean Λ to indicate ean cell and ean sys together # of cells and nets picoseconds (a) Histogra of ean Λ Noralized ean * argest positive = y line Noralized sv w * argest negative (b) ean Λ correlates to w Λ Figure 13: Correlation between ean Λ and wλ In Figure 13-(a), we see two clear gaps at both ends on the ean Λ histogra It is interesting to observe that in Figure 13-(b), we also observe the sae two gaps at the two ends This shows again that in the SVM ranking, the ost uncertain entities stand out as outliers We also see that the ipact of going fro 13 entities to 23 on ranking accuracy is relatively sall 6 SUMMARY AND DISCUSSION Design-silicon tiing correlation can ean different things in different applications When the focus of analysis is on failing saples, diagnosis and silicon debug ai to uncover the root causes for the failures When the focus of analysis is on good and arginal chips, on-chip onitors ai to easure the effects on low-level paraeters fro process, voltage, and teperature variations When these two approaches are not applicable, the third option is to analyze delay test data While the first two approaches have been eployed in the industry for years, this paper discusses a path-based ethodology for correlating test data to tiing analysis Delay testing has traditionally been optiized for cost and for capturing defects Changes need to be ade to the tools, ethodologies and ATEs if we want to utilize delay testing for etracting design-related inforation On the ATPG side, a ore fleible odel is required for guiding test pattern generation This odel should be easily adustable by a user to target specific design aspects of interest On the ethodology side, a separate ethodology specific for design inforation gathering needs to be developed This ethodology ay need to integrate with the eisting design tools On the ATE side, a tester should allow related data to be gathered ore easily In the past few years, we have observed changes to the tools, ethodologies and ATEs to the directions described above, although they are not necessary for the purpose of etracting designrelated inforation as discussed in this paper Even with delay testing, it is ipossible to test for all design concerns left unaddressed in the pre-silicon design process Take the path-based ethodology as an eaple There are liited nuber of paths we can test at the post-silicon stage However, there are enorous nuber of cells and wires in a design It is virtually ipossible to utilize the proposed ethod to evaluate the tiing deviations for all of the This raises an iportant question for the proposed path-based ethodology That is, how to select paths? Without proper path selection, analyzing path delay data ay not help to address the key concerns In suary, an effective design-silicon correlation fraework needs to address three iportant aspects of the proble: (1) inforation content, (2) inforation decoding, and (3) application of the inforation Silicon data should contain the required inforation for analyzing the design aspects of interest Containent can be thought as if given unliited coputational resource, the required inforation can be decoded fro the data Then, efficient ethods should be developed to decode the inforation as uch as possible This inforation should be in the for that can be easily applicable This paper only discusses the second aspect and hence, the path-based ethodology is only the first step for developing a ore coprehensive correlation fraework This fraework should also be integrated with the on-chip onitor based correlation analysis as described in Figure 3 7 REFERENCES [1] ee et al On Silicon-Based Speed Path Identification, In IEEE VTS, 24, pp [2] M Abraovici, M Breuer Fault Diagnosis Based on Effect-Cause Analysis: An Introduction, In DAC 198, pp [3] Z Wang, KH Tsai, M Marek-Sadowska, J Raski An Efficient and Effective Methodology on the Multiple Fault Diagnosis, IN ITC 23, pp [4] A Kristic, KT Cheng Delay Fault Testing for VSI Circuits Boston: Kluwer Acadeic Publishers, 1998 [5] A Kristic, i-c Wang, KT Cheng, JJ ou, M Abadir Delay Defect Diagnosis Based Upon Statistical Tiing Models - The First Step, In DATE3 [6] Milor, Yu, B iu ogic Product Speed Evaluation and Forecasting During the Early Phases of Process Technology Developent Using Ring Oscillator data, Proc International Workshop on Statistical Metrology, 1997, pp 2-23 [7] D Boning, S Nassif, A Gattiker, F ui, et al Test Structures for Delay Variability Proc of the 85h ACM/IEEE TAU 22, p19 [8] M Bhushan, A Gattiker, M Ketchen, K Das, Ring oscillator for CMOS process tuning and variability control, IEEE Transactions on Seiconductor Manufacturing, Vol 19, pp 1-18, 26 [9] M Ketchen, M Bhushan, D Pearson, High speed test structures for in-line process onitoring and odel calibration, Proc IEEE Int Conf on Microelectronic Test Structures, 25 pp [1] Benain ee, i-c Wang, Magdy S Abadir Refined statistical static tiing analysis through learning spatial delay correlations, In Proc DAC 26, pp [11] Trevor Hastie, Robert Tibshirani, and Jeroe Friedan The Eleents of Statistical earning Springer Series in Statistics, 21 [12] A Agarwal, D Blauuw, and V Zolotov Statistical tiing analysis for intra-die process variations with spatial correlations, In Proc ICCAD, 23 [13] E F Schistera, et al Estiation of the correlation coefficient using the Bayesian Approach and its applications for epideiologic research, BMC Medical Research Methodology, Vol 3, 23 [14] Nello Cristianini, John Shawe-Taylor An Introduction to Support Vector Machine Cabridge University Press, 22 [15] C Visweswariah, et al First-order increental block-based statistical tiing analysis DAC, 24, pp Authorized licensed use liited to: Univ of Calif Santa Barbara Downloaded on Noveber 21, 29 at 15:1 fro IEEE Xplore Restrictions apply 389