Unified Model for Short-Channel Poly-Si TFTs

Transcription

1 Unified Model for Short-Channel Poly-Si TFT Benjaín Iñiguez, 1 Zheng Xu, 1 Tor A. Fjeldly 1, and Michael. S. Shur 1 1 Departent of Electrical, Coputer, and Syte Engineering, Renelaer Polytechnic Intitute, Troy, NY 1180 Center for Technology at Kjeller, Norwegian Intitute of Science and Technology (NTNU), N-007, Kjeller, Norway Abtract We preent a new unified odel for long and hort-channel polyilicon thin-fil tranitor (poly-si TFT) uitable for circuit iulation. The odel i baed on the effective ediu approxiation, and hould be valid for tranitor of channel length down to 1 µ. The odel account for field effect obility enhanceent in the oderate inverion regie and for obility degradation at high gate voltage, for DIBL effect, effect, off-tate current and channel-length odulation. Good agreeent between the odel and the eaureent wa found for a wide range of channel length. 1. Introduction In the lat year, there ha been a coniderable increae of the application of poly-si TFT, epecially in active atrix liquid crytal diplay (AMLCD), printer, canner, SRAM, and three-dienional LSI circuit. A a reult of the growing iportance of poly-si TFT in integrated circuit, there i a need for accurate phyic baed device odel for circuit deign and iulation. Soe of the exiting odel are too coplicated to be ipleented in circuit iulator [1, ]. Many of the analytical poly-si TFT odel, uually baed on long-channel crytalline MOSFET odel [3], do not account for all effect that are pecific for poly-si TFT. Thi include the effect, the increae of the field-effect obility a the gate voltage i increaed in oderate inverion (ince the potential barrier height i reduced), and the off-current. Thee effect have been accounted for in the odel developed by Jacunki et al. [4, 5]. However, thi odel i only valid for long-channel device. Recently a odel that include oe hort-channel effect ha been preented [6], but the DIBL (Drain

2 Induced Barrier Lowering) and velocity aturation effect have not been accounted for, and the obility degradation at high gate bia wa not conidered. Alo, the odel ue different equation for different operating regie, which i not deirable in circuit iulation. In thi paper, we preent an iproved odel for poly-si TFT that accurately odel long and hort-channel device. We include effect that were not conidered by Jacunki et al., but that are iportant even for long-channel device. Thee include obility degradation well above threhold and the DIBL effect. A dicued in thi paper, the DIBL effect in poly-si TFT i uch ore pronounced than in crytalline MOSFET and cannot be neglected even for long-channel device. Beide, the reduction of the effective depletion charge (charge haring) caue a reduction of the threhold voltage and an increae of the field-effect obility a the channel length i reduced. We alo include other effect that are ore iportant in hort-channel device, uch a velocity aturation and erie reitance. The odel include all the neceary dependencie on channel length to ake it calable fro long-channel to hort-channel device The odel ha been ipleented in the AIM-Spice circuit iulator [7, 8].. Model Forulation Mot of the analytical poly-si TFT odel are baed on the effective ediu approxiation, that treat the polycrytalline aterial in the tranitor a a unifor ediu with effective aterial propertie. Thi approxiation i only valid if the nuber of grain boundarie i high enough (uually, ore than 10 within the gate length). If the nuber of grain boundarie i very all, that i, if the channel length i hort enough, copared to the grain boundary ize, we can expect ignificant tatitical variation of perforance between tranitor of the ae ize but with different nuber of grain boundarie. In thi cae the nuber of grain boundarie doe not cale with the channel length and becaue of the poible fluctuation of their nuber in tranitor of

3 the ae ize a calable odel i not very ueful for the deign and iulation of circuit with very hort-channel tranitor. Our drain current odel i written following a copact forulation that ha been ued for other FET [7, 8]. We develop new expreion by adaptation to poly-si TFT of our unified crytalline MOSFET odel [9]. In thi odel the effect of the erie reitance i taken into account in an exact way, not a a firt-order approxiation. The drain current of the unified odel i given by the expreion: I = g ch ( 1+ λ ) 1/ [ 1+ ( g / I ) ] ch ate, (1) where i the extrinic drain-ource voltage, I i a unified expreion of the aturation current, ate i a knee-hape fitting paraeter, λ i a paraeter that account for channel-length odulation, and given by: g ch i the extrinic conductance in the linear regie g ch = g chi 1 + g ( R + R ). () chi d Here, g = qwn µ L i the intrinic channel conductance, and i the unified chi eff / n electron heet charge denity per unit area given by [7, 8]: Here, C ox n Coxη = q th log g exp ηth T. (3) i the oxide capacitance per unit area, η i the ubthrehold ideality factor, i the extrinic gate-ource voltage, theral voltage, and threhold: T i the threhold voltage, th = kbt / q g i the µ eff i a unified field-effect obility valid below and above µ = + (4) eff µ µ n

4 where µ i the ubthrehold obility, and µ n i the above threhold obility. We will ee below that our expreion of µ eff µ n. Above threhold n µ µ n ten to a very all value below threhold, o µ >>, o µ eff µ n. A explained in [4, 5], the field-effect obility odel ha to account for the increae of the threhold voltage with the gate bia in oderate inverion (or peudo-ubthrehold regie). Thi increae i caued by a decreae of the potential barrier height of the grain boundarie. The field-effect obility odel propoed in [4, 5] i: 1 = 1 µ µ FET µ 1 η gte th 1 + µ 0 (5) where gte i the effective gate bia overdrive, valid above and below threhold: gte gt gt = η th 1+ + δ + 1 (6) ηα atth ηα atth where δ, µ 0, 1 µ and are adjutable paraeter, and µ α at account for body effect a well a nonunifor doping. Fro equation (6) we have gte η below threhold and th gte ( g T )/ α at above threhold. According to equation (5), the obility hould tend towar a contant value at high gate bia. However, our experiental reult have deontrated a obility degradation with the gate voltage well above threhold. Thi cannot be attributed to the effect of the erie reitance, ince it ha been oberved alo for channel length up to 50 µ. Intead, thi effect i believed to be caued by the increae of the urface roughne cattering and the increaed urface electric field. We have oberved that the zero-bia obility (extracted fro current eaureent well-above threhold) increae a the channel length i decreaed. Thi can be related to a reduction of the urface electric field becaue of increaing charge haring (ae reaon

5 why the threhold voltage decreae a channel length i decreaed [6]). We odel thi ( ) effect a: µ µ 1+ ( L) 0 00 L µ 0 / =, where µ 00 and are adjutable paraeter. On the other hand, the obility extracted cloe to threhold ten to becoe aller than in long-channel device, ince in that regie fro ubthrehold to above threhold, obility increae with the heet carrier denity, i.e., with the urface electric field. In hortchannel device, the urface electric field i lower than in long-channel device and therefore the obility, given by ( ) uing µ µ 1 ( L) 1 10 L µ 1 / L µ0 µ gte µ 1, i lower. We account for thi effect by η th = in equation (15), where µ 10 and L µ1 are adjutable paraeter. The following expreion take the above effect into account: µ n µ FET =. (7) 1 + θ gte Here µ FET i given by equation (5). In Fig. 1 we how plot of the calculated obilitie uing (7) for different channel length. We jutify our unified obility (4) expreion. Fro (5), (6) and (7) µ µ n µ FET 1 µ 1 µ << below threhold; therefore µ eff µ. Well above threhold, µ n ha the ae order of agnitude a µ 0, which i uch larger than µ. The DIBL effect i uch ore pronounced in poly-si TFT than in crytalline MOSFET. Experientally, we have found that the decreae of the threhold voltage ha a uperlinear dependence on becaue of the DIBL effect, wherea in crytalline MOSFET, thi dependence on i linear. In particular, the threhold voltage in poly- Si TFT can be odeled a [5, 11]: T At + Bt = T 0 (8) L

6 where A and B are adjutable paraeter. The enhanceent of the DIBL effect can be explained becaue of the preence of ionized trap ite. There are two ource for the decreae of the threhold voltage with the drain-ource voltage: haring of depletion charge with the drain and ource region (a in crytalline MOSFET), and the grain barrier height lowering becaue of the lateral field [1]. The grain barrier height decreae linearly with the lateral field (which, to firt order, i proportional to the drain voltage), and caue an increae of drain current. Thi increae can be expreed a a hift in the threhold voltage; a uperlinear dependence on the drain voltage i reaonable becaue, a een in [1], of the exponential dependence of the current on the grain barrier height. t t We alo have to account for the reduction of the DIBL effect with increaing gate bia. A in crytalline MOSFET, the drain induced barrier lowering diappear well-above threhold. We can odel thi effect in poly-si TFT in a iilar way a in crytalline MOSFET [10], that i, uing a continuou function that ake tend to zero wellabove threhold: σ t A t = 1+ exp At 0 g T 0 σ σt A t σ T 0 where and are fitting paraeter that control the tranition, and i the threhold voltage for zero drain bia. Becaue of the reduction of the effective depletion charge with decreaing channel length, we can expect a decreae of the body effect paraeter, (9) α at. However, α at cannot be lower than 1 (ideal value). A uitable expreion for thi dependency, conitent with the expreion ued for threhold voltage and obility, i: ( + exp( L L) ) α = α (10) at at 0 1 C t 0 / where i a fitting paraeter and L can be aued to have the ae value a in the Ct 0 obility equation. Eq. (10) i epirical, but ha hown to reproduce the decreae of α at a L i reduced. If the channel i very long, α at α at0 + C, and therefore i t

7 independent of the channel-length, a expected fro a long-channel theory (which neglect two-dienional effect). The aturation current i given by [13, 7]: gchigte I at =, (11) gchir gte / L 1 gchi R (1 gte / L ) where = v L / µ. L eff Thi expreion i obtained fro the following velocity-field relationhip (Sodini expreion, [13]): v = d µ n dx µ n d 1+ v dx v if µ n d dx ele < v (1) where v i the aturation velocity. Channel-length odulation can be included into our odel in a ore accurate way than in (1). Fro uch an analyi (ee [14]) it i poible to how that the factor 1 + λ ) coe fro a firt-order approxiation of thi ore coplex odel. Anyway, ( if the channel odulation odel of (1) i ued, it i neceary to cale thi paraeter a λ = / L. λ 0 Paraeter, which control the tranition fro the linear regie to aturation, alo ha to be caled. A explained in [7], the tranition becoe oother, correponding to a decreae in a the channel length i decreaed. We have ued ( 1 ( L L) ) =, where and L are adjutable paraeter. 0 / 0 The total drain current i written a the u of three ter: a channel-current ter that reult fro drift-diffuion, a effect ter, 11]:, and a leakage current, [5, I I leak

8 I d = I + I + I (13) leak Nuerical iulation how that the effect ee to be deterined by the barrier lowering at the ource junction becaue of hole generated by ipact ionization, that arrive at the ource [15]. Thi i iilar to what happen in floating-body crytalline SOI MOSFET. Accordingly, recobination via trap, uggeted a the reaon for the effect in [5, 11], i not the doinant echani. However we ue the odel preented in [5, 11] for the current in the region, ince it i till copatible with the explanation of the effect given above. According to thi odel, the increae of the current due to the effect can be written a: I L e = I L exp (14) e where the ter L / L account for the feedback ( L and are extracted contant), which becoe ore iportant for horter channel length. interpolation function that ten to at, in aturation, ( ) i an in the linear regie and to the aturation voltage, e e =, (15) 1/ ( 1+ ( / ) ) where i a fitting paraeter that control the tranition fro to. Although Jacunki odel [5, 11] for the additional current due to the effect work well above threhold, it fail to predict the oberved decreae of the ideality factor in ubthrehold a at i increaed. Only a careful conideration of the coponent of the ource current can explain thi effect. The reaon of thi decreae of the ubthrehold ideality factor i the increaing potential difference between the fil and the ource, that at

9 i induced by the hole generated by ipact ionization current near the drain. According to [16], the reulting change in the ubthrehold lope i given by: η = η0 (16) b 1+ ( η0 1) g b = 0 where η 0 i the zero-bia ubthrehold lope and b i the induced bia voltage between the fil and the ource. Therefore, to odel the ubthrehold ideality factor, we need to b g expre the induced in ter of. Thi expreion i found by equating the ourcefil junction current to the ipact ionization current in ubthrehold (ince, a deontrated in [15], the hole generated by ipact ionization reach the ource where they recobine). The ource-fil junction current (at forward-bia) i given by: b I j = WJ FD exp 1, (17) th where J FD i the aturation current per unit width, and i the ideality factor of the ource junction. The ipact ionization current generated in the weak inverion regie, I, wi, wa tudied in [17] for crytalline MOSFET. Adapting that odel to poly-si TFT (in order to account for the feedback) we obtain: I, wi = L L W g exp µ coxn0 exp L ηth T (18) Equating the two current, (17) and (18), and differentiating we get at b = 0 :

10 b g b = 0 = η 0 I' I' + 1 (19) where I, wi I' =. WJ FD Therefore, the change in the ubthrehold lope due to the change in b i given by: η0 η = I' η I' η Hence, η decreae a the ipact ionization current increae, that i, when the drainource voltage increae. The above odel for η ha to be included into a unified drain current odel. Therefore, thi expreion ha to be odified in order to give the correct behavior of the drain current odel in trong inverion. A ueful unified expreion i given by: 0 (0) where η = 1+ η η0 I1 1+ I 1 η 1 0 η 0 (1) and L e W I1 = L exp () e L i conidered a a fitting paraeter. η The expreion of at to be ued to account for the ipact ionization ter can be calculated by uing I at with W L µ eff µ eff 1+ v at c ox GTe α at at at [13]. It yiel: at b + b 4c = (3)

11 where b c L 1 = WCoxα at Lv L = I Wµ C α eff ox at at W C L ox gte An expreion of e alo ha to be ued in the calculation of η. However, ince the dependence of η on e doe not allow for an analytical olution, we approxiate η by uing e obtained fro with the long-channel expreion of the aturation voltage, =, in (15) and (). at gte 3. Reult We have eaured the characteritic of tranitor of everal channel length. The polyilicon fil and the gate oxide were 100 n thick. The device it on top of an oxide ubtrate. Detail of the fabrication proce can be found in [5]. The grain boundary ize i about 0. µ. Therefore, if the channel length i a hort a µ, the nuber of grain boundarie will be about 10, and the effective ediu approach can till be applied. The paraeter are extracted fro the operating regie where they are relevant, and are hown in Table I. For oe paraeter it i poible to find initial etiate uing direct technique. After thee firt etiation are obtained, paraeter value are iproved uing a global optiization. The nuber of adjutable paraeter can only be alleviated by two-dienional odeling, needed for caling, DIBL, etc. However, paraeter have a phyical bai. The threhold voltage cannot be extracted by tandard etho for crytalline MOSFET, becaue of the interediate regie between weak and trong inverion. The threhold voltage i defined a the gate voltage at which the dependence of current on gate voltage ceae to be exponential. Inverion then tart at the urface of the grain outide the grain boundarie, but a till higher gate voltage alo the urface of the grain

12 boundarie are inverted. Thi effect i accounted for by the expreion for the obility that give an increae with the gate voltage until aturation i reached. Paraeter A t and B t are obtained fro value of the threhold voltage at different channel length and drain-ource voltage. Once we know T 0, the threhold voltage for a long-channel device at low, we obtain the quantitie A t / L and B t / L fro a linear regreion of the eaured threhold voltage veru the quare of the drain voltage (8) for a hortchannel device. Paraeter A and B are obtained fro the extracted value of and B t / L. t t A t / L The erie reitance, R, and the lateral diffuion length, L, can be extracted following the ethod of [18], provided the data ued for the extraction correpond to the linear regie well above threhold, o that the obility i only affected by degradation with gate bia. At the ae condition, we can deterine µ 0 and θ following a ethod baed on [19] and calculating, fro the value of µ 0 extracted at different channel length, µ 00 and L µ0. α at Fro the aturation regie of operation, we can obtain initial etiate of v,, and λ, following the etho reported in [7] for crytalline MOSFET. Soe paraeter value have to be choen in order to properly fit the tranition regie. Thi i the cae for µ 1 and, which deterine the odel tranition fro ubthrehold to above threhold. Thi i alo the cae of paraeter and odel the diappearance of the DIBL effect well above threhold. Finally, initial value of paraeter that deterine the effect,, L and can be obtained uing a ethod iilar to that preented by [0] to extract the ipact ionization paraeter fro the ubtrate current. µ Fig. -7 how coparion of odeled and eaured I- characteritic of tranitor of different noinal channel length and width. We have found a good agreeent with eaureent in all operating regie, fro ubthrehold to above threhold (Fig. 3, 5 and 7) and fro the linear regie to the aturation and regie (Fig., 4 and 6). Note that the DIBL effect, a well a the decreae of the ideality factor dif σ σ t

13 with increaing drain-ource voltage are properly odeled (Fig. 3). Alo, obility degradation i oberved at high gate voltage even for long-channel device (Fig. 7). 4. Concluion We have preented a coplete dc odel for polyilicon TFT that include hortchannel effect. The odel i valid in a wide range of channel length and in all operating regie. In particular it decribe well the oberved floating body effect, that are iportant for hort-channel device even in the ubthrehold regie. Furtherore, the odel exhibit continuou tranition between the different regie, which ake it uitable for circuit iulation. TABLE I. Extracted odel paraeter value. Paraeter Definition Unit alue µ 00 High field long-channel zero-bia obility µ 10 Low field obility c / c / µ Subthrehold obility c / 0. 9 η 0 Zero-bia ideality factor 7 α at0 Body effect para Long-channel zero-bia threhold voltage t0 A t0 Threhold coeff. c B t Threhold length coeff. c L µ0 0 µ length coeff. c

14 C t α length coeff at L 0 Length at which α at aturate c Electric field para. In regie L Length coeff. in regie c Long channel aturation tranition para η floating-body para η Low-field obility exponent. 9 µ Feedback exponent 1. 1 e tranition paraeter 1. 5 v Saturation velocity c/ δ gte tranition paraeter 4 λ 0 Channel-length odulation para. c/ R Paraitic ource reitance Ω 350 σ Above-threhold DIBL para σ t Above threhold DIBL para L dif Lateral diffuion length c θ Mobility degradation para L µ1 Low-field obility length para. c L length para. c FIGURE CAPTIONS Fig. 1 Calculated effective obility veru g for a tranitor with (1) L = 50 µ () L = µ uing the extracted paraeter given in Table II.

15 Fig. I v. for an n-poly-si TFT with L = µ and W = 10 µ. Solid d line: odel. Sybol: experiental. Fig. 3 I v. (logarithic cale) for an n-poly-si TFT with L = µ and d g W = 10 µ. Solid line: odel. Sybol: experiental. Fig. 4 I v. for an n-poly-si TFT with L = 4 µ and W = 10 µ. Solid d line: odel. Sybol: experiental. Fig. 5 I v. (linear cale) for an n-poly TFT with L = 4 µ and d g W = 10 µ. Solid line: odel. Sybol: experiental. Fig. 6 I v. for an n-poly TFT with L = 30 µ and W = 50 µ. Solid d line: odel. Sybol: experiental. Fig. 7 I v. (linear cale) for an n-poly TFT with L = 30 µ and d g W = 50 µ. Solid line: odel. Sybol: experiental. REFERENCES [1] R. Guerrieri, P. Ciapolini, A. Gnudi, M. Rudan and G. Baccarani, Nuerical Siulation of Polycrytalline-Silicon MOSFET, IEEE Tran. on Electron Device, vol. 33, no. 8, Augut [] A. F. M. Anwar and A. N. Khondker, A Model for Polyilicon MOSFET, IEEE Tran. on Electron Device, vol. 34, no. 6, pp , June 1987.

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