Zero-Voltage Switching Post Regulation Scheme for Multi-output Forward Converter with Synchronous Switches

Transcription

1 Zero-oltage witching Post Regulation chee for Multi-output Forward Converter with ynchronous witches Jae-Kuk Ki tudent Meber IEEE KAIT Daejeon Republic of Korea eong-wook Choi tudent Meber IEEE KAIT Daejeon Republic of Korea Gun-Woo Moon Meber IEEE KAIT Daejeon Republic of Korea Abstract -- A new ulti-output forward (MOFC) converter is proposed. It consists of four synchronous switches in secondary side for two outputs. The priary switches control the ain output voltage and the synchronous switches in transforer secondary side control the auxiliary output voltage. The ain advantages of the proposed converter are that the secondary switches can achieve the zero voltage switching (Z) at entire load conditions and the secondary rectified voltage is a three level wavefor which can reduce the output filter. The operational principle analysis and design considerations of the proposed converter are presented in this paper. The validity of this study is confired by the experiental results fro dual outputs (-8.3A and 5-6A) prototype for PC power supply. Index Ters Z ulti-output synchronous switch I. INTRODUCTION Energy conservation through equipent efficiency is an essential coponent of international efforts to slow global waring and prevent the potentially catastrophic effects of cliate change. Aong various equipents personal coputers (PCs) have becoe an indispensible appliance in hoes and offices. Thus reducing power consuption in coputers is very iportant issue. In particular PC consues an appreciable aount of power during the ties when they are not only on but are not being used. The tie that a coputer spends in this idle ode can add up to several hours of every day. Therefore power consuption in coputers can be easurably reduced by increasing the efficiency during the idle ode []. When the processor is idle the average power consuption is about 40W~00W according to the processors []. Thus the efficiency in this low power level should be increased. A switching power supply for PC generally has ultioutput structure. everal ethods have been proposed to regulate the ultiple outputs. Aong the the ethod of post regulation attracts great attention because it has the advantage of precise regulation of all outputs [3]-[]. The synchronous switch post regulator (PR) is one of the ethods that can achieve the post regulation. In the PR the MOFET seiconductor is used instead of the saturable reactor in agap regulator. The PR is easy to ipleent the protection functions and achieves good regulation over a wide range of line and load variations [3]-[5]. However despite these advantages the series connected switch and diode can increase the conduction loss and the synchronous switch also cause additional switching loss by the hard switching operation. In [8] to reduce the conduction loss the MOFET switch with low turn-on resistance is used instead of the diode to achieve the post regulation of the auxiliary output. However the switching loss still exists in the switch. In [9] instead of the rectifier diodes the synchronous switches are used for each output. To control the each output the shunt synchronous switches control the powering period so the reflected input voltage in secondary side is all applied to the decoupling inductor. Thus the priary and secondary conduction loss can be uch higher than the conventional PR circuit. Also the each shunt switch to regulate each output can not achieve the zero voltage switching (Z). In this paper a new ulti-output forward converter (MOFC) is proposed. To overcoe the above drawbacks the proposed converter has synchronous switches for low conduction loss and achieves the Z of the synchronous switches. II. OPERATIONA PRINCIPE Fig. shows the circuit configuration of the active clap forward converter with two outputs eploying the proposed regulation schee. It consists of active clap reset for Z of priary switches and synchronous switches for low conduction loss in secondary side. The ain switch Q M and the switch Q are operated in a duty ratio of D and the auxiliary switch Q A and the switch Q 3 are operated with copleentary to the switches Q M and Q. The secondary switch Q is turned on with the switch Q A siultaneously and the switch Q is operated with copleentary to the switch Q. Fig. shows the key operating wavefors of the proposed converter in the steady state. Each switching period is subdivided into nine odes. In order to illustrate the steady-state operation several assuptions are ade as follows. ) All parasitic coponents except for those specified in Fig. are neglected. ) C O and C O are sae output capacitance of C O. 3) The output voltage O and reset capacitor voltage C are constant during a switching cycle. 4) The transforer turns ratio n=n P /N =N P /N /09/$ IEEE 668

2 Fig.. Circuit diagra of the proposed Z MOFC with active clap reset. Fig.. Key wavefors of the proposed converter. 669

3 Mode [t 0 ~t ]: Mode begins when the coutations of the secondary switches are copleted. Then i o (t) flows through Q 3 and i o (t) flows through Q and Q 3. Thus the current stress of Q 3 has i o (t)+i o (t) which increases the conduction loss of the proposed converter. ince Q A is on state and Q M is off state C is applied to +. O and O are applied to O and O respectively. This causes that the output inductor currents linearly decrease. i (t) i o (t) and i o (t) can be expressed as follows: C i () t = t+ i( t0) = i() t () + where i () t = t+ i ( t ) () O o o 0 i () t = t+ i ( t ) (3) O o o 0 C i( t 0 ) = ( D) ( + ) i t I + Z I + DT Z o O o( 0 ) = O O ( ) i t I I o O o( 0 ) = O + O + ( D) Z = (Dα 3 Dα + DDα) O ( Dα Dα ) n. Mode [t ~t ]: This ode begins when Q A and Q 3 are turned off. i (t) charges C O and discharges C O siultaneously. It is assued that i (t ) is constant during this ode. Thus C O and C O are linearly charged and discharged respectively. i (t) can be expressed as follows: i ( t ) = i ( t ) (4) = ( D). ( + ) Mode 3 [t ~t 3 ]: After v QM (t) decreases to v pri (t) reaches 0. i o (t) begins to freewheel through d Q and d Q3 and i o (t) begins to freewheel through d Q Q and d Q3. Fro assuption () i (t) can be expressed as follows: i () ( )cos t = i t t. (5) CO Mode 4 [t 3 ~t 4 ]: Q M and Q are turned on with Z at t 3. The priary voltage across the transforer is still 0 and is all applied to. Therefore i (t) rapidly increases as follows: i () = t t + i ( t 3). (6) Mode 5 [t 4 ~t 5 ]: This ode begins when the coutation of Q Q d Q and d Q3 is copleted. This period is for regulating the auxiliary voltage O. ince Q is still on state i o (t) flows through Q and Q and i o (t) flows through Q. is applied to +. /n O is applied to O and /n O is applied to O. Therefore the power is transferred fro the input source to the output. i (t) i o (t) and i o (t) can be expressed as follows: where i () t = t+ i( t4) + + ( io () t + io() t ) n (7) / n O io () t = t+ io ( t4) (8) O / n i () t = t+ i ( t ) (9) O o o 4 i( t4) = D ( + ) o O o( 4 ) = O O ( ) i t I Z I DT Z i t I I. o O o( 4 ) = O O ( D) Mode 6 [t 5 ~t 6 ]: In this ode Q is turned off and Q is turned on with Z. It is assued that the coutation of i o (t) fro Q to Q occurs iediately. i o (t) flows through Q so /n O is applied to O. Therefore rec has threelevel wavefor. i (t) i o (t) and i o (t) can be expressed as follows: i () t = t+ i( t5) + (0) + ( io () t + io(). t ) n / n O io () t = t+ io ( t5 ) () / n O io() t = t+ io( t5) () where i ( t5) D + Dα ( + ) ( + ) i t I / n O O o( 5) O ( D) Z + Dα o io( t5) = I O / n I ( D) T + D T. O O O α Mode 7 [t 6 ~t 7 ]: This ode begins when Q M Q and Q are turned off. Until v pri (t) becoes 0 Q 3 and Q are still reverse biased. It assues that i (t 6 ) is constant during this ode. 670

4 Fig. 3. Gate signal of Q. Fig. 4. The secondary side circuit. (a) Proposed converter. (b) Conventional converter. Fig. 5. witching transitions of the synchronous switches. (a) Turn-on transition of Q in the proposed converter. (b) Turn-on transition of Q and Q 5 and (c) turn-off transition of Q and Q 5 in the conventional converter. Therefore C O and C O are linearly charged and discharged by i (t) respectively. i (t) can be expressed as follows: i ( t6) = i ( t7 ) (3) = D + ( io ( t6) + io( t6) ). ( + ) n Mode 8 [t 7 ~t 8 ]: When v QM (t) increases to v pri (t) reaches 0. i o (t) begins to freewheel through d Q and d Q3 and i o (t) begins to freewheel through d Q Q and d Q3. Therefore the switch Q can be turned on with Z. i (t) can be expressed as follows: i () ( 7)cos t = i t t. (4) CO Mode 9 [t 8 ~t 9 ]: Q A Q 3 and Q are turned on with Z. The voltage across the transforer is still 0 so C is all applied to. Therefore i (t) rapidly decreases as follows: i () = C t t + i ( t 8). (5) When i (t) reaches the transforer agnetizing current i (t) this ode ends. III. ANAYI AND DEIGN CONIDERATION A. DC conversion ratios The gate signal of Q is shown in Fig. 3. Q is turned on siultaneously with Q A to reduce the conduction loss. Although Q A is turned off at t the Q reains on state for the regulation of O. By controlling this period (D α T regulation period) O can be regulated. Therefore the DC conversion ratios of O and O are given as follows: O DN+ Dα N M = = (6) N P 67

5 vrec vrec vrec (N+N)/NP Dα (N+N)/NP Dα N/NP D α N/NP (D-Dα) N/NP (D-Dα) (a) (b) (c) Fig. 6. Rectified voltage v rec and output inductor current i o wavefors. (a) Proposed converter at O > N /N P and (b) at O < N /N P. (c) Conventional converter. Fig. 7. The output filter inductance o in the proposed and conventional converter. M O D( N+ N) = =. (7) N P B. Coparison of the proposed and conventional converter DC conversion ratios Fig. 4 shows the secondary side of the proposed and conventional converters. The proposed converter has siple structure. Also the nuber of the power switches has one less than that of the conventional converter. (a) Z of Q Fig. 5 shows the switching transitions of the synchronous switches in proposed and conventional converter. As shown in Fig. 5(a) in the proposed circuit after the switches Q M Q and Q are turned off at t i (t) charges and discharges the priary switches Q M and Q A respectively as shown in ode 7. At t v pri (t) and v Q (t) reach to 0 so the coutations of secondary switches start. Thus if Q can be turned on after t the Z of Q is achieved. Because the coutations io O io O io O t t t between the secondary switches always occur if there exists enough dead tie between Q M and Q A the Z of Q is guaranteed. However in the conventional converter as shown in Fig. 5(b) after the coutations occur at t v Q (t) and v Q5 (t) are not 0. This is because the output capacitors of Q and Q 5 are resonated with the transforer leakage inductance after Q and Q 5 are turned off as shown in Fig. 5(c). The turn-off voltages v pf and v pr can be expressed as follows: v v = P Pf (8) v N / N v = P P (9) Pr where N i ( t4 ') N v = ( cos ω ) + P P t sin ωt NP N N P ω =. (C O =C O5 =C O ) N CO Thus hard switching always occurs at Q and Q 5. For this reason the switching loss of the conventional converter is higher than that of the proposed converter. (b) Output filter inductance o Fig. 6 shows the rectified voltage wavefors of the proposed and conventional converter where D α is the duty N ratio of Q and Q 5 and D' α = ( D Dα). The N+ N proposed converter has two types of the rectified wavefors according to D α or secondary turns N and N. As shown in Fig. 6(a) if O > N /N P the output filter inductor current will increase during D α T. The output filter inductance is ( ) N + N O Dα NP. (0) = o As shown in Fig. 6(b) if O < N /N P the output filter inductor current will decrease during (-D α )T. The output filter inductance is O O = ( D). () o As for the conventional converter its output filter inductance is O O = ( D ' α ). () o Fig. 7 shows the output filter inductance o in the proposed converter copared to the conventional converter as a function of the range of input variation where input voltage =350~400 output O =5/6A and O =/8.3A switching frequency f =00kHz o =.A N = N = and D ax =0.4. In this specification the proposed converter includes in Fig. 6(b). 67

6 Fig. 8. The secondary turns N as a function of the secondary turns N. Fig. 0. N+ ultiple outputs. TABE I COMPONEN IT Fig. 9. The total conduction loss according to D α. The required inductance for the output inductor current ripple of.a is about 3.33uH for the proposed converter and 6.46uH for the conventional converter. Thus the proposed converter has about 9% reduced output filter inductor. I. DEIGN EXAMPE To validate the characteristics of the proposed converter siple design exaple is derived with the following specification. A. Design pecification Input voltage: = Output voltage: O =5 O = Output current: I O =6A I O =8.3A witching frequency: f =00kHz B. election of the turns ratio of the transforer The turns ratio of the transforer can be obtained by using (7). Considering the voltage stress of the priary switches Q M and Q A the axiu duty ratio D ax is about 0.4 so the turns ratio is about. C. election of the secondary turns of the transforer et O =α O then fro the DC conversion ratios (6) and (7) O D( N+ N) α = = DN + D N. (3) O α Fig. 8 shows the secondary turns N as a function of the secondary turns N. according to D α by using (3). According to D α the conduction loss can be changed. Fig. 9 shows the total conduction loss according to D α in the proposed converter. As D α decreases the total conduction loss decreases. Therefore since secondary conduction loss is doinant for high output current application the low D α and iniizing the secondary turns are desirable. When D α is selected to 0.05 N and N are turn and turns respectively.. TOPOGICA EXTENION The proposed post regulation schee can be easily extended to a large nuber of outputs by using the basic cell as shown in Fig. 0. The outerost output O(N+) is regulated by the duty ratio of the priary switches. The other output ON are regulated by the each secondary switch Q N and the Z of Q N can be achieved. 673

7 W 50W 75W 00W 5W 50W 75W 00W 5W 50W Fig.. Efficiency coparison under load variation. Fig.. Experiental wavefors at full-load condition. Fig.. Z wavefors v Q and i Q with the load variation. I. EXPERIMENTA REU A -8.3A and 5-6A prototype of the proposed MOFC has been built and tested to verify the operational principle using the coponents as shown in Table I. Fig. shows the experiental wavefors at full load condition. The voltage wavefor of Q 3 v rec is a three level wavefor. Fig. shows the voltage and current wavefors of Q with the load variation. Because Q is turned on after the coutation of the secondary switches the Z of Q can always achieved under all load conditions. Fig. 3 shows the efficiency coparison between the proposed and the conventional converter. The proposed converter has lower efficiency at heavy load conditions. This is because the current stress of Q 3 is the su of the load currents of two outputs. Thus the conduction loss in the proposed converter can be higher than the conventional converter. However as the load decreases the difference of the conduction loss reduces sharply so the switching loss can be doinant factor in light load conditions. Because the proposed converter can achieve the Z of all switches it has higher efficiency in ediu and light load conditions. As previously entioned in the introduction the power consuption in coputers can be easurably reduced by increasing the efficiency during the idle ode and in this ode the average power consuption is about 40W~00W. Therefore because the efficiency of the proposed converter is higher under about 50W the proposed Z MOFC can be desirable for PC power application. II. CONCUION A new MOFC is presented. The operational principle analysis design considerations and exaple are illustrated in this paper. The validity of the basic operational principle is verified by the experient with -8.3A and 5-6A prototype. The proposed converter features that the synchronous switch can achieve the Z under entire load conditions the secondary rectified voltage is a three level wavefor which can reduce the output filter. Fro the experiental results the proposed converter has higher efficiency in ediu and light load conditions. Therefore the proposed Z MOFC can be desirable for PC power application. REFERENCE [] F. H. Khan T. D. Geist B. airaohan B. D. Fortenbery and E. Hubbard Challenges and olutions in Measuring Coputer Power upply Efficiency for 80 Plus Certification in Proc. IEEE APEC 09 Conf. 009 pp

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