Fa st Inductance and Re sistance Extraction of 32D VLSI Interconnects Ba sed on the Method of K Element
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1 ACTA ELECTRONICA SINICA Vol. 33 No. 8 Aug K,,, (, ) : GHz,, K ( ),,,,, FastHenry : ; ; K ; ; : TN47 : A : (2005) Fa st Inductance and Re sistance Extraction of 32D VLSI Interconnects Ba sed on the Method of K Element WEI Hong2chuan, YU Wen2jian, YANG Liu,WANG Ze2yi ( Department of Computer Science and Technology, Tsinghua University, Beijing , China) Abstract : In the integrated circuits with frequency above several GHz,parasitic inductive effect has greatly influenced the cir2 cuit performance,therefore requiring efficient algorithm for extraction of frequency2dependent inductance and resistance. Based on good localization property of the K element (inverse of the partial inductance method),a fast algorithm for interconnect inductance and re2 sistance extraction is proposed in this paper. With an efficient window selection technique,filament partitioning,and two improvements on calculating filament inductance and inverting the global admittance matrix,complex structures of multilayered interconnects can be handled very well. While preserving good accuracy,the presented method exhibits about 100x speed2up over the FastHenry for some actual examples. Key words : 32D VLSI interconnect ;extraction of inductance and resistance ; K element ;high frequency ;the window technique 1, GHz., low2k,, [1,2 ].,,Ruehli PEEC(partial element equivalent circuit) [3 ],, PEEC,,.,, [4 ].,,, [5 ] Halo [6 ] Shell [7 ] (shell),., [8 ].,Devgan 2000 K [9,10 ]. K,, [10 ]., [11 ] K, 2002,, [8 ] K RKC, : ; : : 863 (No. 2004AA1Z1050) ; (No )
2 ,, [8 ] K,,,,,, MIT FastHenry [12 ] 2 K 211 K L, K L [9 ] : K = L - 1 (1) L loop = 0 0 C0-1 [9 ]., K, K, K, [8 11 ]. K : ( a) i, ( ) W i ; ( b) W i L i, i W i K, i K ( c) ( a), ( b), K K K,, RKC [10 ]. RLC, K [11 ].,, ( ( a) ) 212,. (filament),, PEEC, Y, Z. Z,, [12 ]. MIT FastHenry, [12 ]. Z = R + j L,, K = L - 1 Y = Z - 1., K, : ( a) i, ( ) W i ; ( b) W i, Z f ; ( c) i 1V, 0V, V f ; ( d) Z f I f = V f, I f ; ( e) I f, I c, I c i W i Y ( ) ; ( f) I c Y Y all, i Y ; ( g) ( a) ( f ), Y all ; ( h) Y all, Z all = Y - 1 all. Z all,, Y K,, ( a), ( b) ( h) 3,,,, ;,. [8 ],,,,.,,, (, ).,, 1 1 Y, XOY, a b c d. XOY, [8 ], x, x, X
3 8 : K 1367 ( ),. : ( a) XOY, YOZ ZOX,, i xy i XOY ( b) XOY X Y, YOZ ZOX, 6 ( c) XOY X, i, : ( i) j = i + 1, j xy i xy ; ( ii) j xy i xy, j xy i xy, j = j + 1, ; ( iii) j xy k xy, k xy i xy, k i j i, j = k, ; ( iv) j xy ( i xy, x ), j xy i xy min{ } + 1. j xy, ; ( v) ( i) ( iv), i xy, i xy s xy i xy i xy s xy, ( d) 5 ( c) i j,. 1 XOY, a,, ( ) ; b, ( iv) 1; c, d c ( ), c, d, d 1; c, d, b d, c ,, Zf,, [10 ] : L ij = l i l j dv 4 a i a j Vi Vj r i - r j j dv i (2), V i V j i j, a i a j, l i l j, r i r j i j, A B, A B (2), A B C D, A B C D, ( 2). A B C D,, FastHenry, 9, 6, 3.,, 9,, 9,, (2),,,.,,,, 3, D1 D2 D3 D4 C, 2 2 (2), C D1, D2 D3 D4 ( 3 ).,,,,.,,.,, 6,
4 , 3, 4 ( ). (2).,, Z f 412 Y all, Z all., ( ),, Z all, : X, Y, ( ). 5, I X, II Y, III,, Y ( 3 ), 5, I II Y,,, I II,, III. 5 FRLE(Fast Resistance and Inductance Extractor),, FastHenry, Sun Ultra V880 ( 750 MHz) 1 VLSI, 5 P/ G, 2 m, P/ G 10, 0. 4 m, 2 m, 60 m,,, 0. 8 m, P/ G 2 m. 6, X, Y, 4 m ( 6 ). 10GHz, 4 4, 6, x = , 4 FRLE, 4 FastHenry, 2 ( ),, 1 1 Y (s) FastHenry FRLE( ) FRLE( ) ( FastHenry ) < 3 % 3 % 6 % 6 % 9 % 9 % 12 %12 % 15 % > 15 % % % 9. 3 % % % % % % Y (s) FastHenry FRLE( ) FRLE( ) ( FastHenry ) < 3 % 3 % 6 % 6 % 9 % 9 % 12 % 12 % 15 % > 15 % ( ) % % % % % 0 ( ) % % % % 0 0 ( ) % % % % % 0 ( ) % % % % 0 0 1, FRLE FastHenry 100, Y,, Y,, 2 2,FRLE (, ). 2, 260, X 150, Y 30, GHz, 4 (4, 3, x = FRLE , FRLE FastHen2 ry 78, 4. 4, FRLE, 2,
5 8 : K 1369 Z 6 K., Y,,,, FastHenry, K,,, : [ 1 ] K Gala,D Blaauw,J Wang,et al. Inductance 101 :analysis and design issues[a]. Proc. Design Automation Conference[ C]. New York,USA : ACM press, [ 2 ] M W Beattie,L T Pileggi. Inductance 101 : modeling and extraction [A]. Proc. Design Automation Conference[ C]. New York,NY,USA : ACM press, [ 3 ] A E Ruehli. Inductance calculation in a complex integratd circuit envi2 ronment[j ],IBM Journal of Research and Development,1972,16 : [ 4 ] Z He,M Celik,L T Pileggi. Spie :Sparse partial inductance extraction [A]. Proc. Design Automation Conference [ C]. New York,NY,USA : ACM press, [ 5 ] K Gala,V Zolotov,R Panda,et al. On2chip inductance modeling and analysis[ A ]. Proc. Design Automation Conference [ C ]. New York, NY,USA :ACM press, [ 6 ] KL Shepard,Z Tian. Return2limited inductances :a practical approach to on2chip inductance extraction [J ]. IEEE Trans omputer2aided De2 sign,2000,19 (4) : [ 7 ] M W Beattie,L T Pileggi. Modeling magnetic coupling for on2chip in2 terconnect [ A ], Proc. of Design Automation Conference [ C ]. New York,NY,USA :ACM press, [ 8 ] T 2H Chen,C Luk,H Kim,et al. INDUCTWISE: Inductance2wise in2 terconnect simulator and extractor [ A ]. Proc. IEEE International Con2 ference on CAD[ C]. Los Alamitos,Calif,USA : IEEE Computer Society press, [ 9 ] A Devgan,H Ji,W Dai. How to efficiently capture on2chip inductance effects: Introducing a new circuit element K[ A ]. Proc. IEEE Interna2 tional Conference on CAD[ C]. Los Alamitos,Calif,USA : IEEE Com2 puter Society press, [ 10 ] H Ji,A Devgan,W Dai. KSim :A stable and efficient RKC simulator for capturing on2chip inductance effect [ A],Proc. ASP2DAC[ C]. New York,NY,USA :ACM press, [ 11 ] M Beattie,L T Pileggi. Efficient inductance extraction via windowing [A]. Proc. Design Automation and Test in Europe[ C]. Piscataway NJ, USA :IEEE press, [ 12 ] M Kamon,M J Tsuk,J White. FASTHENRY:A multipole2accelerated : 3D inductance extraction program[j ]. IEEE Trans Microwave Theory Tech.,1994,42 (9) : ,1978,,. E2mail tsinghua. edu. cn.,1977,,, VLSI,1977,,.,1940,,, VLSI,.
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