How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K

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1 How to Efficientl Capture On-Chip Inductance Effects: Introducing a New Circuit Element K Anirudh Devgan Hao Ji Wane Dai IBM Microelectronics UC Santa Cruz CE Dept. UC Santa Cruz CE Dept. Austin, TX 5 Santa Cruz, CA 95 Santa Cruz, CA 95 devgan@us.ibm.com hji@cse.ucsc.edu dai@cse.ucsc.edu Abstract On-chip inductance etraction and analsis is becoming increasing critical. Inductance etraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path which is tpicall unknown prior to etracting and simulating the circuit model. In this paper, we propose a new circuit element, K, to model inductance effects, at the same time being easier to etract and analze. K is defined as inverse of partial inductance matri L, and has localit and sparsit normall associated with a capacitance matri. We propose to capture inductance effects b directl etracting and simulating K, instead of partial inductance, leading to much more efficient procedure which is amenable to full chip etraction. This proposed approach has been verified through several simulation results. Introduction Increasing clock speeds, die sizes, and power dissipations have driven VLSI manufacturers to abandon the simple scaling approach of interconnect wiring. Instead, the emplo a hierarch of metal wiring levels. Thinner wiring levels are used at the circuit level where densit is required, and thicker laers at the top or global levels in order to route low-skew clock trees, low-loss power distribution buses, and the fastest signal interconnects. This trend, coupled with the recent introduction of copper wiring (because its resistivit is approimatel half that of aluminum wiring) has made on-chip inductance modeling necessar for clocks and the fastest signal interconnects. Inductance etraction is difficult because mutual inductance depends on the current return path which is unknown prior to etracting and simulating a circuit model. Rosa introduced the concept of partial inductances to avoid this difficult b assuming that each segment has a return current at infinit []. Ruehli introduced partial inductance to modern ICs and proposed the PEEC (Partial Equivalent Element Circuits) model to handle general three dimensional interconnects [, ]. Kamon, et al more recentl de- This work was supported, in part, b IBM Corporation and Ultima Interconnect Technolog, Inc. veloped the algorithm, FastHenr [5], to solve for effective inductance from partial inductances with multi-pole acceleration. Nonetheless, the partial inductance approach, which assigns portions of the loop inductances to segments along the loop, results in a large, densel-coupled network representation, which makes subsequent circuit simulation practical onl for small eamples. Moreover, unlike capacitance matrices which can be truncated to represent onl localized couplings, simpl discarding distant mutual inductances can result in an unstable equivalent circuit model (positive poles) []. As an alternative to simple truncation, a shift-truncate potential method was proposed b Krauter, et al [, ]. This shift-truncate potential method assumes that segment currents return at a finite radius r, instead of infinit. Therefore, segments spaced more than r apart have no inductive coupling. This technique can guarantee to generate positive definite sparse approimations of the original partial inductance matri. Nevertheless, to determine a proper value of r to ensure a desired accurac involves complicated schemes and iterations. Moreover, this approach does not work well for long wires. Shepard, et al proposed the concept of return-limited loop inductance to sparsif the partial inductance matri []. It is based on the assumption that the currents of signal lines return within the region enclosed b the nearest same-direction power-ground lines. However, this ma not be true when power-ground lines are of same order of dimensions as signal lines. Recentl, Lin developed the mutual inductance screening rule [9]. Since this rule basicall discards the consideration of circuit topolog, it cannot be applied to some comple interconnect topolog, such as mesh ground plane []. Thus, unlike capacitance etraction, where onl the nearest neighbor conductors need to be considered, in inductance etraction, a large number of conductors are involved. Techniques used in capacitance etraction, such as librar construction and analtical formulas cannot be applied to inductance etraction. However, although C matri is sparse, the inverse of C has been observed to be dense. We speculated that if L is dense, then the inverse of L ma be sparse. In this paper, we introduce a new circuit element to represent inductance

2 effect, while still preserve localit for large sstems. This new circuit element, K, is basicall the inverse of partial inductance. Therefore, we proposed to capture on-chip inductance effect b directl etracting and simulating K, instead of partial inductance. Since K has localit, we onl need to consider a small number of neighbors. As the result, the K matri for circuit simulation is ver sparse. Thus it can save a great amount of CPU time and memor usage when capturing on-chip inductance effect. Moreover, we can further construct libraries or analtical formulas for K,which will enable this K-based method to be a practical one to predict and capture inductance effect for the whole chip. This new concept has been verified b the simulation results of practical eamples. Partial Inductance Since our proposed K is defined as the inverse of the partial inductance, we begin with a brief review of partial inductance. It s well known that inductance is a propert of closed loops. Since for on-chip interconnects, the induced current return paths are unknown, the prevailing inductance models are built on partial inductance concepts. Partial inductance are best understood in terms of the normalized magnetic vector potential drop along a conductor segment due to current in that, or another segment. Consider the two conductor segments, i and j, as shown in Fig.. A jj a b I j A ij c d Figure : Partial inductance associated with magnetic vector potential drop along the conductor segments. Both segment loops are assumed to close at infinit. The partial inductance L ij between segment i and j is given b h R i ai ai Rlj A ij dl i da i L ij = () I j where A ij is the magnetic vector potential along segment i due to the current I j in segment j. Segmenti has a cross section a j. In magneto-statics, the relationship between the magnetic vector potential A ij and the current I j is given b " Z Z # A ij = I j dl j da j () a j aj lj r ij where r ij is the geometric distance between two points in segment i and j. Substitute Eq. () into Eq. (), we can get " Z Z Z Z # L ij = dl i dl j da i da j () a i a j r ij ai aj li The partial inductance matri for a set of n conductors is an nn real smmetric matri. The corresponding linear sstem is given b L L L L.. L nn I.. 5 I n lj 5 = np a i= np i= an R Ai dlda.. R Ani dl n da n From Eq. (), we can see that the partial inductance L ij onl depends on the relative position and length of segment i and j, and is independent of the eistence of other conductors. That is to sa, the eistence of other conductors has no shielding effect on the inductive coupling between segment i and j, under this partial inductance definition. Furthermore, since the integral kernel of L ij is r ij, the off-diagonal elements in the partial inductance matri decrease ver slowl (at the order of log r ij ) with the increase of spacing r ij. Because of this long range inductive coupling effect for partial inductance of on-chip wires, capturing inductive couplings becomes much more difficult than capturing capacitive couplings, which is known to be local. Moreover, it is understood that making the matri sparse b merel discarding the smallest terms can render the matri indefinite and thereb introduce positive pole(s) in subsequent circuit simulations. Circuit Element K. Definition of K [K] is defined as inverse of partial inductance matri [L]. [K] =[L], (5) This definition originated from the well known relationship between capacitance and inductance for transmission line structures, () [L loop ]=[C], () where and are permittivit and permeabilit in free space, respectivel. [C] is the capacitance matri which would result if all dielectric laers were replaced b free space. This relationship inspired us that for structures other 5

3 than transmission lines, although the inverted inductance matri, [K] (or [L], ), is not proportional to capacitance matri, [C], [K] ma still have similar local propert as [C]. If this is true, then we can appl K etraction locall, and derive RKC equivalent circuit models, instead of RLC models to model the inductance effect. Here, we should emphasize that [L loop ] have complete different meaning with [L]. The element in [L loop ] is loop inductance, and it was calculated with a pre-defined ground return path. That is to sa, there is onl an (n, ) (n, ) [L loop ] matri for an n conductor sstem. While the element in L matri is partial inductance, and it was assumed all current return in infinit. For an n conductor sstem, an nnlmatri is obtained. Therefore,although, the K matri has similar localit as the C matri, it is not related to the capacitance matri.. Localit of K The following eample demonstrate the localit of K matri. Consider a laout eample with five parallel buses, shown in Fig.. The length of all buses is m, the cross section is m, and the spacing between the buses is 5 m. h w l s 5 Figure : Laout Eample with 5 Parallel Buses We calculated the partial inductance matri, L, using FastHenr [5], [L] = : : :5 :9 : : : : :5 :9 :5 : : : :5 :9 :5 : : : : :9 :5 : : and then inverted L to get K matri. [K] = 5,:,:,:,:,:,:,:,:,:,: 5,:,:,:,:,:,:,:,:,:,: ph; () () From Eq. () and Eq. (), we can see that the partial mutual inductance L5 is./. or :% of the partial self inductance L, while jk5j is onl./ or :% of the self term K. Meanwhile, we also calculated the capacitance matri of the above structure shown in Fig. using FastCap []. [C] = 555,,:,:5,:9,,,:,:5,:,,,:9,:5,:,,,:9,:5,:9, H, Eperiment Results 5 pf (9) It can be observed the amazing similarit of the decreasing trend of the off-diagonal elements in both K and C matri. For eample, the absolute value of mutual capacitance jc5j is about.9/555or:% of the self capacitance C. That is to sa, the off-diagonal elements in K matri decrease faster than that of the partial inductance matri, and at a similar speed as that in capacitance matri, which we call K matri has localit. The phsical eplanation of this localit for K matri is provided in [].. K-based method Since K has localit, we onl need to consider a small number of conductors enclosed in small window when etracting K. Our approachcan be summarizedas follows. Calculate the partial inductance matri, L, of a small structure which is enclosed in a small window. Calculate the small K matri b inverting the corresponding L matri. Compose the big K all matri b the column in each small K matri, which is corresponding to the aggressor, like the techniques used in capacitance etraction. Simulate the subsequent RKC equivalent circuit. As we mentioned before, in order to be a practical approach, K-based method has to guarantee the stabilit of the subsequent RKC equivalent circuit. The proof of the stabilit abide b the following steps []: K matri in general is diagonal dominant. The sparse K all matri constructed b K-based method is still diagonal dominant. K all matri is positive definite. Therefore, the subsequent RKC equivalent circuit is stable. Due to space limitation, please reference [] for detailed proof. Therefore, for a large sstem, K-based method will generate a ver sparse and stable sstem in later circuit simulation. Thus it can save a great amount of CPU time and memor usage when capturing on-chip inductance effect. To simpl illustrate the accurac of K-based method, we still use the 5 parallel buses eample shown in Fig.. We calculate the loop inductance between bus and 5 with and without the coupling term K5. That is we calculate the loop inductance between bus and 5 associated with matri [K] and [K ], stated in Eq. and Eq., respectivel. Since directl calculating loop inductance using K

4 matri involves complicated calculation, we use the corresponding partial inductance matrices, [L] and [L ], stated in Eq. and Eq., respectivel. [K ]= [L ]=,:,:,:,:,:,:,:,:,: 5,:,:,:,:,:,:,:,:,: : : : : :9 : : : : : : : : : : : : : : : :9 : : : : 5 ph; () () As we all know, L loop5 = L + L55, L5, L5. With the coupling term K5, wegetl loop5 = (:, :) = :ph. Without the coupling term K5, we get L loop5 = (:, :9) = :ph, whichis.9% more than the eact value L loop5. However, if we approimate L loop5 b directl ignoring L5 in [L] matri, we will get L loop5 =: =:ph, which is.% overestimation, a much larger error compared to K-base method. Net, consider the two power planes depicted in Fig.. This is the same eample presented in Fig. 5 of []. When power plane inductance and K matri are modeled, power planes such as these are meshed into separate and conductor segments. (Even solid power planes are meshed into separate and conductors.) Because orthogonal conductors do not couple magneticall, the resulting inductance matri and K matri are block diagonal matrices. plane thickness =.5 mm meshed into equal mm square segments along the direction, and uniform current flow was assumed along all segments (FastHenr parameters nhinc and nwinc were set to one). Firstl, to visualize the decrease speed of the off- 5 9 H, diagonal elements in L matri and K matri, we plotted the normalized mutual couplings between the left-bottom most segment and other segments in the same power plane with respect to the self term of the left-bottom most segment for both L and K matri, depicted in Fig. and Fig. 5, respectivel. We observed that the off-diagonal elements in K matri decrease much faster than those of the partial inductance matri, which again illustrated the localit of K matri compared to L matri. Since K has localit, we onl need to consider a small number of conductors enclosed in small window when etracting K. Normalized mutual L i vs. L.... Figure : Normalized mutual couplings between the leftbottom most segment and other segments in the same power plane with respect to the self term of the left-bottom most segment for L matri z cm cm. mm Figure : Two Power Planes for Inductance Effect Modeling Normalized mutual L i vs. L.... To compare our approach with the conventional and the shift-truncate method in [], we calculate the eigenvalues of partial inductance matri in the conventional and the shift-truncate method b strictl following Krauter s paper []. That is, for the two planes depicted in Fig., we created, using FastHenr [5], a partial inductance matri to model the magnetic coupling in the direction. Each plane was Figure 5: Normalized mutual couplings between the leftbottom most segment and other segments in the same power plane with respect to the self term of the left-bottom most segment for K matri

5 Secondl, from this FastHenr partial inductance matri, we created two sparse approimations of the full matri. The first approimation was formed using the shifttruncate procedure. That is, we set the current return radius r equal to mm, and when the result was negative, the matri term was set to zero. The projection on - coordinate of the small representing structure enclosed in the current return shell is shown in Fig.. cm also betheinverseof thoseof L matri. For better illustration, we plotted the inverse of K s eigenvalues in Fig.. In observing Fig., note that the approach of simpl discarding the smallest terms in the inductance matri, ields both an inaccurate and an unstable approimation as it fails to match the eigenvalues of the full matri at both etremes and in the middle. Although the smallest eigenvalues of the shift-truncate method match those of the full L matri, and shows the same discontinuous jump between the th and st eigenvalue, there are significant difference for larger eigenvalues between the shift-truncate method and the full matri. r cm e-.5e- full L matri sparse K matri current return shell Figure : The Representing Structure in Modeling the Two Power Planes eigenvalues (H) e- 5e-9 The second sparse approimation was formed b discarding all mutual inductances less than.5 nh. In both cases,, of the total, matri terms were set to zero, (i.e. both approimations were > 95% sparse). Finall, the eigenvalues of the full matri and the two sparse approimations were computed. The eigenvalues for each matri are plotted in Fig.. e- -5e-9 eigenvalue # Figure : Eigenvalues for Full L matri and 95% Sparse K Matri Modeling the Two Power Planes in Fig. eigenvalues (H).5e- e- 5e-9 full L matri truncation onl shift-truncation -5e-9 eigenvalue # Figure : Eigenvalues for Full and 95% Sparse L Matrices Modeling the Two Power Planes in Fig. In our K-based approach, we calculated the K matri of the conductor segments included in the small window as those enclosed in the current return shell in shift-truncate method to ensure same sparsit. Therefore, the whole K sstem has eactl same sparsit (> 95%) as those in shifttruncate and truncation onl method. Since K matri is the inverse of L matri, the eigenvalues of K matri should Fig. shows the ecellent match of the eigenvalues between sparse K matri and full L matri. Finall, to compare the effects of full inductance matri and sparse K matri in circuit simulations, we choose a structure presented in Fig. (b) of Krauter s paper []. The circuit is illustrated in Fig. 9. We deliberatel chose this circuit topolog because the current loops were larger than that in Fig. (a) of Krauter s paper []. Thus, it will be more obvious whether or not the K-based method can capture enough mutual inductance coupling. In this structure, each conductor has cross section of m square, d =m, d =m, and d = m. Each conductor was broken into fort equal segments in order to create a large et illustrative partial inductance matri. To make the inductive effects dominate, R s and R t were set to and ohms, and a rise time (.ns) was emploed to simulate the frequenc of on-chip interconnect application. In our approach, the window size was assumed to include at most segments of each conductor. The sparsit of the resulted K matri is about 9.%. The circuit simulation is performed b Ksim [], which simulates RKC equivalent circuit, instead of RLC. The simulation results is shown in Fig.. We can see good agreement in terms

6 R s d d Figure 9: Circuit Eample same as Fig. from Krauter s paper[] of circuit simulation results between the full L matri and the sparse K matri. V_ (V).... d Simulation results of V_ for full matri and sparse matrices modeling the circuit with conductors. input full L matri K-based method time (ns) Figure : Simulation Results for Circuit Eample in Fig. 9 5 Conclusion Partial inductance are etremel useful in modeling circuit inductances when the induced current loops are unknown. Unfortunatel, these matrices are dense and def conventional simplifications (i.e. the smallest matri cannot be indiscriminatel discarded). In this paper, we introduce a new circuit element, K, as the inverse of partial inductance. We found out that K is capable of capturing inductance effect, while still preserve localit. Since K matri is a sparse diagonall dominant matri, we onl need to consider a small number of neighbors. Therefore, we proposed to capture on-chip inductance effect b directl etracting and simulating K, instead of partial inductance. As the result, the K matri for circuit simulation is ver sparse. Thus it can save a great amount of CPU time and memor usage when capturing on-chip inductance effect. This new concept has been verified b the simulation results of practical eamples, and showed remarkable accurac over other sparsification techniques, such as the shift-truncate method and R t truncation onl method. We further understand the phsical meaning of K and the reason that K has local propert []. Most importantl, it can be proved that the sparse sstem matri constructed b ignoring far awa mutual K is positive definite []. Therefore, we can later construct libraries or analtical formulasfor K, which will enable this K-based methodto be a practical one to predict and capture inductance effect for the whole chip. References [] H. Ji, A. Devgan, and W. Dai, Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect, UCSC Technique Report, UCSC-CRL- -, Apr.. [] E. Rosa, The self and mutual inductance of linear conductors, in Bulletin of the National Bureau of Standars, pp., 9. [] A. Ruehli, Inductance calculations in a comple integrated circuit environment, IBM Journal of Research and Development, pp., Sept. 9. [] A. Ruehli, Equivalent circuit models for threedimensional multiconductor sstems, IEEE Trans. on MTT, pp., Mar. 9. [5] M. Kamon, M. J. Tsuk, and J. K. White, FAS- THENRY: A multipole-accelerated -D inductance etraction program, IEEE Trans. on MTT, pp., Sept. 99. [] Z. He, M. Celik, and L. Pileggi, SPIE: Sparse partial inductance etraction, in Proc. -th Design Automation Conference, pp., June 99. [] B. Krauter and L. Pileggi, Generating sparse partial inductance matries with guaranteed stabilit, in Proc. IEEE International Conference on Computer Aided Design, pp. 5 5, Nov [] K. L. Shepard and Z. Tian, Return-limited inductances: A practical approach to on-chip inductance etraction, in Proc. IEEE Custom Integrated Circuits Conference, pp. 5 5, 999. [9] S. Lin, N. Chang, and S. Nakagawa, Quick on-chip self- and mutual-inductance screen, in Proc. IEEE st International Smposium on Qualit Electronic Design, pp. 5 5, Mar.. [] K. Nabors and J. K. White, FastCap: a multipole accelerated -D capacitance etraction program, IEEE Trans. on CAD, pp. 59, Nov. 99.