Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits

Transcription

1 Engineering Letters, 6:, EL_6 ost Reduction in Nearest Neighbour ased Synthesis of Quantum oolean ircuits Mozammel H.. Khan bstract Quantum computer algorithms require an oracle as an integral part. n oracle is a reversible quantum oolean circuit, where the inputs are kept unchanged at the outputs and the functional outputs are realized along ancillary input constants or. Recently, a nearest neighbour template based synthesis method of quantum oolean circuits has been proposed to overcome the adjacency requirement of the input qubits of physical quantum gates. The method used SWP gates to bring the input qubits of quantum NOT or NOT gates adjacent. In this paper, we propose cost reduction techniques such as ancillary constant determination to reduce the number of NOT gates and variable ordering and product grouping to reduce the number of SWP gates required in nearest neighbour template based synthesis. The proposed approach significantly reduces the quantum realization cost of the synthesized quantum oolean circuit than that of the original nearest neighbour template based synthesis. Inde Terms ncillary constant determination, nearest neighbour template, product grouping, quantum oolean circuit, fied polarity Reed-Muller epression, reversible logic, variable ordering I. INTROUTION Quantum computer algorithms require a black bo called oracle. n oracle is a reversible quantum oolean circuit, which takes a set of inputs and produces a set of functional outputs. The inputs are kept unchanged at the outputs and the functional outputs are generated along ancillary input constants or. Thus, if the oracle has n inputs and m functional outputs, then the oracle is realized as a n + m-qubit reversible quantum oolean circuit [], where the circuit has n + m inputs and outputs. Therefore, synthesis of reversible quantum oolean circuit is very important in quantum computation. Younnes and Miller [] introduced representation of oolean quantum circuits as Reed-Muller epression using k + -qubit k NOT gates. However, physical realization of k NOT gate for k > is practically very difficult and this physical constraint requires that quantum oolean circuit be synthesized using k NOT gates with k. k + -qubit k NOT gate has k controlling inputs and one target input. The target qubit value is inverted if and only if all the controlling qubit values are. Physical realizations of these quantum gates require that the controlling qubits and the target qubit be physically adjacent []. This constraint also requires that, Manuscript received ecember, 7. Mozammel H.. Khan is with the epartment of omputer Science and Engineering, East West University, 4 Mohakhali, haka, angladesh, phone: ; fa: ; mhakhan@ ewubd.edu. in a quantum oolean circuit, the controlling qubits and the target qubit of a quantum gate must be brought to physically adjacent position using quantum SWP gates. For this purpose, hakrabarti and Sur-Kolay [4] introduced a nearest neighbour template based synthesis, where the controlling qubits and the target qubit are brought to adjacent positions by using quantum SWP gates. They also used a quantum gate library consisting of only NOT, NOT, NOT, and SWP gates to overcome the physical realization problem with k >. In this nearest neighbour template based synthesis, besides NOT, NOT, and NOT gates, a large number of SWP gates are needed. In the present paper, we have reduced the number of SWP gates by using variable ordering and product grouping techniques. We have also reduced number of NOT gates by judicious determination of ancillary constant value. The rest of the paper is organized as follows. We introduce NOT, NOT, NOT, and SWP gates in Section II. Then we discuss Reed-Muller epressions of a oolean function in Section III. In Section IV, we discuss quantum gate network for fied polarity Reed-Muller FPRM epression and also discuss the ancillary constant determination to reduce the number of NOT gates. We then discuss nearest neighbour template based synthesis of quantum gate network for FPRM epression from [4] in Section V. In Section VI, we propose variable ordering and product grouping techniques to reduce the number of SWP gates in nearest neighbour template based synthesis of quantum gate network. We calculate quantum gate counts and quantum realization costs of several FPRM epressions and compare with that of [4] in Section VII. Finally, in Section VIII, we conclude the paper. II. SOME QUNTUM GTES In the nearest neighbour template based synthesis of [4], a quantum gate library consisting of NOT, NOT, NOT, and SWP gates is used. In this section, we introduce these gates. These gates are shown in Figure. The NOT gate maps the input, where the symbol represents the EXOR operation. The NOT gate inverts the input qubit value at the output. The NOT gate maps two inputs, y, y, where is the control input and y is the target input. The NOT gate inverts the target qubit value at the output if and only if the control qubit value is. The NOT gate is also known as Feynman gate. The NOT gate maps three inputs, y, z, y, z y, where the product represents the N operation. Here, and y are control inputs and z is target input. NOT gate inverts the target qubit value at the output if and only if both the control qubit values are. We refer the two control lines of a NOT gate as top control line dvance online publication: 9 February 8

2 Engineering Letters, 6:, EL_6 and bottom control line. NOT gate is also known as Toffoli gate. The SWP gate maps two inputs, y y,. SWP gate echanges the two qubit values at the output. NMR based implementation costs of these gates are as follows [4, 9, ]: ost of NOT gate = ost of NOT gate = 5 ost of NOT gate = 5 ost of SWP gate = 5 f = polarity 4,,,, f = polarity 4 5 f,, = polarity 5 6 f,, = polarity 6 7 f,, = polarity 7 8 y y y y y z z y y a b c d Figure. a NOT gate, b NOT gate, c NOT gate, d SWP gate III. REE-MULLER EXPRESSION OF OOLEN FUNTION In [] and also in the nearest neighbour template based synthesis of [4], a oolean function is represented by its Reed-Muller epression and then the Reed-Muller epression is realized using quantum k NOT gates. In this section, we discuss Reed-Muller epressions of a oolean function in brief. There are many canonical two-level N-EXOR epressions for a given oolean function [5]. mong them positive polarity Reed-Muller PPRM epression and fied polarity Reed-Muller FPRM epressions are very popular. In the PPRM epression, all the variables appear in uncomplemented form throughout the N-EXOR epression. In the FPRM epression, a variable appears either in complemented form or in uncomplemented form throughout the N-EXOR epression. If a variable appears in uncomplemented form, we say that its polarity is and if the variable appears in complemented form, we say that its polarity is. If a oolean function has n variables, then the n-tupple of the variable polarities represent the polarity of the FPRM epression. s there are n possible choices of polarity for an n-variable oolean function, there are n possible FPRM epressions for the function. In this respect, the PPRM epression is an FPRM epression with polarity. There are several methods of converting a oolean function into a given polarity FPRM epression [6-8]. Here, we will not discuss the methods and the readers may see the references. The 8 possible FPRM epressions for the oolean function f,,,5,6,7 are given below:,, = = f = polarity f,, = polarity f = polarity,, These FPRM epressions are used in [4] to illustrate the nearest neighbour template based synthesis. We will also use these FPRM epressions for our eamples. IV. QUNTUM GTE NETWORK FOR FPRM EXPRESSION In [4], an n-input single-output FPRM epression is realized using the quantum gate network model of Figure, where to n are the n function inputs and the functional output f is realized along an ancillary constant input c =. In the quantum gate network of an FPRM epression, the complemented variables are first realized using NOT gates. Then, the first product term from the FPRM epression is realized using the control inputs of a k NOT gate and the product is EXORed with ancillary constant using the target input of the gate. The net product term from the FPRM epression is realized similarly and then EXORed with the previous product term which is the target output of the previous k NOT gate using another k NOT gate. In this way, EXOR sum of all the product terms are realized. Then, if the FPRM epression has a constant as in, 6, 7, and 8, then another NOT gate is placed along the output f since, =. Finally, the complemented variables are restored using NOT gates. The quantum gate network for FPRM epression f,, = of 7 is shown in Figure. Readers can see [4] for quantum gate networks for FPRM epressions of,,, 4, 5, 6, and 8. In [4], the ancillary constant c is assumed to be. The problem of this assumption is that if an FPRM epression has a constant as in, 6, 7, and 8, then an additional NOT is required. This NOT gate can be omitted if we assume c = for these cases. This rule can be generalized as Rule ncillary constant determination: If an FPRM epression has a constant in the epression, then assume c =, otherwise assume c =. n n M M c f Figure. Model of quantum oolean circuit To describe the quantum gate network of Figure, we number the input lines from onward starting from the target dvance online publication: 9 February 8

3 Engineering Letters, 6:, EL_6 input ancillary constant. We also assume that quantum gates are placed one after another from left to right. We describe a gate in the quantum network using the line numbers as follows: NOTline number, NOTcontrol line number, target line number, and NOTtop control line number, bottom control line number, target line number. For eample, the first NOT gate from the left in Figure is described as NOT,,. Using this convention, we describe the quantum gate network of Figure as f = NOT NOT NOT,, NOT,, NOT, NOT, NOT NOT The nearest neighbour templates require a large number of SWP gates. In [4], rules for calculating the number of SWP gates are given, but the rule statements are ambiguous and do not directly agree with the eamples. However, the eample calculations are correct. Here, we state rules for calculating SWP gates very clearly. Rule Number of SWP gates needed for NOT gate: Let, in a NOT gate, t be the top control line number and b be the bottom control line number. Then the number of SWP gates required to bring the control inputs adjacent to the target input is t + b. Line no f Figure. Quantum gate network for FPRM epression f,, = V. NEREST NEIGHOUR TEMPLTE SE SYNTHESIS OF QUNTUM GTE NETWORK FOR FPRM EXPRESSION Reader can see that, in Figure, the control lines of NOT,, gate are adjacent but they are not adjacent to the target line. Similarly, the control line of NOT, and NOT, gates are not adjacent to the target line. The control lines of these gates are to be brought adjacent to the target line using SWP gates. In [4], nearest neighbour templates are introduced for this purpose as shown in Figure 4. We describe a SWP gate as SWPtop line number, bottom line number. Then, we can describe the templates of Figure 4 as Eample: For NOT,, gate, t = and b =. Then the number of SWP gates needed is + = 4. Rule Number of SWP gates needed for NOT gate: Let, in a NOT gate, c be the control line number. Then the number of SWP gates required to bring the control input adjacent to the target input is c. Eample: For NOT, gate, c =. Then the number of SWP gates needed is = 4. Now, if we replace the NOT,,, NOT,, and NOT, gates of Figure by their corresponding templates, we get the quantum gate network of Figure 5, which requires additional SWP gates. The quantum gate network of Figure 5 can be described as f = NOT NOT SWP, SWP, NOT,, SWP, SWP, NOT,, SWP, SWP, NOT, SWP, SWP, SWP, NOT, SWP, NOT NOT NOT,, SWP, SWP, NOT,, SWP, SWP, NOT,, SWP, NOT,, SWP, NOT, SWP, SWP, NOT, SWP, SWP, NOT, SWP, NOT, SWP, Line no a b c d Figure 4. Nearest neighbour templates for a NOT,,, b NOT,,, NOT,, and NOT, f Figure 5. Quantum gate network for FPRM epression f,, = with SWP gates. VI. VRILE ORERING N PROUT GROUPING From Rules and, we see that the number of SWP gates is directly proportional to the distance from the target input to the control inputs. We can reduce these distances by judicious ordering of the variables and grouping of the products of the FPRM epression. We propose here techniques for such variable ordering and product grouping. The philosophy of variable ordering is to bring the frequent variables closer to the target input so that the number of SWP gates needed to bring the variables adjacent to the target input is reduced. The variable ordering technique is discussed below: We construct a variable occurrence table as shown in Table. The first column lists the variables of the function. The net few columns eactly equal to the dvance online publication: 9 February 8

4 Engineering Letters, 6:, EL_6 number of products in the FPRM epression represent the products of the FPRM epression. We then determine the occurrence of the variables in the products of the FPRM epression by putting in the corresponding cells of the table. For eample, variable occurs in the products and. Therefore, we put s in the intersections of the columns corresponding to the products, and the row corresponding to the variable. In this way, we fill up the occurrence information in the table. Then, we calculate total occurrence of the variables. For eample, variable occurs twice and its total occurrence is. Then we order the variables according to their decreasing order of total occurrence. Tie is broken arbitrarily. In Table, the order of the variables is < < and this ordering is indicated by their order number in the last column. Table. Variable occurrence table for the FPRM epression f,, =. Products Total Variable Variable occurrence order We then rewrite the function using the decided variable order. The FPRM epression f,, = of 7 is now rewritten as f,, =. 9 The quantum gate network for the FPRM epression of 9 is shown in Figure 6. The quantum gate network of Figure 6 needs only 4 SWP gates compared to SWP gates in the quantum gate network of Figure 5. The quantum gate network of Figure 6 can be represented as which needs SWP gates. If we group the products of as F,,, =, then the quantum gate network with SWP gate will be as shown in Figure 7b, which needs 8 SWP gates. Therefore, this sort of product grouping will reduce the number of SWP gates in the quantum gate network. In the case of such product grouping, the swapped variables are swapped back to original order after implementing all the products of the group and thus the number of SWP gates is reduced. The rule for such product grouping is stated below. Rule 4 Product grouping: If a smaller product of an FPRM epression has number of literals and these literals are eactly similar to the first literals of another larger product, then these two products are grouped together. If more than two products satisfy the criteria, then they all are grouped together. a F b Figure 7. a Quantum gate network with SWP gates for F,,, = and b quantum gate network with SWP gates for F,,, = as. Using rule 4, we can rewrite the FPRM epression of 9 F f = NOT NOT NOT,, SWP, NOT,, SWP, SWP, NOT, SWP, NOT, NOT NOT f Figure 6. Quantum gate network for FPRM epression f,, = with SWP gates. Now, we will discuss the product grouping technique. The motivation of product grouping is illustrated using the quantum gate network of Figure 7. Figure 7a represents the quantum gate network with SWP gates for the eample FPRM epression f,, = The quantum gate network for with SWP gates is shown in Figure 8, which needs 4 SWP gates. The quantum gate network of Figure 8 can be described as f = NOT NOT NOT,, NOT, SWP, NOT,, SWP, SWP, NOT, SWP, NOT NOT In this eample, the numbers of SWP gates of Figures 6 and 8 are same. ut the motivation discussed above shows that in many situation the product grouping technique will reduce the number of SWP gates. F,,, =, dvance online publication: 9 February 8

5 Engineering Letters, 6:, EL_6 Figure 8. Quantum gate network with SWP gates for the FPRM epression f,, = with product Polarity of FPRM epression grouping. f VII. EXPERIMENTL RESULTS We have calculated the numbers of NOT gates, NOT gates, NOT gates, SWP gates, and quantum realization costs for the FPRM epressions of to 8 and these values are compared with those from [4] in Table. We have also shown the percentage decrease of quantum realization costs in our approach. Table shows that in one case polarity the cost of our approach is eactly the same as that of [4]. For the other seven cases the cost of our approach is.5% to 6.96% lesser than that of [4], which shows that the proposed approach significantly reduces the quantum realization cost. Table. omparison of quantum gate counts and quantum realization costs for FPRM epression of to 8 For the case of [4] For our case Number Number Number Number Quantum Number Number Number Number Quantum of of of of NOT realization of of of of NOT realization NOT NOT SWP gates cost NOT NOT SWP gates cost gates gates gates gates gates gates % decrease of quantum realization cost Polarity Polarity Polarity Polarity 4* 4** Polarity Polarity Polarity Polarity * This count is reported as 6 in [4], which should be 4. ** This value is reported as 6 in [4], which should be 4. VIII. ONLUSION In [4], a nearest neighbour template based synthesis of quantum oolean circuit is proposed using NOT, NOT, NOT, and SWP gates. The necessity of using SWP gates is due to the requirement of the physical quantum gates that its input qubits should be adjacent. In this paper, we have introduced variable ordering and product grouping techniques to bring the input lines of a quantum gate more close so that the number of SWP gates required is less than that of [4]. We also proposed ancillary constant selection rule to reduce one NOT gate than the approach of [4]. Eperimental results show that our approach significantly reduces the realization cost of the quantum circuit. polarity Reed-Muller epressions, International Journal of Electronics, vol. 8, no., 997, pp [8] M. H.. Khan and M. S. lam, lgorithms for conversion of minterms to positive polarity Reed-Muller coefficients and vice versa, Information Processing Letters, vol. 6, 997, pp. -. [9] J. Kim, J-S. Lee, and S. Lee, Implementation of the refined eutsch-jozsa algorithm on a three-bit NMR quantum computer, Physical Review, vol. 6,,. [] J. Kim, J-S. Lee, and S. Lee, Implementing unitary operators in quantum computation, Physical Review, vol. 6,,. REFERENES [] M.. Nielsen and I. L. huang, Quantum omputation and Quantum Information, ambridge University Press,. []. Younes and J. Miller, Representation of oolean quantum circuits as Reed-Muller epressions, ariv:quant-ph/44, May. [] I.. Grigorenko and. V. Khveshchenko, Single-step implementation of universal quantum gates, Physical Review Letters, 95, 5, 5. [4]. hakrabatri and S. Sur-Kolay, Nearest neighbour based synthesis of quantum oolean circuits, Engineering Letters, vol. 5, no., 7. [5] T. Sasao ed, Logic Synthesis and Optimization, Kluwer cademic Publishers, 99, h.. [6] M. H.. Khan and M. S. lam, Mapping of on-set fied polarity Reed-Muller coefficients from on-set canonical sum of products coefficients and the minimization of pseudo Reed-Muller epressions, International Journal of Electronics, vol. 86, no., 999, pp [7] M. H.. Khan and M. S. lam, Mapping of fied polarity Reed-Muller coefficients from minterms and the minimization of fied dvance online publication: 9 February 8