SSD1289. Advance Information. 240 RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver with built-in RAM

Transcription

1 SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA Crystalfontz Thiscontrolerdatasheetwasdownloadedfrom htp/ SSD1289 Advance Information 240 RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver with built-in RAM This document contains information on a new product. Specifications and information herein are subject to change without notice. http// SSD1289 Rev 1.1 P 1/81 Sep 2006 Copyright 2006 Solomon Systech Limited

2 CONTENTS 1 GENERAL DESCRIPTION FEATURES ORDERING INFORMATION BLOCK DIAGRAM DIE PAD FLOOR PLAN PIN DESCRIPTION BLOCK FUNCTION DESCRIPTION COMMAND TABLE COMMAND DESCRIPTION GAMMA ADJUSTMENT FUNCTION MAXIMUM RATINGS DC CHARACTERISTICS AC CHARACTERISTICS GDDRAM ADDRESS INTERFACE MAPPING DISPLAY SETTING SEQUENCE POWER SUPPLY BLOCK DIAGRAM SSD1289 OUTPUT VOLTAGE RELATIONSHIP APPLICATION CIRCUIT PACKAGE INFORMATION Solomon Systech Sep 2006 P 2/81 Rev 1.1 SSD1289

3 TABLES Table 3-1 Ordering Information... 7 Table SSD1289 Bump Pad Coordinate (Bump Center) Table 6-1 Power Supply Pins Table Interface Logic Pins Table 6-3 Mode Selection Pins Table 6-4 Driver Output Pins Table 6-5 Miscellaneous Pins Table Data bus selection modes Table 7-2 RGB signal matching in data bus Table Command Table Table 8-2 Gamma Registers POR value Table 8-3 Registers POR value at GAMAS[20] = 000, Table 8-4 Registers POR value at GAMAS[20] = 001, Table 8-5 Registers POR value at GAMAS[20] = 010, Table 8-6 Registers POR value at GAMAS[20] = 011, Table field interlace driving Table 13-1 Parallel 6800 Timing Characteristics (T A = -20 to 70 C, V DDIO = 1.4V to 3.6V, V DDEXT = 1.4V 1.95V, REGVDD= L ) Table 13-2 Parallel 8080 Timing Characteristics Table Serial Timing Characteristics Table 15-1 Interface setting and data bus setting Table 15-2 The Function of 6800-series parallel interface Table SSD1289 Rev 1.1 P 3/81 Sep 2006 Solomon Systech

4 FIGURES Figure SSD1289 Block Diagram Description... 8 Figure SSD1289 Pad Arrangement (Bump face up)... 9 Figure 7-1 Read Display Data Figure 9-1 gate output timing in 3-field interlacing driving Figure 9-2 Line Inversion AC Driver Figure 9-3 OTP circuitry Figure 13-1 Parallel 6800-series Interface Timing Characteristics Figure 13-2 Parallel 8080-series Interface Timing Characteristics Figure wire Serial Timing Characteristics Figure Pixel Clock Timing in RGB interface mode Figure Booster Capacitors Figure 17-2 Filtering and charge sharing capacitors Figure 17-3 Power supply pin connection Figure 17-4 Panel Connection Example Figure ITO and FPC connection example Solomon Systech Sep 2006 P 4/81 Rev 1.1 SSD1289

5 1 GENERAL DESCRIPTION SSD1289 is an all in one TFT LCD Controller Driver that integrated the RAM, power circuits, gate driver and source driver into a single chip. It can drive up to 262k color amorsphous TFT panel with resolution of 240 RGB x 320. It also integrated the controller function and consists of 172,800 bytes (240 x 320 x 18 / 8) Graphic Display Data RAM (GDDRAM) such that it interfaced with common MPU through 8-/9-/16-/18-bit 6800-series / 8080-series compatible parallel interface or serial peripheral interface and stored the data in the GDDRAM. Auxiliary 18-/16-/6-bit video interface (VSYNC, HSYNC, DOTCLK, DEN) are integrated into SSD1289 for animation image display. SSD1289 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver with minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display counter electrode. An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide maximum flexibility and optimal display quality. SSD1289 can be operated down to 1.4V and provide different power save modes. It is suitable for any portable batterydriven applications requiring long operation period and compact size. SSD1289 Rev 1.1 P 5/81 Sep 2006 Solomon Systech

6 2 FEATURES 240RGBx320 single chip controller driver IC for 262k color amorphous TFT LCD Power Supply - VDDEXT = 1.4V 3.6V (Internal Logic) - VDDIO = 1.4V 3.6V (I/O Interface) - VCI = 2.5V 3.6V (power supply for internal analog circuit) Output Voltages - Gate Driver VGH-GND = 9V ~ 15V VGL-GND = -7 ~ -15V VGH-VGL = 30Vp-p - Source Driver V0 V63 = 0 5V Typical Source Output Voltage variation ±10 mv - VCOM drive VCOMH = 3.0V ~ 5.0V VCOML = -2.0V ~ -3.0V VCOMHA = 5.5V System Interface - High-speed interface by 8-/9-/16-/18-bit 6800-series / 8080-series parallel ports - Serial Peripheral Interface (SPI) - Moving picture display interface - 6-/16-/18-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, DB17-0) - VSYNC interface (system interface + VSYNC) - WSYNC interface (system interface + WSYNC) Support low power consumption - Low voltage supply - Low current sleep mode - 8-color display mode for power saving - Charge sharing function for step-up circuits High-speed RAM addressing functions - RAM write synchronization function - Window address function - Display by RAM data and generic data selectively and simultaneously - Vertical scrolling function - Picture in Picture mode - Partial display mode Internal power supply circuit - Voltage generator - DC-DC converter up to 6x/-6x Built-in internal oscillator Internal GDDRAM capacity Byte Support Frame and Line inversion AC drive TFT storage capacitance Cs on common and Cs on gate Support source and gate scan direction control Programmable gamma correction curve 4 Preset gamma correction curve Built-in Non Volatile Memory for VCOM calibration Display Size 240 RGB x 320 Support flexible arrangement of gate circuits on both sides of the glass substrate Solomon Systech Sep 2006 P 6/81 Rev 1.1 SSD1289

7 3 ORDERING INFORMATION Table 3-1 Ordering Information Ordering Part Number Source Gate Package Form Reference SSD1289Z 240 x 3 (720) 320 Gold Bump Die SSD1289 Rev 1.1 P 7/81 Sep 2006 Solomon Systech

8 4 BLOCK DIAGRAM Figure SSD1289 Block Diagram Description VCOM G0 to G319 S0 to S719 VCI VDDEXT VDDIO REGVDD SHUT REV VDD regulator circuit Regulator Circuit Gamma / Grayscale Voltage Generator Source driver Switches Network VCI CN CP C1N C1P C2N C2P C3N C3P CXP CXN CYP CYN EXTCLK VSS/AVSS/ DVSS/VCHS Booster Circuit OSC Regulator Circuit VGH VGL VGOFFH VGOFFHL GateDriver VLCD63 Address Counter Timing Generation System Interface / RGB Interface Data Latches GDDRAM WSYNC RES PS0-3 E CS R/W D/C D[170] DEN DOTCLK HSYNC VSYNC TB RL CM BGR GD Solomon Systech Sep 2006 P 8/81 Rev 1.1 SSD1289

9 5 DIE PAD FLOOR PLAN Figure SSD1289 Pad Arrangement (Bump face up) Pin 1 Pin 1336 Note (1) Diagram showing the die face up. (2) Coordinates are referenced to center of the chip. (3) Coordinate units and size of all alignment marks are in um. (4) All alignment keys do not contain gold bump. Alignment Marks Center (11802,715.5) Center (-11802,715.5) Size x μm 2 Size x μm Center (-11740,-549.5), (11740,-549.5) Size 180 x 180 μm 2 Output Pad Pitch (Gate and source) Pin 358 Pin 357 Die Size x mm 2 Die Thickness 406 ± 25 um Typical Bump Height 15 um Bump Co-planarity (within die) 3 um Bump Size 1 55 x 117 μm 2 (Pin ) Pad Pitch 1 85 μm Bump Size 2 22 x 115 μm 2 (Pin 1-57, , ) Pad Pitch 2 24 μm stagger SSD1289 Rev 1.1 P 9/81 Sep 2006 Solomon Systech

10 Table SSD1289 Bump Pad Coordinate (Bump Center) Note IC material temperature expansion factor is 2.6ppm, customer should take into account during panel design Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 1 NC C2N D NC C2N D NC C1P D NC C1P D NC C1N D NC C1N D NC CP D NC CP D THROUGH CN D THROUGH CN D G C3P D G C3P D G C3P D G C3P D G C3N D G C3N D G C3N D G C3N D G VCI D G VCI D G VCI D G VCI D G VGL D G VGL D G VCHS D G VCHS D G VCHS D G VDDIO D G GD D G VSS D G CAD D G VDDIO D G REV D G VSS D G GAMAS D G VDDIO /RD G GAMAS /RD G VSS /WR G GAMAS /WR G VDDIO DC G BGR DC G VSS SDO G TB SDO G VDDIO SDI G RL SDI G VSS SCK G REGVDD SCK G VDDIO /CS G PS /CS G VSS WSYNC G PS WSYNC G VDDIO TESTA G PS TESTB G PS TESTC DUMMY SHUT EXTCLK NC CM VREGC NC /RES VREGC DUMMY /RES VCORE VCOM VSYNC VCORE VCOM VSYNC VREGR NC HSYNC VREGR VGH HSYNC VRAM VGH DOTCLK VRAM VGH DOTCLK VDDEXT VGH DEN VDDEXT C2P DEN VDDEXT C2P D VDDEXT Solomon Systech Sep 2006 P 10/81 Rev 1.1 SSD1289

11 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 202 VSSRC VCIX G VSSRC CYP G CDUM CYP G CDUM CYP G CDUM CYP G CDUM CYP G VSS CYP G VSS CYN G VSS CYN G VSS CYN G VSS CYN G VSS CYN G VSS CYN THROUGH VSS VCHS THROUGH AVSS VCHS NC AVSS VCHS NC AVSS VCHS NC AVSS VCHS NC AVSS VCHS NC AVSS CXN NC VDDIO CXN NC VDDIO CXN NC VDDIO CXP DUMMY VDDIO CXP VGL VCI CXP DUMMY VCI VGOFFH DUMMY VCI VGOFFH THROUGH VCI VCOM THROUGH VCI VCOM G VCI VCOM G VCIP VCOM G VCIP VCOMR G VCIP NC G VCIP NC G VGOFFHL GTESTR G VGOFFHL G G NC G G NC G G VLCD G G VLCD G G VLCD G G VLCD G G VCOML G G VCOML G G VCOML G G VCOML G G VCOMH G G VCOMH G G VCOMH G G VCOMH G G VCIM G G VCIM G G VCIM G G VCIM G G NC G G NC G G VCI G G VCI G G VCI G G VCI G G VCIX2J G G VCIX2J G G VCIX2G G G VCIX2G G G VCIX G G VCIX G G VCIX G G SSD1289 Rev 1.1 P 11/81 Sep 2006 Solomon Systech

12 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 403 G G S G G S G G S G G S G G S G G S G G S G G S G G S G G S G DUMMY S G DUMMY S G VCOM S G VCOM S G DUMMY S G DUMMY S G DUMMY S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S G S S Solomon Systech Sep 2006 P 12/81 Rev 1.1 SSD1289

13 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 604 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S SSD1289 Rev 1.1 P 13/81 Sep 2006 Solomon Systech

14 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 805 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S DUMMY S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Solomon Systech Sep 2006 P 14/81 Rev 1.1 SSD1289

15 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S SSD1289 Rev 1.1 P 15/81 Sep 2006 Solomon Systech

16 Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos Pad# Signal X-pos Y-pos 1207 S G NC G DUMMY G DUMMY G VCOM G VCOM G DUMMY G GTESTL G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G THROUGH G THROUGH G DUMMY G DUMMY G VGL G DUMMY G G G G Solomon Systech Sep 2006 P 16/81 Rev 1.1 SSD1289

17 6 PIN DESCRIPTION Remark I = Input; O = Output; IO = Bi-directional; P = Power; VCC = System VDD; GND = System VSS; Table 6-1 Power Supply Pins Name Type Connect to When not in Function Description use V SS GND System ground pin of the IC. - AV SS GND Ground of Grounding for analog circuit. - V SSRC P the Power Grounding for analog circuit. This pin requires a noise free path for GND Supply providing accurate LCD driving voltages. - V CHS AV SS Grounding for booster circuit. - Booster input voltage pin. V CI Power Supply Power - - Connect to voltage source between 2.5V to 3.6V Supply for P Analog Voltage supply pin for analog circuit. This pin requires a noise free path V CIP V CI Circuits for providing accurate LCD driving voltages. - - Connect to same source of V CI Stabilizing V CIM Negative voltage of V capacitor CI. - Booster O Stabilizing voltages V CIX2 Equals to 2x V capacitor CI - V CIX2J V CIX2 on FPC Voltage for They are the power supply used by on chip analog blocks and VGH/VGL - P V CIX2G V CIX2 on FPC analog dcdc. - V COMR I External This pin provides voltage reference for internal voltage regulator when External voltage source register VDV[40] of Power Control 4 set to Reference or Open - Connect to an external voltage source for reference Open V COMH V COML V LCD63 V GH V GL V GOFFH V GOFFHL O O Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor or open Voltages for VCOM Signal LCD Driving Voltages This pin indicates a HIGH level of VCOM generated in driving the VCOM alternation. This pin indicates a LOW level of VCOM generated in driving the VCOM alternation. This pin is the maximum source driver voltage. - A positive power output pin for gate driver. This pin is ESD sensitive. It can achieve 2000V ESD (HBM) with connection of external components in applicaton circuit. A negative power output pin for gate driver. - When the VGOFF alternation is driven, this pin indicates a high level of VGOFF. - Connect a capacitor for stabilization if Cs on gate structure is used - This pin can be open if Cs on common structure is used I Stabilizing capacitor to V COM or open - Connect a capacitor to V COM if Cs on gate application. Open CXP Booster - Connect a capacitor to CXN - CXN capacitor - Connect a capacitor to CXP - CYP Booster - Connect a capacitor to CYN - CYN capacitor - Connect a capacitor to CYP - CP Booster - Connect a capacitor to CN - CN capacitor - Connect a capacitor to CP - C1P Booster and - Connect a capacitor to C1N - Booster Stabilization C1N capacitor Capacitors - - Connect a capacitor to C1P This pin is ESD sensitive. It can achieve 2000V ESD (HBM) with connection of external C2P components in applicaton circuit. I - Connect a capacitor to C2N - Booster - Connect a capacitor to C2P C2N capacitor This pin is ESD sensitive. It can achieve 2000V ESD (HBM) with connection of external - components in applicaton circuit. C3P Booster - Connect a capacitor to C3N - C3N CDUM0 CDUM1 capacitor Stabilizing capacitor Stabilizing capacitor Stabilization Capacitors EXTCLK I V SS OSC input - Connect a capacitor to C3P Open - Connect a capacitor to V SS Open - Connect a capacitor to V SS Open A clock input pin for internal oscillator. Connect to V SS when using the internal oscillator. GND SSD1289 Rev 1.1 P 17/81 Sep 2006 Solomon Systech

18 REGVDD I V DDIO or V SS V CORE P Stablilizing capacitor V REGC P V CORE V RAM P Stablilizing capacitor V REGR P V RAM V DDEXT P Power Supply V DDIO P Power Supply Logic Control Power for Core Logic Regulator output for logic circuits Power for RAM Regulator output for RAM Power for internal V DD regulator Power for interface logic pins Input pin to enable internal vdd regulation. - Connect to V DDIO if system Vdd > 1.95V or system Vdd < 1.65V, internal Vdd regulator will be enabled - Connect to V SS if system Vdd is 1.65V 1.95V. Internal vdd regulator will be disabled. Vdd for core use. Connect a capacitor for stabilization Regulator output for V CORE use. - Vdd for RAM use. Connect a capacitor for stabilization Regulator output for RAM use. - Voltage input pin for internal logic, connect to system VDD. - Connect to voltage source between 1.4V to 3.6V Voltage input pin for logic I/O, connect to system VDD. - Connect to voltage source between 1.4V to 3.6V GND Table Interface Logic Pins Name Type Connect to Function Description When not in use DEN MPU Display enable pin from controller. Data will be treated as dummy regardless the DEN status during front/back porch setting at registers R16 and R17. V DDIO Frame synchronization signal. VSYNC MPU Display V - Fixed to V DDIO or V SS if not used DDIO or V ss I Timing Line synchronization signal. HSYNC MPU Signals V - Fixed to V DDIO or V SS if not used DDIO or V ss DOTCLK MPU Dot-clock signal and oscillator source. A non-stop external clock must be provided to that pin even at front or black porch non-display period. V DDIO or V ss When using the RGB interface, it is a input pin put the driver into sleep mode. A sharp SHUT I falling edge must be provided to such pin when IC power on. V DDIO or Logic - Connect to V V SS Control DDIO for sleep mode - Connect to V SS for normal operating mode This pin has no effect in system interface and should be connected to V DDIO / V SS V DDIO or V ss DC MPU Data or command V DDIO or V ss E ( RD ) MPU 6800-system E (enable signal) 8080-system /RD (read strobe signal) V DDIO or V ss Logic Serial mode Not used and should be connected to V DDIO or V I ss Control 68-system R/ W (indicates read cycle when High, write cycle when Low) R/ W MPU 80-system WR (write strobe signal) V DDIO or V ss ( WR ) Serial mode Not used and should be connected to V DDIO or V ss For parallel mode, 8/9/16/18 bit interface. D0-D17 IO MPU Data bus For generic mode, RGB interface. Please refer to Section 15 Interface Mapping for definition. V SS Unused pins must be float or connect to V SS. WSYNC O MPU Logic Control Ram Write Synchronization output Open RES I MPU CS MPU System Reset System reset pin. - Connect to V DDIO when not used V DDIO Chip select pin of serial interface. - Leave it OPEN when not used Open SCK SDI I MPU MPU Serial Interface Clock pin of serial interface. - Leave it OPEN when not used Open Data input pin in serial mode. - Leave it OPEN when not used Open SDO O MPU Data output pin in serial mode. - Leave it OPEN when not used Open Solomon Systech Sep 2006 P 18/81 Rev 1.1 SSD1289

19 Table 6-3 Mode Selection Pins Name CM Type I Connect to V DDIO or V SS Function Logic Control Description When using the RGB interface, it is a input pin to select 262k-color or 8-color display mode. After entered 8-color display mode, the driver will switch to Frame-Inversion- Mode, and only MSB of the data Red, Green and Blue will be considered. - Connect to V DDIO for 8-color display mode - Connect to V SS for 262k-color display mode When not in use V DDIO or V ss RL GD TB BGR REV CAD I V DDIO or V SS V DDIO or V SS V DDIO or V SS V DDIO or V SS V DDIO or V SS V DDIO or V SS Panel Mapping Controls This pin has no effect in system interface and should be connected to V DDIO / V ss Input pin to select the Source driver data shift direction. - Connect to V DDIO for display first RGB data at S0-S2 - Connect to V SS for display first RGB data at S719-S717 Input pin to select the 1st output Gate GD = 0, G0 is 1st output Gate, Gate sequence G0, G1, G2, G3,, G318, G319 GD = 1, G1 is 1st output Gate, Gate sequence G1, G0, G3, G2,, G319, G318 Input pin to select the Gate driver scan direction. - Connect to V DDIO for Gate scan from G0 to G319 - Connect to V SS for Gate scan from G319 to G0 Input pin to select the color mapping. - Connect to V DDIO for Blue-Green-Red mapping - Connect to V SS for Red-Green-Blue mapping (Refer to S0-S719 pin description on Page 19 for details) Input pin to select the display reversion. - Connect to V DDIO mapping data 0 to maximum pixel voltage for normal white panel - Connect to V SS mapping data 0 to minimum pixel voltage for normal black panel Panel structure selection pin. - Connect to V DDIO if Cs on gate structure is used - Connect to V SS if Cs on common structure is used V DDIO or V ss V DDIO or V ss V DDIO or V ss V DDIO or V ss V DDIO or V ss V DDIO or V ss PS0 PS1 PS2 PS3 I V DDIO or V SS V DDIO or V SS V DDIO or V SS V DDIO or V SS Interface Selection PS3 PS2 PS1 PS0 Interface Mode wire SPI wire SPI bit 6800 parallel interface bit 6800 parallel interface bit 8080 parallel interface bit 8080 parallel interface bits 6800 parallel interface bits 6800 parallel interface bit 8080 parallel interface bit 8080 parallel interface bit serial RGB interface bit RGB interface + 4-wire SPI bit RGB interface + 4-wire SPI GAMAS0 GAMAS1 GAMAS2 I V DDIO or V SS V DDIO or V SS V DDIO or V SS Logic Control Gamma selection pin. This pin should be connected to V DDIO / V SS Gamma selection pin. This pin should be connected to V DDIO / V SS Gamma selection pin. This pin should be connected to V DDIO / V SS V DDIO or V SS V DDIO or V SS V DDIO or V SS SSD1289 Rev 1.1 P 19/81 Sep 2006 Solomon Systech

20 Table 6-4 Driver Output Pins Name Type Connect When not Function Description to in use VCOM LCD A power supply for the TFT-display common electrode. Open G0-G319 LCD Gate driver output pins. These pins output V GH, V GL or V GOFFH level. Open GTESTR LCD Open GTESTL S0-S719 O LCD LCD LCD Driving Signals Gate driver output test pins, leave these pins no connection when using Cs on common Source driver output pins. S(3n) display Red if BGR = LOW, Blue if BGR = HIGH. S(3n+1) display Green. S(3n+2) display Blue if BGR = LOW, Red if BGR = HIGH. Open Open Table 6-5 Miscellaneous Pins Name Type Connect When not Function Description to in use NC These pins must be left open and cannot be connected together Open THROUGH Dummy pads. Used to measure the COG contact resistance. Open THROUGH These two pads are short circuited within the chip Open THROUGH Dummy pads. Used to measure the COG contact resistance. Open THROUGH These two pads are short circuited within the chip Open THROUGH Dummy pads. Used to measure the COG contact resistance. Open THROUGH These two pads are short circuited within the chip Open THROUGH Dummy pads. Used to measure the COG contact resistance. Open THROUGH These two pads are short circuited within the chip Open DUMMY Floating pins and no connection inside the IC. These pins should be open. Open Test pin of the internal circuit. TESTA FPC Open - Leave this pin open and insert test point in FPC IC Test pin of the internal circuit. TESTB IO FPC Testing Open - Leave this pin open and insert test point in FPC Signal Test pin of the internal circuit. TESTC FPC Open - Leave this pin open and insert test point in FPC Solomon Systech Sep 2006 P 20/81 Rev 1.1 SSD1289

21 7 BLOCK FUNCTION DESCRIPTION 7.1 System Interface The System Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-series high speed parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral interface. The selection of different interface is done by PS3, PS2, PS1 and PS0 pins. Please refer to the pin descriptions on page 19. a) MPU Parallel 6800-series Interface The parallel Interface consists of 18 bi-directional data pins D[170], R / W, D/ C, E and CS. R / W input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register. R / W input low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E input serves as data latch signal (clock) when high provided that CS is low. Please refer to Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in the following diagram. R/W#(WR#) E(RD#) DATA BUS N n n+1 n+2 write column address dummy read data read1 data read 2 data read 3 Figure 7-1 Read Display Data b) MPU Parallel 8080-series Interface The parallel interface consists of 18 bi-directional data pins D[170], RD, WR, D/ C and CS. RD input serves as data read latch signal (clock) when low provided that CS is low. Whether reading the display data from GDDRAM or reading the status from the status register is controlled by D/ C. WR input serves as data write latch signal (clock) when low provided that CS is low. Whether writing the display data to the GDDRAM or writing the command to the command register is controlled by D/ C. A dummy read is also required before the first actual display data read for 8080-series interface. Please refer Figure 7-1. c) MPU 4-lines Serial Peripheral Interface The 4-lines serial peripheral Interface consists of serial clock SCK, serial data SDI, D/ C and CS. SDI is shifted into 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6 data bit 0. D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock. SSD1289 Rev 1.1 P 21/81 Sep 2006 Solomon Systech

22 d) MPU 3-lines Serial Peripheral Interface The operation is similar to 4-lines serial peripheral interface while D/ C is not used. There are altogether 9-bits will be shifted into the shift register on every ninth clock in sequence D/ C bit, D7 to D0 bit. The D/ C bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM ( D/ C bit = 1) or the command register ( D/ C bit = 0) series Parallel 8080 series Parallel MCU Serial Interface Interface Interface Data Read 18/16/9/8-bits 18/16/9/8-bits No Data Write 18/16/9/8-bits 18/16/9/8-bits 8-bits Command Read Status only Status only No Command Write Yes Yes 8-bits Table Data bus selection modes 7.2 RGB Interface SSD1289 supports RGB interface and VSYNC interface as the moving display interace to display animation image. RGB interface unit consists of D[170], HSYNC, VSYNC, DOTCLK and DEN signals for display moving pictures. When the RGB interface is selcted, the display operation is synchronized with external control signals (HSYNC, VSYNC and DOTCLK). In this operation, Data D[170,] will be treated as RR[50], GG[50] and BB[05], is written in synchronization with the control signals when DEN is enabled for write operation in order to avoid flicker or tearring effect while updating display data. Table 7-2 RGB signal matching in data bus Data Bus D[1712] D[116] D[50] RGB signals RR[50] GG[50] BB[05] In VSYNC interface operation, the display operation is synchronized with the internal clock, which synchronizes the display operation with the VSYNC signal. The display data is written to the GDDRAM through the system interface. When writing data via VSYNC interface, the speed of writing data in the internal RAM is faster from the falling edge of frame synchronous (VSYNC) than calculated minimum speed. The display may be updated even the data written in the RAM is not completed. In this operation, some restrictions in setting the frequency and the method to write data to the internal RAM are required. 7.3 Address Counter (AC) The address counter (AC) assigns address to the GDDRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading the data, the AC is not updated. A window address function allows for data to be written only to a window area specified by GRAM. 7.4 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 240 RGB x 320 x 18 / 8 = 172,800 bytes. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. Please refer to the command Data Output/Scan direction for detail description. Four pages of display data forms a RAM address block and stored in the GDDRAM. Each block will form the fundamental units of scrolling addresses. Various types of area scrolling can be performed by software program according to the command Set area Scroll and Set Scroll Start. Solomon Systech Sep 2006 P 22/81 Rev 1.1 SSD1289

23 7.5 Gamma/Grayscale Voltage Generator The grayscale voltage circuit generates a LCD driver circuit that corresponds to the grayscale levels as specified in the grayscale gamma adjustment resister. 262,144 possible colors can be displayed when 1 pixel = 18 bit. For details, see the gamma adjustment register. 7.6 Booster and Regulator Circuit These two functional blocks generate the voltage of VGH, VGL, VCOM levels and VLCD0~63 which are necessary for operating a TFT LCD. 7.7 Timing Generator The timing generator generates a timing signal for the operation of internal circuit such as the internal RAM accessing, date output timing etc. 7.8 Oscillation Circuit (OSC) This module is an on-chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the display timing generator. 7.9 Data Latches This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level Liquid Crystal Driver Circuit SSD1289 consists of a 720-output source driver (S0-S719) and a 320-output gate driver (G0-G319). The display image data is latched when 720 bits of data are inputted. The latched data control the source driver and output drive waveforms. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the source driver can be changed by setting the RL bit and the shift direction of gate output from the gate driver can be changed by setting the TB bit. The scan mode by the gate driver can be changed by setting the SM bit. Sets the gate driver pin arrangement in combination with the TB bit to select the operimal scan mode for the module. SSD1289 Rev 1.1 P 23/81 Sep 2006 Solomon Systech

24 8 COMMAND TABLE Table Command Table Reg# Register R/W D/C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R Index ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 SR Status Read 1 0 L7 L6 L5 L4 L3 L2 L1 L R00h R01h R02h Oscillation Start (0000h) Driver output control RL REV CAD BGR SM TB MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 [0XXX][X0X1]3F 0 X X X X 0 X LCD drive AC control FLD ENWS B/C EOR WSMD NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0 (0000h) Power control (1) 0 1 DCT3 DCT2 DCT1 DCT0 BT2 BT1 BT0 0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 0 R03h All GAMAS[20] setting 8 color (6A64h) R05h R06h Compare register (1) 0 1 CPR5 CPR4 CPR3 CPR2 CPR1 CPR0 0 0 CPG5 CPG4 CPG3 CPG2 CPG1 CPG0 0 0 (0000h) Compare register (2) CPB5 CPB4 CPB3 CPB2 CPB1 CPB0 0 0 (0000h) Display control PT1 PT0 VLE2 VLE1 SPT 0 0 GON DTE CM 0 D1 D0 R07h (0000h) Frame cycle control 0 1 NO1 NO0 SDT1 SDT0 0 EQ2 EQ1 EQ0 DIV1 DIV0 SDIV SRTN RTN3 RTN2 RTN1 RTN0 R0Bh (5308h) Power control (2) VRC2 VRC1 VRC0 R0Ch (0004h) R0Dh Power control (3) VRH3 VRH2 VRH1 VRH0 R0Eh Power control (4) VCOMG VDV4 VDV3 VDV2 VDV1 VDV Gate scan start ROFh position SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 (0000h) Sleep mode SLP R10h (0001h) Entry mode 0 1 VS mode DFM1 DFM0 TRANS OEDef WMode DMode1 DMode0 TY1 TY0 ID1 ID0 AM LG2 LG1 LG0 R11h (6830h) OSCE N R15h Generic Interface Contrl INVDOT INVDEN INNVHS INVVS (00D0h) Horizontal Porch 0 1 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 HBP7 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 R16h (EF1Ch) Vertical Porch 0 1 VFP7 VFP6 VFP5 VFP4 VFP3 VFP2 VFP1 VFP0 VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 R17h (0103h) Solomon Systech Sep 2006 P 24/81 Rev 1.1 SSD1289

25 (continued) Reg# Register R/W D/C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R1Eh Power control (5) notp 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 R22h RAM data write 0 1 RAM data read 1 1 Data[170] mapping depends on the interface setting R23h RAM write data mask (1) 0 1 WMR5 WMR4 WMR3 WMR2 WMR1 WMR0 0 0 WMG5 WMG4 WMG3 WMG2 WMG1 WMG0 0 0 (0000h) R24h RAM write data mask (2) WMB5 WMB4 WMB3 WMB2 WMB1 WMB0 0 0 (0000h) Frame Frequency 0 1 OSC3 OSC2 OSC1 OSC R25h (8000h) VCOM OTP R28h (000Ah) VCOM OTP R29h (80C0h) R30h γ control (1) PKP12 PKP11 PKP PKP02 PKP01 PKP00 R31h γ control (2) PKP32 PKP31 PKP PKP22 PKP21 PKP20 R32h γ control (3) PKP52 PKP51 PKP PKP42 PKP41 PKP40 R33h γ control (4) PRP12 PRP11 PRP PRP02 PRP01 PRP00 R34h γ control (5) PKN12 PKN11 PKN PKN02 PKN01 PKN00 R35h γ control (6) PKN32 PKN31 PKN PKN22 PKN21 PKN20 R36h γ control (7) PKN52 PKN51 PKN PKN42 PKN41 PKN40 R37h γ control (8) PRN12 PRN11 PRN PRN02 PRN01 PRN00 R3Ah γ control (9) VRP14 VRP13 VRP12 VRP11 VRP VRP03 VRP02 VRP01 VRP00 R3Bh γ control (10) VRN14 VRN13 VRN12 VRN11 VRN VRN03 VRN02 VRN01 VRN00 R41h Vertical scroll control (1) VL18 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10 (0000h) R42h Vertical scroll control (2) VL28 VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20 (0000h) R44h Horizontal RAM address position 0 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 (EF00h) Vertical RAM R45h address start VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 position (0000h) Vertical RAM R46h address end VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 position (013Fh) First window start SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 R48h (0000h) First window end SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 R49h (013Fh) Second window R4Ah start SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 (0000h) Second window end SE28 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 R4Bh (013Fh) Set GDDRAM X R4Eh address counter XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0 (0000h) Set GDDRAM Y R4Fh address counter YAD8 YAD7 YAD6 YAD5 YAD4 YAD3 YAD2 YAD1 YAD0 (0000h) Note In R01h, bits REV, CAD, BGR, TB, RL, CM will override the corresponding hardware pins settings. Setting R28h as 0x0006 is required before setting R25h and R29h registers. SSD1289 Rev 1.1 P 25/81 Sep 2006 Solomon Systech

26 Table 8-2 Gamma Registers POR value Command R30h-R3Bh GAMAS[20] 000, GAMAS[20] 001, 101 GAMAS[20] 010, 110 GAMAS[20] 011, 111 PKP PKP PKP PKP PKP PKP5 010 PRP PRP VRP VRP PKN PKN PKN PKN PKN PKN PRN PRN VRN VRN Table 8-3 Registers POR value at GAMAS[20] = 000, Reg# Register Hex code IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R03h Power control (1) R0Dh Power control (3) R0Eh Power control (4) R1Eh Power control (5) Table 8-4 Registers POR value at GAMAS[20] = 001,101 Reg# Register Hex code IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R03h Power control (1) 6A R0Dh Power control (3) 000A R0Eh Power control (4) 2C R1Eh Power control (5) Table 8-5 Registers POR value at GAMAS[20] = 010,110 Reg# Register Hex code IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R03h Power control (1) R0Dh Power control (3) R0Eh Power control (4) R1Eh Power control (5) 002F Table 8-6 Registers POR value at GAMAS[20] = 011,111 Reg# Register Hex code IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R03h Power control (1) R0Dh Power control (3) 000A R0Eh Power control (4) R1Eh Power control (5) Solomon Systech Sep 2006 P 26/81 Rev 1.1 SSD1289

27 9 COMMAND DESCRIPTION Index (IR) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index instruction specifies the RAM control indexes (R00h to RFFh). It sets the register number in the range of to in binary form. But do not access to Index register and instruction bits which do not have it s own index register. Device Code Read (R00h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R If this register is read forcibly, 8989h is read. Oscillator (R00h) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W OSCEN POR OSCEN The oscillator will be turned on when OSCEN = 1, off when OSCEN = 0. Driver Output Control (R01h) (POR = [0XXXX0X1]3Fh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 RL REV CAD BGR SM TB MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 POR 0 X X X X 0 X Note The POR value of REV, CAD, BGR, TB and RL are determined by the corresponding hardware pin state. The software bit setting will override hardware setting if this command is sent. REV Displays all character and graphics display sections with reversal when REV = 1. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is indicated below. REV 0 1 RGB data 00000H 3FFFFH 00000H 3FFFFH Source Output level Vcom = L V63 V0 V0 V63 Vcom = H V0 V63 V63 V0 CAD Set up based on retention capacitor configuration of the TFT panel. CAD Retention capacitor configuration 0 Cs on Common 1 Cs on Gate BGR Selects the order from RGB to BGR in writing 18-bit pixel data in the GDDRAM. When BGR = 0 <R><G><B> color is assigned from S0. When BGR = 1 <B><G><R> color is assigned from S0. SSD1289 Rev 1.1 P 27/81 Sep 2006 Solomon Systech

28 SM Change scanning order of gate driver. See Scan mode setting on next page. TB Selects the output shift direction of the gate driver. When TB = 1, G0 shifts to G319. When TB = 0, G319 shifts to G0. SM Gate scan squence (GD= 0 ) 0 G0, G1, G2, G3 G219 (left and right gate interlaced) 1 G0, G2, G318, G1, G3, G319 RL Selects the output shift direction of the source driver. When RL = 1, S0 shifts to S719 and <R><G><B> color is assigned from S0. When RL = 0, S719 shifts to S0 and <R><G><B> color is assigned from S719. Set RL bit and BGR bit when changing the dot order of R, G and B. RL setting will be ignored when display with RAM (Dmode[10] = 00). MUX[80] Specify number of lines for the LCD driver. MUX[80] settings cannot exceed 319. Remark When using the partial display, the output for non-display area will be minimum voltage. Solomon Systech Sep 2006 P 28/81 Rev 1.1 SSD1289

29 GD= 1, G1 is the 1st gate output channel, gate output sequence is G1, G0, G3, G2,, G319, G318. SM = 0 SM = 1 G1 G3 G5 G0 G2 G4 G1 G3 TB = 1 RL = 1 G317 G319 G0 G2 G317 G319 G316 G318 G316 G318 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G1 G3 TB = 0 RL = 1 G317 G319 G316 G318 G317 G319 G0 G2 G316 G318 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G1 G3 TB = 1 RL = 0 G317 G319 G0 G2 G317 G319 G316 G318 G316 G318 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G1 G3 TB = 0 RL = 0 G317 G319 G0 G2 G317 G319 G316 G318 G316 G318 S0 S719 S0 S719 SSD1289 Rev 1.1 P 29/81 Sep 2006 Solomon Systech

30 GD= 0, G0 is the 1st gate output channel, gate output sequence is G0, G1, G2, G3,, G318, G319. SM = 0 SM = 1 G1 G3 G5 G0 G2 G4 G0 G2 TB = 1 RL = 1 G1 G3 G316 G318 G317 G319 G316 G318 G317 G319 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G0 G2 G316 G318 TB = 0 RL = 1 G1 G3 G317 G319 G316 G318 G317 G319 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G0 G2 TB = 1 RL = 0 G1 G3 G316 G318 G317 G319 G316 G318 G317 G319 S0 S719 S0 S719 G1 G3 G5 G0 G2 G4 G0 G2 G316 G318 TB = 0 RL = 0 G1 G3 G317 G319 G316 G318 G317 G319 S0 S719 S0 S719 Solomon Systech Sep 2006 P 30/81 Rev 1.1 SSD1289

31 LCD-Driving-Waveform Control (R02h) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W FLD ENWS B/C EOR WSMD NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0 POR FLD Set display in interlace drive mode to protect from flicker. It splits one frame into 3 fields and drive. When FLD = 1, it is 3 field driving, which also limit VBP = 1 and cannot be used for Cs on gate panel type. That is CAD = 1 & FLD =1 cannot be coexist. When FLD = 0, it is normal driving. The following figure shows the gate selection when the 3-field invension is enabled and the output waveform of the 3- field interlaced driving. Table field interlace driving TB = 1 TB = 0 Gate FLD = 0 FLD = 1 Gate FLD = 0 FLD = 1 G0 X G319 X G1 X G318 X G2 X X G317 X X G3 X G316 X G4 X G315 X X X X X X X X x G317 X G2 X G318 X G1 X G319 X X G0 X X Figure 9-1 gate output timing in 3-field interlacing driving 1 frame Blank period Field 1 Field 2 Field 3 Field 1 AC Polarity G0 G1 G2 G3 G4 G5 G3n +1 G3n +2 G3n +3 SSD1289 Rev 1.1 P 31/81 Sep 2006 Solomon Systech

32 B/C Select the liquid crystal drive waveform VCOM. When B/C = 0, frame inversion of the LCD driving signal is enabled. When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[70]+1. EOR When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven and the N-lines. NW[70] Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). N-line is equal to NW[70]+1. Figure 9-2 Line Inversion AC Driver N Frame N+1 Frame Back porch Front porch Back porch Front porch Frame Inversion 320 line drive N Frame N+1 Frame Back porch Front porch Back porch Front porch Line Inversion 320 line drive Solomon Systech Sep 2006 P 32/81 Rev 1.1 SSD1289

33 ENWS When ENWS = 1, it enables WSYNC output pin. Mode1 or Mode2 is selected by WSMD. When ENWS = 0(POR), it disables WSYNC feature, the WSYNC output pin will be high-impedance. WSYNC MPU /CS D/C /WR SSD D[170] WSMD = 0 is mode1, the waveform of WSYNC output will be tn tu WSYNC % Memory Access 0% Fast write MCU Slow write MCU SSD1289 displaying memory tn is the time when there is No Update of LCD screen from on-chip ram content. tu is the time when the LCD screen is updating based on on-chip ram content. e.g. fosc = 510KHz, for 320mux, tn = 282us (6 lines), tu =15.06ms (320 lines) WSMD = 1 is mode2, the waveform of WSYNC output will be WSYNC m-1 mux line read For fast write MCU MCU should start to write new frame of ram data just after rising edge of long WSYNC pulse and should be finished well before the rising edge of the next long WSYNC pulse. e.g. 5MHz 8 bit parallel write cycle for 18 bit color depth, or 3MHz 8 bit parallel write cycle for 16 bit color depth. For slow write MCU (Half the write speed of fast write) MCU should start to write new frame ram data after the rising edge of the first short WSYNC pulse and must be finished within 2 frames time. e.g. 2.5MHz 8 bit parallel write cycle for 18 bit color depth. * Usually, mode2 is for slower MCU, while mode1 is for fast MCU. SSD1289 Rev 1.1 P 33/81 Sep 2006 Solomon Systech

34 Power control 1 (R03h) (POR = 6664h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 DCT3 DCT2 DCT1 DCT0 BT2 BT1 BT0 0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 0 POR *note this POR value is for GAMAS[20] = 000, for POR values of all GAMAS[20] setting please refer to Table 5. DCT[30] Set the step-up cycle of the step-up circuit for 8-color mode (CM = V DDIO ). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DCT3 DCT2 DCT1 DCT0 Step-up cycle Fline Fline Fline Fline Fline Fline Fline Fline Fline Fline fosc / fosc / fosc / fosc / fosc / fosc / 16 * Fline = Line frequency fosc = Internal oscillator frequency (~510KHz) BT[20] Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply voltage to be used. BT2 BT1 BT0 V GH output V GL output V GH booster ratio V GL booster ratio V CIX2 +4 x V CI -(V CIX2 x 3) + V CI V CIX2 +4 x V CI -(V GH ) + V Cix V CIX2 +4 x V CI -(V GH ) V CI x 5 -(V GH ) V CI x 5 -(V GH ) + V CI V CI x 5 -(V GH ) + V Cix V CI x 4 -(V GH ) V CI x 4 -(V GH ) + V CI +4-3 Solomon Systech Sep 2006 P 34/81 Rev 1.1 SSD1289

35 DC[30] Set the step-up cycle of the step-up circuit for 262k-color mode (CM = V SS ). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DC3 DC2 DC1 DC0 Step-up cycle Fline Fline Fline Fline Fline Fline Fline Fline Fline Fline fosc / fosc / fosc / fosc / fosc / fosc / 16 * Fline = Line frequency fosc = Internal oscillator frequency (~510KHz) AP[20] Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current taking into account the power consumption. During times when there is no display, such as when the system is in a sleep mode. AP2 AP1 AP0 Op-amp power Least Small Small to medium Medium Medium to large Large Large to Maximum Maximum Compare register (R05h-R06h) (POR = 0000h) Reg# R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R05h W 1 CPR5 CPR4 CPR3 CPR2 CPR1 CPR0 0 0 CPG5 CPG4 CPG3 CPG2 CPG1 CPG0 0 0 POR R06h W CPB5 CPB4 CPB3 CPB2 CPB1 CPB0 0 0 POR CPR[50], CPG[50], CPB[50] Set the value for the compare register, of which the data read out from the GDDRAM or data written to the GDDRAM by the microcomputer are compared. This function is not available in the external display interface mode. In the external display mode, make sure LG[20] = 000. CPR[50] compares the pins RR[50], CPG[50] compares the pins GG[50], and CPB[50] compares the pins BB[50]. Refer to Section 14 Interface Mapping for writing methods in RGB data. SSD1289 Rev 1.1 P 35/81 Sep 2006 Solomon Systech

36 Display Control (R07h) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W PT1 PT0 VLE2 VLE1 SPT 0 0 GON DTE CM 0 D1 D0 POR PT[10] Normalize the source outputs when non-displayed area of the partial display is driven. VLE[21] When VLE1 = 1 or VLE2 = 1, a vertical scroll is performed in the 1st screen by taking data VL17-0 in R41h register. When VLE1 = 1 and VLE2 = 1, a vertical scroll is performed in the 1 st and 2 nd screen by VL1[80] and VL2[80] respectively. SPT When SPT = 1, the 2-division LCD drive is performed. CM 8-color mode setting. When CM = 1, 8-color mode is selected. When CM = 0, 8-color mode is disable. GON Gate off level becomes VGH when GON = 0. DTE When GON = 1 and DTE = 0, all gate outputs become VGL. When GON = 1 and DTE = 1, selected gate wire becomes VGH, and non-selected gate wires become VGL. D[10] Display is on when D1 = 1 and off when D1 = 0. When off, the display data remains in the GDDRAM, and can be displayed instantly by setting D1 = 1. When D1= 0, the display is off with all of the source outputs set to the GND level. Because of this, the driver can control the charging current for the LCD with AC driving. When D[10] = 01, the internal display is performed although the display is off. When D[10] = 00, the internal display operation halts and the display is off. Control the display on/off while control GON and DTE. GON DTE D1 D0 Internal Display Source output Gate output Operation Halt GND V GH Operation GND V GH Operation GND V GOFFL Operation Grayscale level output V GOFFL Operation Grayscale level output Selected gate line V GH Non-selected gate line V GOFFL Frame Cycle Control (R0Bh) (POR = 5308h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 NO1 NO0 SDT1 SDT0 0 EQ2 EQ1 EQ0 DIV1 DIV0 SDIV SRTN RTN3 RTN2 RTN1 RTN0 POR NO[10] Sets amount of non-overlap of the gate output. Gn NO1 NO0 Amount of non-overlap 0 0 reserved clock cycle (POR) clock cycle clock cycle 1 Line period 1 Line period Gn+1 Non-overlap period Solomon Systech Sep 2006 P 36/81 Rev 1.1 SSD1289

37 SDT[10] Set delay amount from the gate output signal falling edge of the source outputs. EQ[20] Sets the equalizing period. SDT1 SDT0 Delay amount of the source output clock cycle clock cycle (POR) clock cycle clock cycle EQ2 EQ1 EQ0 EQ period No EQ clock cycle clock cycle clock cycle clock cycle clock cycle clock cycle clock cycle Gn 1 Line period 1 Line period Sn EQ Delay amount of the source output Equalizing period DIV[10] Set the division ratio of clocks for internal operation. Internal operations are driven by clocks which frequency is divided according to the DIV1-0 setting. DIV1 DIV0 Division Ratio * fosc = internal oscillator frequency, ~510kHz SDIV When SDIV = 1, DIV1-0 value will be count. When SDIV = 0, DIV1-0 value will be auto determined. SRTN When SRTN =1, RTN3-0 value will be count. When SRTN = 0, RTN3-0 value will be auto determined. RTN[30] Set the no. of clocks in each line. The total number will be the decimal value of RTN3-0 plus 16. e.g. if RTN3-0 = 1010h, the total number of clocks in each line = = 26 clocks. SSD1289 Rev 1.1 P 37/81 Sep 2006 Solomon Systech

38 Frame frequency calculation For DMode[10] = 00 Frame _ Fosc frequency = div ( rtn + 16) ( mux + vbp + vfp + 3) where Fosc = internal oscillator frequency div = Division ratio determined by DIV[10] rtn = RTN[30] mux = MUX[80] vbp = VBP[70] vfp = VFT[70] for default values of SSD1289 Fosc = ~510KHz, DIV[10] = 00, RTN[30] = 8, MUX[80] = 319, VBP[70] = 3, VFP[70] = 1, Frame frequency = 510K 510K = = 65Hz 1 (8 + 16) ( ) Power Control 2 (R0Ch) (POR = 0004h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VRC2 VRC1 VRC0 POR VRC[20] Adjust VCIX2 output voltage. The adjusted level is indicated in the chart below VRC2-0 setting. VRC2 VRC1 VRC0 VCIX2 voltage V V V V V V V V Note The above setting is valid when VCI has high enough voltage supply for boosting up the required voltage. The above setting is assumed % booster efficiency. Please refer to DC Characteristics for detail. Solomon Systech Sep 2006 P 38/81 Rev 1.1 SSD1289

39 Power Control 3 (R0Dh) (POR = 0009h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VRH3 VRH2 VRH1 VRH0 POR* *note this POR value is for GAMAS[20] = 000, for POR values of all GAMAS[20] setting please refer to Table 5. VRH[30] Set amplitude magnification of V LCD63. These bits amplify the V LCD63 voltage 1.54 to times the Vref voltage set by VRH[30]. VRH3 VRH2 VRH1 VRH0 V LCD63 Voltage Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x *Vref is the internal reference voltage equals to 2.0V. Power Control 4 (R0Eh) (POR = 3200h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VCOMG VDV4 VDV3 VDV2 VDV1 VDV POR* *note this POR value is for GAMAS[20] = 000, for POR values of all GAMAS[20] setting please refer to Table 5. VcomG When VcomG = 1, it is possible to set output voltage of VcomL to any level, and the instruction (VDV4-0) becomes available. When VcomG = 0, VcomL output is fixed to Hi-z level, VCIM output for VcomL power supply stops, and the instruction (VDV4-0) becomes unavailable. Set VcomG according to the sequence of power supply setting flow as it relates with power supply operating sequence. VDV[40] Set the alternating amplitudes of Vcom at the Vcom alternating drive. These bits amplify 0.6 to 1.23 times the VLCD63 voltage. When VcomG = 0, the settings become invalid. External voltage at VcomR is referenced when VDH = VCOML = *VCOMH - VCOMA VDV4 VDV3 VDV2 VDV1 VDV0 Vcom Amplitude VLCD63 x VLCD63 x VLCD63 x 0.66 Step = VLCD63 x VLCD63 x Reference from external variable resistor VLCD63 x VLCD63 x 1.08 Step = VLCD63 x VLCD63 x Reserved 1 1 Reserved Note Vcom amplitude < 5.5V SSD1289 Rev 1.1 P 39/81 Sep 2006 Solomon Systech

40 Gate Scan Position (R0Fh) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 POR SCN[80] Set the scanning starting position of the gate driver. The valid range is from 0 to 319. G0 1st line of data G0 G29 1st line of data SCN8-0 = SCN8-0 = G319 G319 Sleep mode (R10h) (POR = 0001h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W SLP POR SLP Sleep mode enable bit. In the sleep mode, the internal display operations are halted except the R-C oscillator to reduce current consumption. No change in the GDDRAM data or instructions during the sleep mode is made, although it is retained. When SLP = 1, the driver enters into the sleep mode. When SLP = 0, the driver leaves the sleep mode. Entry Mode (R11h) (POR = 6830h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 VSMode DFM1 DFM0 TRANS OEDef WMode DMode1 DMode0 TY1 TY0 ID1 ID0 AM LG2 LG1 LG0 POR VSMode When VSMode = 1 at DMode[10] = 00, the frame frequency will be dependent on VSYNC. VSYNC MPU /CS D/C /WR SSD D[170] In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to the internal RAM at faster than the calculated minimum speed (internal display oerpation speed + buffer), it becomes possible to rewrite the moving picture data without flickering the display and display a moving picture via system interface. The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the VSYNC signal. The display data is written in the internal RAM so that the SSD1289 rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. Therefore, the SSD1289 can write data via VSYNC interface in high speed with low power consumption. Solomon Systech Sep 2006 P 40/81 Rev 1.1 SSD1289

41 VSYNC RAM data write via system I/F The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more than the values calculated from the following formulas, respectively. Fosc[ Hz ] = Frame _ frequency* ( mux + vfp + vbp + 3 )* ( rtn + 16 )* ( div ) 240* mux RAMWriteSpeed(min)[ Hz ] > 1 ( vbp + mux m arg ins )* ( rtn + 16 )* fosc where Fosc = internal oscillator frequency div = Division ratio determined by DIV[10] rtn = RTN[30] mux = MUX[80] vbp = VBP[70] vfp = VFT[70] Note When RAM write operation is not started right after the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. DFM[10] Set the color display mode. DFM1 DFM0 Color mode k color (POR) k color TRANS When TRANS = 1, transparent display is allowed during DMode[10] = 1x. OEDef When OEDef = 1, OE defines the display window. When OEDef = 0, the display window is defined by R4Eh and R4Fh. WMode Select the source of data to write in the RAM. WMode Write RAM from 0 Normal data bus (POR) 1 Generic interface DMode[10] SSD1289 allows data display from RAM data or from generic input data. When DMode[10] = 00, it displays the ram content. When DMode[10] = 01, it displays from generic input data. DMode1 DMode0 Display Remark 0 0 Ram (POR) Frame frequency depends on Fosc (POR) 0 1 Generic input Frame frequency depends on VSYNC, default DMode setting in RGB interface 1 0 RAM and Generic data In this case, generic data is shown in the display window 1 1 RAM and Generic data In this case, RAM data is shown in the display window SSD1289 Rev 1.1 P 41/81 Sep 2006 Solomon Systech

42 Picture In Picture Function PS[30] = 0010 / 0001 Initialize SSD1289 and display data from generic input Set SSD1289 RAM write address and GDDRAM X and Y address counter Set DMode = 11 and OEDef = x x 64 SSD1289 RGB data RAM data Define the position of the window to display RAM data Set TRANS = 1 to enable transparent function Picture in Picture TY[10] In 262k color mode, 16 bit parallel interface, there are three types of methods in writing data into the ram, Type A, B and C are described as below. TY1 TY0 Writing mode 0 0 Type A 0 1 Type B 1 0 Type C Hardware pins Interface Color mode Cycle D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 262k Type A 1 st R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x 2 nd B5 G4 B3 B2 B1 B0 x x R5 R4 R3 R2 R1 R0 x x 3 rd G5 G4 G3 G2 G1 G0 x x B5 G4 B3 B2 B1 B0 x x 16 bit 262k Type B 1 st R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x 2 nd x x x x x x x x B5 G4 B3 B2 B1 B0 x x 262k Type C 1 st R5 R4 R3 R2 R1 R0 x x G5 G4 G3 G2 G1 G0 x x 2 nd B5 G4 B3 B2 B1 B0 x x x x x x x x x x Remark x Don't care bits Not connected pins Solomon Systech Sep 2006 P 42/81 Rev 1.1 SSD1289