SSD2123. Product Preview. 480 x 272 RGB TFT LCD Driver Integrated Power Circuit, Gate and Source Driver

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2 SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2123 Product Preview 480 x 272 RGB TFT LCD Driver Integrated Power Circuit, Gate and Source Driver This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http// SSD2123 Rev 0.50 P 1/75 Mar 2008 Copyright 2008 Solomon Systech Limited

3 CONTENTS 1 GENERAL DESCRIPTION FEATURES ORDERING INFORMATION BLOCK DIAGRAM DIE PAD FLOOR PLAN PIN DESCRIPTION COMMAND TABLE COMMAND DESCRIPTION EXTENDED COMMAND DESCRIPTION MTP PROGRAMMING/ ERASE GAMMA ADJUSTMENT FUNCTION STRUCTURE OF GRAYSCALE AMPLIFIER GAMMA ADJUSTMENT REGISTER Gradient adjusting register Amplitude adjusting register Micro adjusting register LADDER RESISTOR / 8 TO 1 SELECTOR BLOCK FUNCTION DESCRIPTION SERIAL INTERFACE...52 Serial Interface 4-wires (8 bits)...52 Serial Interface 3-wires (9 bits)...53 Serial Interface 3-wires (24 bits) DATA CONTROL BOOSTER AND REGULATOR CIRCUIT SHIFT REGISTER DATA LATCHES RESET CIRCUIT DC CHARACTERISTICS AC CHARACTERISTICS DISPLAY SIGNAL OUTPUT TIMING DISPLAY GENERAL INFORMATION DISPLAY GENERAL INFORMATION BIT SERIAL INTERFACE BIT RGB INTERFACE ITO RESISTANCE REQUIREMENT SSD2123Z OUTPUT VOLTAGE RELATIONSHIP SSD2123 Rev 0.50 P 2/75 Mar 2008 Solomon Systech

4 17 INTERFACE MAPPING MAPPING FOR WRITING AN INSTRUCTION MAPPING FOR WRITING PIXEL DATA(S) APPLICATION CIRCUIT PACKAGE INFORMATION DIE TRAY DIMENSION MTP DETAIL SSD2123 Rev 0.50 P 3/75 Mar 2008 Solomon Systech

5 TABLES TABLE 3-1 ORDERING INFORMATION...7 TABLE 5-1 SSD2123 BUMP DIE PAD COORDINATES (BUMP CENTRE)...9 TABLE 6-1 POWER SUPPLY PINS...16 TABLE 6-2 INTERFACE LOGIC PINS...18 TABLE 6-3 INTERFACE LOGIC PINS...19 TABLE 6-4 DRIVER OUTPUT PINS...20 TABLE 6-5 MISCELLANEOUS PINS...20 TABLE 7-1 COMMAND TABLE AND POR (POWER ON RESET) VALUES...21 TABLE 7-2 GAMMA REGISTERS POR VALUE...22 TABLE 10-1 MTP RE-WRITE CYCLE...41 SSD2123 Rev 0.50 P 4/75 Mar 2008 Solomon Systech

6 FIGURES FIGURE 4-1 BLOCK DIAGRAM...7 FIGURE DIE FLOOR PLAN (BUMP FACE UP)...8 FIGURE 8-1 LINE INVERSION AC DRIVER...25 FIGURE 10-1 MTP PROGRAMMING CIRCUITRY...39 FIGURE 10-2 MTP PROGRAMMING FLOWCHART...40 FIGURE 10-3 MTP ERASE CIRCUITRY...41 FIGURE 10-4 MTP ERASE FLOWCHART...42 FIGURE 14-1 GATE AND SOURCE OUTPUT TIMING (LINE INVERSION)...57 FIGURE EXAMPLE OF COLOR FILTER ARRANGEMENT...58 FIGURE PIXEL CLOCK TIMING...58 FIGURE 14-4 COLOR MODE CONVERSION TIMING...60 FIGURE 14-5 VGH OUTPUT AGAINST SHUT & RESB...61 FIGURE POWER UP SEQUENCE...62 FIGURE POWER DOWN SEQUENCE...63 FIGURE SPI INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE...64 FIGURE BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE...65 FIGURE BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE...66 FIGURE LCD DRIVING VOLTAGE RELATIONSHIP...68 FIGURE APPLICATION DIAGRAM...70 SSD2123 Rev 0.50 P 5/75 Mar 2008 Solomon Systech

7 1 GENERAL DESCRIPTION SSD2123 is an all in one driver that integrated the power circuits, gate driver and source driver into single chip. It can drive a 16.7M/262k/8 color a-tft panel with resolution of 480 x 272 RGB. SSD2123 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver with minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display counter electrode. The driver supports three separated RGB Gamma settings. An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide maximum flexibility and optimal display quality. SSD2123 can be operated down to 1.6V and provide different power save modes. It is suitable for any portable battery-driven applications requiring long operation period with compact size. 2 FEATURES 480 x 272 RGB single chip controller driver IC for 16.7M/262k/8 color amorphous TFT LCD RGB color filter arrangement at Gate Power Supply - VDDIO = 1.6V 3.6V (I/O Interface) - VCI = 2.5V 3.6V (power supply for internal analog circuit) Output Voltages - Gate Driver VGH-GND = 6V ~ 18V VGL-GND = -6V ~ -15V VGH-VGL = 32Vp-p - Source Driver Source = VSS ~ AVDD - 0.1V Typical Source Output Voltage variation ±30 mv - VCOM drive VCOMH = 2.5V ~ 6.0V VCOML = 0V ~ -3.0V VCOM amplitude = 6V (max) VCOMH in ~10mV resolution steps System Interface - Serial Peripheral Interface (SPI), 3 wire (9bit), 4 wire and SPID 24 bit interface Video interface - 24-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[70], BB[70], GG[70]) - 18-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[72], BB[72], GG[72]) - 8-bit serial RGB interface - 6-bit serial RGB interface Support low power consumption - Low voltage supply - Low current sleep mode - 8-color display mode for power saving - Charge sharing function for switching circuits - Software settable for Shut and 8 color modes. Internal power supply circuit - Voltage generator - DC-DC converter up to +18/-12 or +15/-15 (VGH - VGL < 32V) - AV DD generator of 2x, 2.5x or 3x of V CI Support separate RGB gamma control Support line / frame inversion TFT storage capacitance Cs on common Support source and gate scan direction control Built-in Non Volatile Memory (MTP) for VCOM calibration SSD2123 Rev 0.50 P 6/75 Mar 2008 Solomon Systech

8 3 ORDERING INFORMATION Table 3-1 Ordering Information Ordering Part Number SSD2123Z Package Form COG 4 BLOCK DIAGRAM Figure 4-1 Block Diagram VCOM G0 to G815 S0 to S479 V CORE/V REGC/V DDIO SHUT CM V CI/V CIP CXN CXP C11N C11P C12N C12P C13N C13P C1N C1P C2N C2P C3N C3P V SS/V SSRC/ AV SS/V CHS Booster Circuit Shift Registers Regulator Circuit V GH V GL Regulator Circuit Gate Driver Serial Interface VLCD Gamma / Grayscale Voltage Generator Source driver Switches Network Data Latches Shift Registers Data Control TB RES CS SCL SDI SDO BB[70] GG[70] RR[70] DEN DOTCLK HSYNC VSYNC RL SRGB BGR REV STYPE[1,0] X400 SSD2123 Rev 0.50 P 7/75 Mar 2008 Solomon Systech

9 5 DIE PAD FLOOR PLAN Die Information Pin 1 Die Center (0,0) x Pin 1640 y Die Size x 730 µm 2 Die Thickness 304 ± 25µm Bump Height 15 µm (Typ.) Bump Co-planarity 2 µm within die Bump Size 1 50 x 80 µm 2 (IO pad, Pad 1-333) Pad Pitch 1 70 µm Bump Size 2 50 x 100 µm 2 (Dummy pad, Pad , ) Pad Pitch 2 53 µm Bump Size 3 17 x 100 µm 2 (G/S pad, Pad ) Pad Pitch 3 18 µm Output Pad Pitch Dummy Center (-11785, 25) Size 75 x 75 µm 2 Dummy G0 G2 G4 G6 G8 G Center (11785, 25) Size 75 x 75 µm Pin 333 Pin Center (-11785, -299) Size 50 x 50 µm 2 50 Center (11785, -299) Size 50 x 50 µm 2 * Diagram is not to scale Figure Die Floor Plan (Bump face up) SSD2123 Rev 0.50 P 8/75 Mar 2008 Solomon Systech

10 Table 5-1 SSD2123 Bump Die Pad Coordinates (Bump Centre) Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 1 NC VGH C12N VCOMH NC VGH C12N VCOMH VGH VGH C12N VCOMH VGH VGH C12N NC VSS VGH C12N AVSS VSS VCHS C13P AVSS VLCD VCHS C13P AVSS VLCD VCHS C13P AVSS VLCD VCHS C13P VSS VLCD VCHS C13N NC VSSRC VCHS C13N NC VSSRC VCHS C13N NC VCIP VCHS C13N NC VCIP VCHS CXP NC TESTA VCHS CXP NC TESTB VCHS CXP VSS VSS VCHS CXP NC NC VCHS CXN NC NC AVDDG CXN NC NC AVDDG CXN NC NC AVDDG CXN NC NC AVDDG VCIM VSS NC AVDDG VCIM CSSRC AVSS AVDDG VCIM CSSRC AVSS AVDDG VCIM CSSRC AVSS AVDDG VCOM AVSS AVSS AVDD VCOM AVSS VGL AVDD VCOM VCI VGL AVDD VCOM VCI VGL AVDD VCOM VCI VGL AVDD VCOM VCORE VGL AVDD VCOM VCORE VGL AVDD VCOM VCORE C3P AVDD CSSRC VCORE C3P AVDD CSSRC VREGC C3P C11P CSSRC VREGC C3P C11P CSSRC VREGC C3P C11P CSSRC VREGC C3N C11P CSSRC VSS C3N C11P AVSS VSS C3N C11P AVSS VSS C3N C11N AVSS VDDIO C3N C11N AVSS VDDIO C2P C11N AVSS VDDIO C2P C11N AVSS VDDIO C2P C11N VCOML B C2P C11N VCOML B C2N VCI VCOML B C2N VCI VCOML B C2N VCI VCOML B C2N VCI VCOML B C1P VCI VCOML B C1P VCI VCOML B C1P VCI VCOML VSS C1P VCI VCOML G C1N VCI VCOML G C1N VCI VCOMH G C1N C12P VCOMH G C1N C12P VCOMH G VGH C12P VCOMH G VGH C12P VCOMH G VGH C12P VCOMH G VGH C12P VCOMH VSS VGH C12N VCOMH R SSD2123 Rev 0.50 P 9/75 Mar 2008 Solomon Systech

11 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 257 R Dummy G<99> G<227> R Dummy G<101> G<229> R Dummy G<103> G<231> R Dummy G<105> G<233> R Dummy G<107> G<235> R Dummy G<109> G<237> R Dummy G<111> G<239> VSS Dummy G<113> G<241> DOTCLK Dummy G<115> G<243> DOTCLK Dummy G<117> G<245> VDDIO Dummy G<119> G<247> HSYNC Dummy G<121> G<249> VSS Dummy G<123> G<251> VSYNC Dummy G<125> G<253> VDDIO Dummy G<127> G<255> DEN G<1> G<129> G<257> VSS G<3> G<131> G<259> SDC G<5> G<133> G<261> SDI G<7> G<135> G<263> SCK G<9> G<137> G<265> CSB G<11> G<139> G<267> SDO G<13> G<141> G<269> VDDIO G<15> G<143> G<271> GPI G<17> G<145> G<273> GPI G<19> G<147> G<275> GPI G<21> G<149> G<277> GPI G<23> G<151> G<279> STYPE G<25> G<153> G<281> STYPE G<27> G<155> G<283> CM G<29> G<157> G<285> RESB G<31> G<159> G<287> SPID G<33> G<161> G<289> REV G<35> G<163> G<291> BGR G<37> G<165> G<293> TB G<39> G<167> G<295> RL G<41> G<169> G<297> SHUT G<43> G<171> G<299> GAMAS G<45> G<173> G<301> NC G<47> G<175> G<303> SRGB G<49> G<177> G<305> DENMODE G<51> G<179> G<307> X G<53> G<181> G<309> VDDIO G<55> G<183> G<311> AVSS G<57> G<185> G<313> AVSS G<59> G<187> G<315> AVSS G<61> G<189> G<317> AVSS G<63> G<191> G<319> VCI G<65> G<193> G<321> VCI G<67> G<195> G<323> VCI G<69> G<197> G<325> VCI G<71> G<199> G<327> NC G<73> G<201> G<329> NC G<75> G<203> G<331> NC G<77> G<205> G<333> NC G<79> G<207> G<335> NC G<81> G<209> G<337> NC G<83> G<211> G<339> NC G<85> G<213> G<341> NC G<87> G<215> G<343> NC G<89> G<217> G<345> NC G<91> G<219> G<347> NC G<93> G<221> G<349> NC G<95> G<223> G<351> NC G<97> G<225> G<353> SSD2123 Rev 0.50 P 10/75 Mar 2008 Solomon Systech

12 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 513 G<355> G<485> G<615> G<745> G<357> G<487> G<617> G<747> G<359> G<489> G<619> G<749> G<361> G<491> G<621> G<751> G<363> G<493> G<623> G<753> G<365> G<495> G<625> G<755> G<367> G<497> G<627> G<757> G<369> G<499> G<629> G<759> G<371> G<501> G<631> G<761> G<373> G<503> G<633> G<763> G<375> G<505> G<635> G<765> G<377> G<507> G<637> G<767> G<379> G<509> G<639> G<769> G<381> G<511> G<641> G<771> G<383> G<513> G<643> G<773> G<385> G<515> G<645> G<775> G<387> G<517> G<647> G<777> G<389> G<519> G<649> G<779> G<391> G<521> G<651> G<781> G<393> G<523> G<653> G<783> G<395> G<525> G<655> G<785> G<397> G<527> G<657> G<787> G<399> G<529> G<659> G<789> G<401> G<531> G<661> G<791> G<403> G<533> G<663> G<793> G<405> G<535> G<665> G<795> G<407> G<537> G<667> G<797> G<409> G<539> G<669> G<799> G<411> G<541> G<671> G<801> G<413> G<543> G<673> G<803> G<415> G<545> G<675> G<805> G<417> G<547> G<677> G<807> G<419> G<549> G<679> G<809> G<421> G<551> G<681> G<811> G<423> G<553> G<683> G<813> G<425> G<555> G<685> G<815> G<427> G<557> G<687> DUMMY G<429> G<559> G<689> DUMMY G<431> G<561> G<691> DUMMY G<433> G<563> G<693> S<479> G<435> G<565> G<695> S<478> G<437> G<567> G<697> S<477> G<439> G<569> G<699> S<476> G<441> G<571> G<701> S<475> G<443> G<573> G<703> S<474> G<445> G<575> G<705> S<473> G<447> G<577> G<707> S<472> G<449> G<579> G<709> S<471> G<451> G<581> G<711> S<470> G<453> G<583> G<713> S<469> G<455> G<585> G<715> S<468> G<457> G<587> G<717> S<467> G<459> G<589> G<719> S<466> G<461> G<591> G<721> S<465> G<463> G<593> G<723> S<464> G<465> G<595> G<725> S<463> G<467> G<597> G<727> S<462> G<469> G<599> G<729> S<461> G<471> G<601> G<731> S<460> G<473> G<603> G<733> S<459> G<475> G<605> G<735> S<458> G<477> G<607> G<737> S<457> G<479> G<609> G<739> S<456> G<481> G<611> G<741> S<455> G<483> G<613> G<743> S<454> SSD2123 Rev 0.50 P 11/75 Mar 2008 Solomon Systech

13 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 773 S<453> S<388> S<323> S<258> S<452> S<387> S<322> S<257> S<451> S<386> S<321> S<256> S<450> S<385> S<320> S<255> S<449> S<384> S<319> S<254> S<448> S<383> S<318> S<253> S<447> S<382> S<317> S<252> S<446> S<381> S<316> S<251> S<445> S<380> S<315> S<250> S<444> S<379> S<314> S<249> S<443> S<378> S<313> S<248> S<442> S<377> S<312> S<247> S<441> S<376> S<311> S<246> S<440> S<375> S<310> S<245> S<439> S<374> S<309> S<244> S<438> S<373> S<308> S<243> S<437> S<372> S<307> S<242> S<436> S<371> S<306> S<241> S<435> S<370> S<305> S<240> S<434> S<369> S<304> DUMMY S<433> S<368> S<303> S<239> S<432> S<367> S<302> S<238> S<431> S<366> S<301> S<237> S<430> S<365> S<300> S<236> S<429> S<364> S<299> S<235> S<428> S<363> S<298> S<234> S<427> S<362> S<297> S<233> S<426> S<361> S<296> S<232> S<425> S<360> S<295> S<231> S<424> S<359> S<294> S<230> S<423> S<358> S<293> S<229> S<422> S<357> S<292> S<228> S<421> S<356> S<291> S<227> S<420> S<355> S<290> S<226> S<419> S<354> S<289> S<225> S<418> S<353> S<288> S<224> S<417> S<352> S<287> S<223> S<416> S<351> S<286> S<222> S<415> S<350> S<285> S<221> S<414> S<349> S<284> S<220> S<413> S<348> S<283> S<219> S<412> S<347> S<282> S<218> S<411> S<346> S<281> S<217> S<410> S<345> S<280> S<216> S<409> S<344> S<279> S<215> S<408> S<343> S<278> S<214> S<407> S<342> S<277> S<213> S<406> S<341> S<276> S<212> S<405> S<340> S<275> S<211> S<404> S<339> S<274> S<210> S<403> S<338> S<273> S<209> S<402> S<337> S<272> S<208> S<401> S<336> S<271> S<207> S<400> S<335> S<270> S<206> S<399> S<334> S<269> S<205> S<398> S<333> S<268> S<204> S<397> S<332> S<267> S<203> S<396> S<331> S<266> S<202> S<395> S<330> S<265> S<201> S<394> S<329> S<264> S<200> S<393> S<328> S<263> S<199> S<392> S<327> S<262> S<198> S<391> S<326> S<261> S<197> S<390> S<325> S<260> S<196> S<389> S<324> S<259> S<195> SSD2123 Rev 0.50 P 12/75 Mar 2008 Solomon Systech

14 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 1033 S<194> S<129> S<64> DUMMY S<193> S<128> S<63> DUMMY S<192> S<127> S<62> DUMMY S<191> S<126> S<61> G<814> S<190> S<125> S<60> G<812> S<189> S<124> S<59> G<810> S<188> S<123> S<58> G<808> S<187> S<122> S<57> G<806> S<186> S<121> S<56> G<804> S<185> S<120> S<55> G<802> S<184> S<119> S<54> G<800> S<183> S<118> S<53> G<798> S<182> S<117> S<52> G<796> S<181> S<116> S<51> G<794> S<180> S<115> S<50> G<792> S<179> S<114> S<49> G<790> S<178> S<113> S<48> G<788> S<177> S<112> S<47> G<786> S<176> S<111> S<46> G<784> S<175> S<110> S<45> G<782> S<174> S<109> S<44> G<780> S<173> S<108> S<43> G<778> S<172> S<107> S<42> G<776> S<171> S<106> S<41> G<774> S<170> S<105> S<40> G<772> S<169> S<104> S<39> G<770> S<168> S<103> S<38> G<768> S<167> S<102> S<37> G<766> S<166> S<101> S<36> G<764> S<165> S<100> S<35> G<762> S<164> S<99> S<34> G<760> S<163> S<98> S<33> G<758> S<162> S<97> S<32> G<756> S<161> S<96> S<31> G<754> S<160> S<95> S<30> G<752> S<159> S<94> S<29> G<750> S<158> S<93> S<28> G<748> S<157> S<92> S<27> G<746> S<156> S<91> S<26> G<744> S<155> S<90> S<25> G<742> S<154> S<89> S<24> G<740> S<153> S<88> S<23> G<738> S<152> S<87> S<22> G<736> S<151> S<86> S<21> G<734> S<150> S<85> S<20> G<732> S<149> S<84> S<19> G<730> S<148> S<83> S<18> G<728> S<147> S<82> S<17> G<726> S<146> S<81> S<16> G<724> S<145> S<80> S<15> G<722> S<144> S<79> S<14> G<720> S<143> S<78> S<13> G<718> S<142> S<77> S<12> G<716> S<141> S<76> S<11> G<714> S<140> S<75> S<10> G<712> S<139> S<74> S<9> G<710> S<138> S<73> S<8> G<708> S<137> S<72> S<7> G<706> S<136> S<71> S<6> G<704> S<135> S<70> S<5> G<702> S<134> S<69> S<4> G<700> S<133> S<68> S<3> G<698> S<132> S<67> S<2> G<696> S<131> S<66> S<1> G<694> S<130> S<65> S<0> G<692> SSD2123 Rev 0.50 P 13/75 Mar 2008 Solomon Systech

15 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 1293 G<690> G<560> G<430> G<300> G<688> G<558> G<428> G<298> G<686> G<556> G<426> G<296> G<684> G<554> G<424> G<294> G<682> G<552> G<422> G<292> G<680> G<550> G<420> G<290> G<678> G<548> G<418> G<288> G<676> G<546> G<416> G<286> G<674> G<544> G<414> G<284> G<672> G<542> G<412> G<282> G<670> G<540> G<410> G<280> G<668> G<538> G<408> G<278> G<666> G<536> G<406> G<276> G<664> G<534> G<404> G<274> G<662> G<532> G<402> G<272> G<660> G<530> G<400> G<270> G<658> G<528> G<398> G<268> G<656> G<526> G<396> G<266> G<654> G<524> G<394> G<264> G<652> G<522> G<392> G<262> G<650> G<520> G<390> G<260> G<648> G<518> G<388> G<258> G<646> G<516> G<386> G<256> G<644> G<514> G<384> G<254> G<642> G<512> G<382> G<252> G<640> G<510> G<380> G<250> G<638> G<508> G<378> G<248> G<636> G<506> G<376> G<246> G<634> G<504> G<374> G<244> G<632> G<502> G<372> G<242> G<630> G<500> G<370> G<240> G<628> G<498> G<368> G<238> G<626> G<496> G<366> G<236> G<624> G<494> G<364> G<234> G<622> G<492> G<362> G<232> G<620> G<490> G<360> G<230> G<618> G<488> G<358> G<228> G<616> G<486> G<356> G<226> G<614> G<484> G<354> G<224> G<612> G<482> G<352> G<222> G<610> G<480> G<350> G<220> G<608> G<478> G<348> G<218> G<606> G<476> G<346> G<216> G<604> G<474> G<344> G<214> G<602> G<472> G<342> G<212> G<600> G<470> G<340> G<210> G<598> G<468> G<338> G<208> G<596> G<466> G<336> G<206> G<594> G<464> G<334> G<204> G<592> G<462> G<332> G<202> G<590> G<460> G<330> G<200> G<588> G<458> G<328> G<198> G<586> G<456> G<326> G<196> G<584> G<454> G<324> G<194> G<582> G<452> G<322> G<192> G<580> G<450> G<320> G<190> G<578> G<448> G<318> G<188> G<576> G<446> G<316> G<186> G<574> G<444> G<314> G<184> G<572> G<442> G<312> G<182> G<570> G<440> G<310> G<180> G<568> G<438> G<308> G<178> G<566> G<436> G<306> G<176> G<564> G<434> G<304> G<174> G<562> G<432> G<302> G<172> SSD2123 Rev 0.50 P 14/75 Mar 2008 Solomon Systech

16 Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos 1553 G<170> G<40> G<168> G<38> G<166> G<36> G<164> G<34> G<162> G<32> G<160> G<30> G<158> G<28> G<156> G<26> G<154> G<24> G<152> G<22> G<150> G<20> G<148> G<18> G<146> G<16> G<144> G<14> G<142> G<12> G<140> G<10> G<138> G<8> G<136> G<6> G<134> G<4> G<132> G<2> G<130> G<0> G<128> Dummy G<126> Dummy G<124> G<122> G<120> G<118> G<116> G<114> G<112> G<110> G<108> G<106> G<104> G<102> G<100> G<98> G<96> G<94> G<92> G<90> G<88> G<86> G<84> G<82> G<80> G<78> G<76> G<74> G<72> G<70> G<68> G<66> G<64> G<62> G<60> G<58> G<56> G<54> G<52> G<50> G<48> G<46> G<44> G<42> Note IC material Temperature expansion factor should take into account during panel design. SSD2123 Rev 0.50 P 15/75 Mar 2008 Solomon Systech

17 6 Pin Description SSD2123 Pin Function Description Key I = Input O =Output I/O = Bi-directional (input/output) P = Power pin GND = System VSS Table 6-1 Power Supply Pins Connect When not Name Type Function Description to in use V SS GND System ground pin of the IC. - A VSS GND Grounding for analog circuit. - Ground of Grounding for analog circuit. This pin requires a P Power V SSRC GND noise free path for providing accurate LCD driving - Supply voltages. V CHS V CORE V DDEXT V DDIO V CI V CIP V CIM AV DD AV DDG V COMH V COML V LCD255 V GH V GL V COMR V REGC P P O O O O I P GND V REGC System V DD System V DD Power supply V CI Stabilizing capacitor Stabilizing capacitor AV DD on FPC Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor External voltage source or Open Stabilizing capacitor Power for Core Logic Power for Internal VCORE Regulator Power for Interface Logic Pins Power for Analog Circuits Booster Output Booster Voltages Voltage for analog Voltages for Signal V COM LCD Driving Voltages External Reference Grounding for booster circuit. - V DD for core use - Connect a capacitor for stabilization Voltage input pin for internal logic. Connect to System V DD (refer to power connection Figure 14-1) Voltage input pin for logic I/O. - Booster input voltage pin. - Connect to voltage source between 2.5V to 3.6V Voltage supply pin for analog circuit. This pin requires a noise free path for providing accurate LCD driving voltages. Negative voltage of V CI - Booster voltage and regulated between 5.1V to 6.1V. Controlled by command Power control 2 (R0Ch) power supply used by on chip analog blocks and V GH /V GL dcdc. Must connect AV DD together This pin indicates a HIGH level of V COM generated in driving the V COM alternation. This pin indicates a LOW level of V COM generated in driving the V COM alternation. This pin is the maximum source driver voltage. - A positive power output pin for gate driver. - A negative power output pin for gate driver. - This pin provides voltage reference for internal voltage regulator when register VDV[40] of Power Control 4 is set to Regulator output for Regulator output for V CORE use Open SSD2123 Rev 0.50 P 16/75 Mar 2008 Solomon Systech

18 logic circuits CXP Booster - Connect a capacitor to CXN - CXN capacitor - Connect a capacitor to CXP - C11P Booster - Connect a capacitor to C11N - C11N capacitor - Connect a capacitor to C11P - C12P Booster - Connect a capacitor to C12N C12N capacitor - Connect a capacitor to C12P Booster C13P Booster - Connect a capacitor to C13N and C13N capacitor - Connect a capacitor to C13P P Stabilizati C1P Booster on - Connect a capacitor to C1N - C1N capacitor Capacitors - Connect a capacitor to C1P - C2P Booster - Connect a capacitor to C2N - C2N capacitor - Connect a capacitor to C2P - C3P Booster - Connect a capacitor to C3N - C3N capacitor - Connect a capacitor to C3P - CSSRC Charge Sharing - Connect a capacitor to VSS Open SSD2123 Rev 0.50 P 17/75 Mar 2008 Solomon Systech

19 Name SPID Typ e Connect to Function Description V DDIO V SS or Table 6-2 Interface Logic Pins ID selection pin for the SPI serial interface. When sending serial data, the ID bit must match with the logic stage of this pin. (Refer to Serial Interface block description on Page XX for details) CSB MPU Serial Chip select pin of serial interface. I Interface SDI MPU Data input pin in serial mode. SDC MPU Data/Command pin of serial interface. SCK MPU SDO O MPU SHUT I V DDIO V SS VSYNC I MPU HSYNC I MPU DOTCLK I MPU or Serial Interface Logic Control RGB Interface Display Timing Signals Clock input pin in serial mode. Data output pin in serial mode. Display shut down pin to put the driver into sleep mode. A sharp falling edge must be provided to such pin when IC power on. - Connect to V DDIO for sleep mode - Connect to V SS for normal operating mode Note Software can override the setting Frame synchronization signal. Fixed to V DDIO or V SS if not used. synchronization signal. Fixed to V DDIO or V SS if not - used Dot-clock signal and oscillator source. External clock must be provided to that pin even at front or back porch - non-display period. When not in use - Open V DDIO Open V DDIO Open V DDIO Open V DDIO Open or or or or V DDIO or V SS - DEN I MPU Display enable pin from controller. V DDIO RR[70] GG[70] BB[70] I MPU RESB I MPU SRGB I X400 I V DDIO V SS V DDIO V SS or or Graphic Display Data System reset RGB interface selection RGB interface selection - RR[70] Red Data 24bit parallel/8bit serial - RR[72] Red Data 18bit parallel/6bit serial - GG[70] Green Data 24bit parallel - GG[72] Green Data 18bit parallel - BB[70] Blue Data 24bit parallel - BB[72] Blue Data 18bit parallel System reset pin. Initialization occurs once this pin is pulled Low, the minimum pulse length is 1ms. A low pulse must be applied after power-on. Connect this pin to VDDIO when not used. Determine data input for SSD Connect to V SS for the operation of parallel RGB mode 18/24 bits. - - Connect to V DDIO for the operation of serial RGB mode 6/8 bits. Note Software can override the setting Determine data input for SSD Connect to V SS for the operation of using full 480 sources - - Connect to V DDIO for the operation of using 400 sources at center. First data will appear at S40. Note Software can override the setting V DDIO or V SS V DDIO SSD2123 Rev 0.50 P 18/75 Mar 2008 Solomon Systech

20 DENMODE I V DDIO V SS or RGB interface selection Determine data input for SSD Connect to V SS for the operation of SYNC mode - Connect to V DDIO for the operation of DEN mode Note Software can override the setting GPI[30] I User define General propose pins defined by user GAMAS I V DDIO V SS or Logic Control GAMAS controls the default register values - Open (GPIP=V SS ) V DDIO or V SS Name Type Connect to Function Description STYPE0 STYPE1 BGR REV RL I I I I I V DDIO V SS V DDIO V SS V DDIO V SS V DDIO V SS V DDIO V SS or or or or or Serial Interface Selection Panel Mapping controls Table 6-3 Interface Logic Pins STYPE[10] = 0x ; SPID type 3 wires SPI 24 bits - STYPE[10] = 10 ; standard 3 wires SPI 9 bits STYPE[10] = 11 ; standard 4 wires SPI 8 bits - Color mapping selection pin. Refer to G0-G815 pin description. Note Software can override the setting Input pin to select the display reversion. - Connect to V DDIO mapping data 0 to maximum pixel voltage for normal white panel - Connect to V SS mapping data 0 to minimum pixel voltage for normal black panel Note Software can override the setting Select the Source driver data shift direction. - Connect to V DDIO for display first pixel data at S0 - Connect to V SS for display first pixel data at S479 Note Software can override the setting When not in use V DDIO V SS V DDIO V SS V DDIO V SS or or or TB I V DDIO V SS or Select the Gate driver scan direction. Note Software can override the setting V DDIO V SS or CM I V DDIO V SS or Input pin to select 16.7M-color or 8-color display mode. After entered 8-color display mode, the driver will switch to Frame-Inversion-Mode, and only MSB of the data Red, Green and Blue will be considered. - Connect to V DDIO for 8-color display mode - Connect to V SS for 16.7M-color display mode Note Software can override the setting V DDIO V SS or SSD2123 Rev 0.50 P 19/75 Mar 2008 Solomon Systech

21 Table 6-4 Driver Output Pins Name Type Connect to Function Description When not in use VCOM LCD A power supply for the TFT-display common electrode. Open Gate driver output pins. These pins output VGH or VGL G0-G815 O LCD level. LCD Color filter arrangement depends on BGR pin. Driving G(3n) Display Red if BGR = Low, Blue if BGR = High. Signals G(3n+1) Display Green. Open G(3n+2) Display Blue if BGR = Low, Red if BGR = High. S0-S479 LCD Source driver output pins. Open Table 6-5 Miscellaneous Pins Name Type Connect to Function Description When not in use NC These pins must be left open and cannot be connected Open together DUMMY Floating pins and no connection inside the IC. These pins Open can be shorted together or connect to any signal. TESTA/B/C I/O FPC Test pin of the internal circuit. IC Testing - Leave this pin open and optional to insert test point in FPC Open Signal for evaluation. SSD2123 Rev 0.50 P 20/75 Mar 2008 Solomon Systech

22 7 COMMAND TABLE Table 7-1 Command Table and POR (Power On Reset) values Reg# Register R/W D/C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R Index 0 0 * * * * * * * ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Driver output control 0 1 X400 RL REV CAD BGR SM R01h ([XXXX][X011]0Fh ) X X X X X R02h R03h R04h R0Bh R0Ch R0Dh R0Eh R0Fh R10h R15h R16h R17h R1Eh R1Fh R26h R2Ah R2Bh R2Ch R2Dh R2Eh R30h R31h R32h LCD-Driving- Waveform Control B/C EOR NW9 NW8 NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0 (0C02h) Power control (1) 0 1 DCT3 DCT2 DCT1 DCT0 BT3 BT2 BT1 BT0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 1 (0407h) Separate Gamma(1) OLO (0400h) Frame cycle control 0 1 NO1 NO0 SDT1 SDT0 EQ1 EQ0 0 0 EQ BTP1 BTP0 0 0 (D800h) Power control (2) VRC2 VRC1 VRC0 (0005h) Power control (3) VRH3 VRH2 VRH1 VRH0 (000Fh) Power control (4) VCOMG VDV4 VDV3 VDV2 VDV1 VDV VCOMAS (2C00h) Gate scan starting Position SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 (0000h) Software 8 color mode cm_en cm_soft (02CCh) Double source amp SAmp (0090h) Pixel per line 0 1 XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 (EF8Eh) x400= (C786h) x400= Vertical Porch VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 (0003h) Power control (5) nmtp 0 VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 (0034h) Power control (5) VCMR7 VCMR6 VCMR5 VCMR4 VCMR3 VCMR2 VCMR1 VCMR0 (1834h) GAMAS= Gamma Buffer biasing current IT2 IT1 IT (2800h) VCOM EQ (01D2h) nd booster freq 0 1 ENSDO (0520h) nd booster freq DCYT3 DCYT2 DCYT1 DCYT0 DCY3 DCY2 DCY1 DCY (3DDDh) Software Shut (5) UNREG 0 SS1 SS0 0 (3F40h) Read SDO (5) RSDO (B544h) γ control (1) PKP 12 PKP 11 PKP (0000h) GAMAS= γ control (1) PKP 32 PKP 31 PKP (0305h) GAMAS= γ control (1) PKP 52 PKP 51 PKP (0000h) GAMAS= VCOME Q2 PKP 02 PKP 22 PKP 42 VCOME Q1 PKP 01 PKP 21 PKP 41 VCOMEQ 0 PKP 00 PKP 20 PKP 40 SSD2123 Rev 0.50 P 21/75 Mar 2008 Solomon Systech

23 R33h R34h R35h R36h R37h R3Ah R3Bh γ control (1) PRP 12 PRP 11 PRP (0201h) GAMAS= γ control (1) PKN 12 PKN 11 PKN (0607h) GAMAS= γ control (1) PKN 32 PKN 31 PKN (0204h) GAMAS= γ control (1) PKN 52 PKN 51 PKN (0707h) GAMAS= γ control (1) PRN 12 PRN 11 PRN (0203h) GAMAS= γ control (2) VRP 14 VRP 13 VRP 12 VRP 11 VRP (0F0Fh) GAMAS= γ control (2) VRN 14 VRN 13 VRN 12 VRN 11 VRN (0F02h) GAMAS= Note X means hardware defining default setting Table 7-2 Gamma Registers POR value Register GAMAS=0 GAMAS=1 PKP PKP PKP PKP PKP PKP PRP PRP VRP VRP PKN PKN PKN PKN PKN PKN PRN PRN VRN VRN BT[30] TBD 0100 BTP[10] TBD 00 VRC[20] TBD 101 VRH[30] TBD 1111 VDV[40] TBD VCM[70] TBD HBP[60] TBD VRP 03 VRN 03 PRP 02 PKN 02 PKN 22 PKN 42 PRN 02 VRP 02 VRN 02 PRP 01 PKN 01 PKN 21 PKN 41 PRN 01 VRP 01 VRN 01 PRP 00 PKN 00 PKN 20 PKN 40 PRN 00 VRP 00 VRN 00 SSD2123 Rev 0.50 P 22/75 Mar 2008 Solomon Systech

24 8 COMMAND DESCRIPTION Index (IR) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index instruction specifies the RAM control indexes (R00h to R7Fh). It sets the register number in the range of to in binary form. But do not access to Index register and instruction bits which do not have it s own index register. Driver Output Control (R01h) (POR = [XXXX][X011]0Fh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X400 RL REV 0 BGR 0 1 MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 POR X X X 0 X X400 When X400= 0, full 480 sources are in operation When X400= 1, only 400 sources at the center are in operation. First data will appear at S40. X400 = 0 X400 = 1 G1 G3 G5 G0 G2 G4 G1 G3 G5 G0 G2 G4 G813 G815 S479 S0 G812 G814 G717 G719 S439 S40 G716 G718 RL Selects the output shift direction of the source driver. When RL = 1, S0 shifts to S479 and 1 st pixel color is assigned from S0. When RL = 0, S479 shifts to S0 and 1 st pixel color is assigned from S479. Set RL bit and BGR bit when changing the dot order of R, G and B. REV Displays all character and graphics display sections with reversal when REV = 1. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is indicated below. REV 1 0 RGB data B B B B Source Output level VCOM = H V63 V0 V0 V63 VCOM = L V0 V63 V63 V0 BGR Selects the <R><G><B> arrangement. When BGR = 0 <R><G><B> color is assigned from G0. When BGR = 1 <B><G><R> color is assigned from G0. Note The default setting of register bits X400, RL, REV, BGR and TB are defined by the logic stage of corresponding hardware pins. These bits will override the hardware setting once software command was sent to set the bits. SSD2123 Rev 0.50 P 23/75 Mar 2008 Solomon Systech

25 TB = 0 TB = 1 G1 G3 G5 G0 G2 G4 G1 G3 G5 G0 G2 G4 RL = 0 G813 G815 S479 S0 G812 G814 G813 G815 S479 S0 G812 G814 G1 G3 G5 G0 G2 G4 G1 G3 G5 G0 G2 G4 RL = 1 G813 G815 S479 S0 G812 G814 G813 G815 S479 S0 G812 G814 SSD2123 Rev 0.50 P 24/75 Mar 2008 Solomon Systech

26 LCD-Driving-Waveform Control (R02h) (POR = 0C02h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W B/C EOR NW9 NW8 NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0 POR B/C Select the liquid crystal drive waveform VCOM. When B/C = 0, frame inversion of the LCD driving signal is enabled. When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[90]+1. EOR When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven and the N-lines. NW9-0 Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). NW9-0 alternate for every set value + 1 lines. Figure 8-1 Inversion AC Driver N Frame N+1 Frame Back porch Front porch Back porch Front porch Frame Inversion 816 line drive N Frame N+1 Frame Back porch Front porch Back porch Front porch Inversion 816 line drive SSD2123 Rev 0.50 P 25/75 Mar 2008 Solomon Systech

27 Power control 1 (R03h) (POR = 0407h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 DCT3 DCT2 DCT1 DCT0 BT3 BT2 BT1 BT0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 1 POR DCT3-0 Set the step-up cycle of the step-up circuit for 8-color mode (CM = V DDIO ). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DCT3 DCT2 DCT1 DCT0 No. of dotclk (POR) Note For 416 dotclk per line, Horizontal line frequency (f H Typ. 14.8kHz, when dotclk=6.14mhz ) For 512 dotclk per line, Horizontal line frequency (f H Typ. 16.7kHz, when dotclk=8.54mhz ) For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline. DCT3 DCT2 DCT1 DCT0 Step-up cycle Fline 1 (max dotclk = 512) Fline Fline Fline 8 BT3-0 Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply voltage to be used. BT3 BT2 BT1 BT0 V GH output V GL output V GH booster ratio V GL booster ratio AVDD x 3 -(VGH - VCI) AVDD x 3 -(VGH - AVDD) AVDD x 3 -(AVDD x 3) AVDD x 2 + VCI -(VGH) AVDD x 2 + VCI -(VGH - VCI) AVDD x 2 + VCI -(VGH - AVDD x 2) AVDD x 2 -(VGH) AVDD x 2 -(VGH - VCI) Reserved Reserved Reserved Reserved AVDD x 3 -(AVDD) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SSD2123 Rev 0.50 P 26/75 Mar 2008 Solomon Systech

28 DC3-0 Set the step-up cycle of the step-up circuit for 16.7M-color mode (CM = V SS ). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DC3 DC2 DC1 DC0 No. of dotclk (POR) Note For 416 dotclk per line, Horizontal line frequency (f H Typ. 14.8kHz, when dotclk=6.14mhz ) For 512 dotclk per line, Horizontal line frequency (f H Typ. 16.7kHz, when dotclk=8.54mhz ) For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline. DC3 DC2 DC1 DC0 Step-up cycle Fline 1 (max dotclk = 512) Fline Fline Fline 8 AP2-0 Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current taking into account the power consumption. While there is no display, such as the system is in a sleep mode, AP2-0 can be set to (0,0,0) and shutting down the operational amplifier can reduce the power consumption. AP2 AP1 AP0 Op-amp power Least Small Small to medium Medium Medium to large Large Large to Maximum Maximum SSD2123 Rev 0.50 P 27/75 Mar 2008 Solomon Systech

29 Seperate Gamma (R04h) (POR = 0400h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W OLO POR OLO When OLO = 1, all R,G and B gamma registers are set by one set of gamma control, R30h to R3Bh. When OLO = 0, R, G and B gamma registers are set separately by registers R30h to R3Bh, R40h to R4Bh and R50h to R5Bh. Frame Cycle Control (R0Bh) (POR = D800h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 NO1 NO0 SDT1 SDT0 EQ1 EQ0 0 0 EQ BTP1 BTP0 0 0 POR NO1-0 Sets amount of non-overlap of the gate output. NO1 NO0 Amount of non-overlap 0 0 HSYNC_falling DOTCLK 0 1 HSYNC _falling + 60 DOTCLK 1 0 HSYNC _falling + 30 DOTCLK DOTCLK after Source On Gn 1 period 1 period Gn+1 Non-overlap period SDT1-0 Set delay amount from the gate output signal falling edge of the source outputs. EQ2-0 Sets the equalizing period on source SDT1 SDT0 Delay amount of the source output 0 0 HSYNC_falling 3 DOTCLK 0 1 HSYNC_falling 7 DOTCLK 1 0 HSYNC_falling 11 DOTCLK 1 1 HSYNC_falling 15 DOTCLK EQ2 EQ1 EQ0 EQ period No EQ clock cycle clock cycle Reserved clock cycle clock cycle clock cycle clock cycle Gn 1 period 1 period Sn EQ Delay amount of the source output Equalizing period SSD2123 Rev 0.50 P 28/75 Mar 2008 Solomon Systech

30 BTP1-0 Set the Primary booster ratio. BTP1 BTP0 Primary booster ratio 0 0 2X X 1 0 3X 1 1 2X Power Control 2 (R0Ch) (POR = 0005h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VRC2 VRC1 VRC0 POR VRC[20] Adjust AVDD output voltage. The adjusted level is indicated in the chart below VRC2-0 setting. VRC2 VRC1 VRC0 AVDD voltage V V V V V V Reserved Reserved Note VCI=3.3V and without panel loading Figures on the above table are target AVDD output, actual AVDD voltage depends on VCI, booster efficiency and panel loading Power Control 3 (R0Dh) (POR = 000Fh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VRH3 VRH2 VRH1 VRH0 POR VRH3-0 Set amplitude magnification of V LCD255. These bits amplify the V LCD255 voltage 1.78 to 3.00 times the Vref voltage set by VRH3-0. VRH3 VRH2 VRH1 VRH0 V LCD255 Voltage Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Vref x Note Vref is the internal reference voltage equals to 2.0V. SSD2123 Rev 0.50 P 29/75 Mar 2008 Solomon Systech

31 Power Control 4 (R0Eh) (POR = 2C00h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VCOMG VDV4 VDV3 VDV2 VDV1 VDV VCOMAS POR VCOMG When VCOMG = 1, it is possible to set output voltage of V COML to any level, and the instruction (VDV4-0) becomes available. When VCOMG = 0, V COML output is fixed to Hi-z level, V CI2 output for V COML power supply stops, and the instruction (VDV4-0) becomes unavailable. Set VCOMG according to the sequence of power supply setting flow as it relates with power supply operating sequence. VDV4-0 Set the alternating amplitudes of VCOM at the VCOM alternating drive. These bits amplify VCOM amplitude 0.6 to 1.23 times the V LCD255 voltage. When VCOMG = 0, the settings become invalid. VDV4 VDV3 VDV2 VDV1 VDV0 VCOMA V LCD255 x V LCD255 x V LCD255 x 0.66 Step = V LCD255 x V LCD255 x External Voltage Reference V LCD255 x V LCD255 x 1.08 Step = V LCD255 x V LCD255 x Reserved 1 1 Reserved Note1 VCOMA < 6.0V Note2 VCOMH VCOML < 6.0V Note3 VCOML < VCI VCOMAS Set the equation of V COML. V COML = α x V COMH - V COMA α VCOMAS Software 8 colour mode (R10h) (POR = 02CCh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W CM1 CM0 POR CM1-0 Software command enter 8 colour mode CM1 CM0 Status 0 0 Follow the CM pin setting 0 1 Follow the CM pin setting 1 0 Enter full colour mode 1 1 Enter 8 colour mode SSD2123 Rev 0.50 P 30/75 Mar 2008 Solomon Systech

32 Double source amplifier (R15h) (POR = 0090h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W Sourceamp POR Sourceamp Control the source amplifier biasing current Sourceamp Status 0 Double source amplifier biasing current 1 Normal source amplifer biasing current SSD2123 Rev 0.50 P 31/75 Mar 2008 Solomon Systech

33 Pixel per line (R16h) (POR = EF8Eh when x400=0, POR = C786h when x400=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 POR(x400=0) POR(x400=1) Note Number of dotclk for hsync active low period must be smaller than that of HBP Only for 24-bit, 18-bit parallel and 8-bit, 6-bit serial interface. XL8-0 Set the number of valid pixel per line. XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 No. of pixel per line Step = (por if x400=1) Step = (por if x400=0) Reserved HBP6-0 Set the delay period from falling edge of HSYNC signal to first valid data. No. of clock cycle of DOTCLK HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 8-bit RGB 24-bit RGB (without dummy) (por if x400=1) (por if x400=0) 48 Step = 1 Step = SSD2123 Rev 0.50 P 32/75 Mar 2008 Solomon Systech

34 Example for 24-bit RGB interface Set by HBP6-0 Cycle time of HYSYNC Set by XL8-0 HFP HYSNC Default 480 pixels per line Pixel Data Dummy D0 D1 D2 D477 D478 D479 Dummy DOTCLK 8 clock cycles of DOTCLK HBP6-0 = Example for 8-bit RGB interface (without dummy) Cycle time of HYSYNC Set by HBP5-0 Set by XL8-0 HFP HYSNC Default 480 pixels per line Pixel Data Dummy D0 D479 Dummy DOTCLK 24 clock cycles of DOTCLK HBP5-0 = SSD2123 Rev 0.50 P 33/75 Mar 2008 Solomon Systech

35 Vertical Porch (R17h) (POR = 0003h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 POR VBP7-0 Set the delay period from falling edge of VSYNC to first valid line. The line data within this delay period will be treated as dummy line. VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 No. of clock cycle of HSYNC Step = * * * * Reserved Example for 24-bit RGB interface Set by VBP7-0 Cycle time of VSYNC VSYNC 272s HSYNC Dummy s 1 st Last VFP SSD2123 Rev 0.50 P 34/75 Mar 2008 Solomon Systech

36 Power Control 5 (R1Eh) (POR = 0034h) GAMAS=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W nmtp 0 VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 POR nmtp nmtp equals to 0 after power on reset and V COMH voltage equals to programmed MTP value. When nmtp set to 1, setting of VCM7-0 becomes valid and voltage of V COMH can be adjusted. VCM7-0 Set the V COMH voltage if nmtp = 1. These bits amplify the V COMH voltage to times the V LCD255 voltage. VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 V COMH V LCD255 x V LCD255 x Step = 1/ V LCD255 x V LCD255 x Note VCI < V COMH < AVDD Power Control 6 (R1Fh) (POR = 1834h) GAMAS=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VCMR7 VCRM6 VCMR5 VCMR4 VCMR3 VCMR2 VCMR1 VCMR0 POR Note R1F command register will only be valid when nmtp = 0. VCMR[70] To set the VCM[70] when nmtp = 0 which is equal to programmed MTP register(mtpr) value XOR with VCMR. These bits amplify the V COMH voltage to times the V LCD255 voltage. VCMR7 xor MTPR7 VCMR6 xor MTPR6 VCMR5 xor MTPR5 VCM[70] = VCMR[70] xor MTPR[70] VCMR4 xor MTPR4 VCMR3 xor MTPR3 VCMR2 xor MTPR2 VCMR1 xor MTPR1 VCMR0 xor MTPR0 V COMH VLCD255 x VLCD255 x Step = 1/ VLCD255 x VLCD255 x SSD2123 Rev 0.50 P 35/75 Mar 2008 Solomon Systech

37 9 EXTENDED COMMAND DESCRIPTION Reminder In order to activate extended command, user is required to send R28h-0006 prioir to the extended command in application. See below for further description on the R28h register. Gamma Buffer Biasing Current (R26h) (POR = 2800h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W IT2 IT1 IT POR IT2-0 Command Control Bit, the master control of the internal command decoder. This register provides function of software reset and MTP programming. IT2 IT1 IT0 Op-amp power Least Small Small to medium Medium Medium to large Large Large to Maximum Maximum VCOM MTP (R28h) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W CCB3 CCB2 CCB1 CCB0 POR CCB3-0 Command Control Bit, the master control of the internal command decoder. This register provides function of software reset and MTP programming. CCB3 CCB2 CCB1 CCB0 Usage Release Reset or no action Driver initialization Enable extended test command/ Enable for MTP Programming Fire MTP Reset all command bits to default All other setting Reserved VCOM Equalizing Period (R2Ah) (POR = 01D2h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W VCOMEQ2 VCOMEQ1 VCOMEQ0 POR VCOMEQ2-0 Sets the equalizing period on VCOM VCOMEQ2 VCOMEQ1 VCOMEQ0 EQ period No EQ clock cycle clock cycle clock cycle Xmod3 / Xmod3 / Xmod3 / Xmod3 / 2 Note Xmod3 is the number of dotclk of each subcolor. SSD2123 Rev 0.50 P 36/75 Mar 2008 Solomon Systech

38 Enable SDO (R2Bh) (POR = 0520h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 ENSDO FM1 FM0 0 0 POR ENSDO When ENSDO = 0, disable the SDO pin. When ENSDO = 1, enable the SDO pin, can read MTP or GPIO from SDO. FM1-0 Freeze VCOM SS1 SS0 Usage 0 X VCOM switching (por) 1 0 VCOM=VCOML 1 1 VCOM=VCOMH Secondary Booster Frequency (R2Ch) (POR = 3DDDh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W DCYT3 DCYT2 DCYT1 DCYT0 DCY3 DCY2 DCY1 DCY POR DCYT3-0 Set the step-up cycle of the step-up circuit for 8-color mode (CM = V DDIO ). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DCYT3 DCYT2 DCYT1 DCYT0 No. of dotclk (POR) Note For 416 dotclk per line, Horizontal line frequency (f H Typ. 14.8kHz, when dotclk=6.14mhz ) For 512 dotclk per line, Horizontal line frequency (f H Typ. 16.7kHz, when dotclk=8.54mhz ) For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline. DCYT3 DCYT2 DCYT1 DCYT0 Step-up cycle Fline 1 (max dotclk = 512) Fline Fline Fline 8 DCY3-0 Set the step-up cycle of the step-up circuit for 16.7M-color mode (CM = Vss). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption. DCY3 DCY2 DCY1 DCY0 No. of dotclk (POR) SSD2123 Rev 0.50 P 37/75 Mar 2008 Solomon Systech

39 Note For 416 dotclk per line, Horizontal line frequency (f H Typ. 14.8kHz, when dotclk=6.14mhz ) For 512 dotclk per line, Horizontal line frequency (f H Typ. 16.7kHz, when dotclk=8.54mhz ) For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline. DCY3 DCY2 DCY1 DCY0 Step-up cycle Fline 1 (max dotclk = 512) Fline Fline Fline 8 Software Shut (R2Dh) (POR = 3F40h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W UNREG 0 SS1 SS0 0 POR UNREG When UNREG = 1, VCIX2 primary booster is unregulated. When UNREG = 0, VCIX2 primary booster is regulated by VRC[20] register. SS1-0 Entering the shut mode by software command control SS1 SS0 Usage 0 X Follow SHUT pin status 1 0 S/W SHUT = 0, leave shut 1 1 S/W SHUT = 1, enter shut Read SDO (R2Eh) (POR = B544h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W ENMUX RSDO POR RSDO When RSDO = 0, Read MTP from SDO pin. When RSDO = 1, Read GPIO from SDO pin. ENMUX When ENMUX = 0, All gate tie to VGH for 4 lines period and then tie to VGL after shut mode. When ENMUX = 1, All gate tie to VGH after enter shut mode SSD2123 Rev 0.50 P 38/75 Mar 2008 Solomon Systech

40 10 MTP PROGRAMMING/ ERASE MTP Programming sequence Remark * The application setup should be synchronized. Note1 nmtp must set to 0 to activate the MTP effect. Note2 VCI is suggested to be larger than 3.3V during fire MTP. Precaution 1. All capacitors on MTP machine should be discharged completely before placing the LCD module. 2. The MTP programming voltage should not be applied when placing and removing the LCD module. 3. The MTP programming voltage should not be applied before VDDIO/VDDEXT/VCI. 4. After MTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before removing the LCD module. Figure 10-1 MTP programming circuitry SSD2123 Apply voltage at Step (4) Note C = 1uF (built-in on the module) VGH + C - GND 14.5V ±0.1V SSD2123 Rev 0.50 P 39/75 Mar 2008 Solomon Systech

41 Figure 10-2 MTP Programming Flowchart MTP Sequence Power up the module as application [e.g. V CI = 3.3V, V DDIO = 3.3V]* Turn on the display as normal mode to 16.7M color with a testing pattern if any Set nmtp = 1 in R1Eh Adjust VCOMH by VCM[70] in R1Eh Not optimum value Optimized VCOMH value Toggle reset pin Reset SSD2123 Connect a power supply to the module [V CI = V DDEXT = V DDIO = 3.3V]* Write commands for MTP initialization Register R28h R29h R2Dh Value 0006h 80C0h 3F50h Wait 200ms for activation Connect VGH with 14.5V power supply (Figure 10-3) Write the optimum value to VCM [70] in R1Eh and set nmtp = 1. Write command for firing MTP Register Value R28h 000Ah Wait 500ms for the process Power down the module and remove 14.5V power supply MTP completed SSD2123 Rev 0.50 P 40/75 Mar 2008 Solomon Systech

42 MTP Erase sequence Remark * The application setup should be synchronized. Precaution 1. All capacitors on MTP machine should be discharged completely before placing the LCD module. 2. The MTP erase voltage should not be applied when placing and removing the LCD module. 3. The MTP erase voltage should not be applied before V DDIO /V DDEXT /V CI. 4. After Erasing MTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before removing the LCD module. Figure 10-3 MTP Erase circuitry SSD2123 VGH + - Note C = 1uF GND (built-in on the module) GND 9V MTP Re-Write cycle Table 10-1 MTP Re-write cycle Characteristics Symbol Min Typ Max Units Re-write Cycle N Cycle Power Supply voltage for programming VGH V Power Supply voltage for erase VGH 9-12 V Program time Tprog s Erase time Terase s Note The suggested value is based on IC evaluation result which does not include ITO resistance. SSD2123 Rev 0.50 P 41/75 Mar 2008 Solomon Systech

43 Figure 10-4 MTP Erase Flowchart MTP Erase Sequence Turn off and Power down the module Connect a power supply to the module [e.g. V CI = 3.3V, V DDEXT = V DDIO = 3.3V, REGVDD =High]* Toggle reset pin to reset the module Write commands for erase MTP initialization Register Value R28h 0006h R29h 80C0h R2Dh 3F50h R0Fh 013Fh Wait 200ms for activation Connect VGH with 9V power supply (Figure 10-3) Write command for erasing MTP Register Value R28h 0008h Wait 1s for the process Write command for disable erasing MTP Register Value R28h 0000h Power down the module and remove 9V power supply MTP Erase completed SSD2123 Rev 0.50 P 42/75 Mar 2008 Solomon Systech

44 11 Gamma Adjustment Function The SSD2123 incorporates gamma adjustment function for the 16M-color display. Gamma adjustment is implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid crystal panel s specification. RGB Interface Display Data R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 G7 G6 G5 G4 G3 G2 G1 G0 Positive polarity register PKP02 PKP01 PKP00 PKP12 PKP11 PKP10 PKP22 PKP21 PKP20 PKP32 PKP31 PKP30 PKP42 PKP41 PKP40 PKP52 PKP51 PKP50 PRP02 PRP01 PRP00 PRP12 PRP11 PRP10 VRP03 VRP02 VRP01 VRP00 VRP14 VRP13 VRP12 VRP11 VRP10 Negative polarity PKN02 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN32 PKN31 PKN30 PKN42 PKN41 PKN40 register R G B PKN52 PKN51 PKN50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 VRN03 VRN02 VRN01 VRN00 VRN14 VRN13 VRN12 VRN11 VRN10 8-levels 64 levels Grayscale amplifier V0 V grayscale Control <R> 8-bits 8-bits 8-bits 256 grayscale Control <G> LCD Driver LCD Driver LCD Driver LCD 256 grayscale Control <B> SSD2123 Rev 0.50 P 43/75 Mar 2008 Solomon Systech

45 11.1 Structure of Grayscale Amplifier Below figure indicates the structure of the grayscale amplifier. It determines 8 levels (VIN0-VIN7) by the gradient adjuster and the micro adjustment register. Also, dividing these levels with ladder resistors generates V0 to V255. VLCD255 Gradient adjustment register PRP0 PRP1 Micro adjustment register Amplitude adjustment register PKP0 PKP1 PKP2 PKP3 PKP4 PKP5 VRP0 VRP VINP0 V0 8 to 1 selector VINP1 V4 V18 8 to 1 selector VINP2 V32 V56 Ladder resistor 8 to 1 selector 8 to 1 selector VINP3 VINP4 Grayscale Amplifier V80 V118 V156 V190 8 to 1 selector VINP5 V224 V238 8 to 1 selector VINP6 V252 V253 VINP7 V255 GND * Individual ladder resistors are used for positive and negative polarity. SSD2123 Rev 0.50 P 44/75 Mar 2008 Solomon Systech

46 Ladder resistor for positive polarity Ladder resistor for negative polarity VLCD255 0 to 30R VRP0 5R 4R RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 VRP0[30] KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 8 to 1 selector VINP0 PKP0[20] VINP1 VRN0 5R 4R RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 VRN0[30] KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 8 to 1 selector VINN0 PKN0[20] VINN1 0 to 28R VRHP 1R 5R 1R 16R 1R 5R 1R RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38 PRP0[20] KVP9 KVP10 KVP11 KVP12 KVP13 8 to 1 KVP14 selector KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 8 to 1 KVP22 selector KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 8 to 1 KVP30 selector KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 8 to 1 KVP38 selector KVP39 KVP40 PKP1[20] VINP2 PKP2[20] VINP3 PKP3[20] VINP4 PKP4[20] VINP5 0 to 28R VRHN 1R 5R 1R 16R 1R 5R 1R RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 PRN0[20] KVN9 KVN10 KVN11 KVN12 KVN13 8 to 1 KVN14selector KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 8 to 1 KVN22selector KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 8 to 1 KVN30selector KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 8 to 1 KVN38 selector KVN39 KVN40 PKN1[20] VINN2 PKN2[20] VINN3 PKN3[20] VINN4 PKN4[20] VINN5 0 to 28R VRLP 4R 5R 0 to 31R VRP1 8R RP39 RP40 RP41 RP42 RP43 RP44 RP45 RP46 RP47 PRP1[20] KVP41 KVP42 KVP43 KVP44 KVP45 8 to 1 KVP46 selector KVP47 KVP48 VRP1[40] PKP5[20] VINP6 VINP7 0 to 28R VRLN 4R 5R 0 to 31R VRN1 8R RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 RN47 PRN1[20] KVN41 KVN42 KVN43 KVN44 KVN45 8 to 1 KVN46 selector KVN47 KVN48 VRN1[40] PKN5[20] VINN6 VINN7 GND SSD2123 Rev 0.50 P 45/75 Mar 2008 Solomon Systech

47 11.2 Gamma Adjustment Register This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This register can independent set up to positive/negative polarities and there are three types of register groups to adjust gradient, amplitude, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. (Using the same setting for Reference-value and R.G.B.) Following graphics indicates the operation of each adjusting register. Gradient adjustment Amplitude adjustment Micro adjustment Grayscale Voltage Grayscale Voltage Grayscale Voltage Grayscale Number Grayscale Number Grayscale Number Gradient adjusting register The gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistors in the middle of the ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive Amplitude adjusting register The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it controls the variable resistors in the boundary of the ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities as well as the gradientadjusting resistor Micro adjusting register The micro-adjusting register is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls each reference voltage level by the 8 to 1 selector towards the 8-level reference voltage generated from the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. SSD2123 Rev 0.50 P 46/75 Mar 2008 Solomon Systech

48 11.3 Ladder Resistor / 8 to 1 selector This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. The gamma registers control the variable resistors and 8 to 1 selector resistors. Variable Resistor There are 3 types of the variable resistors that are for the gradient and amplitude adjustment. The resistance is set by the resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0 / VRP(N)1) as below. PRP(N)[01] Resistance VRP(N)0 Resistance VRP(N)1 Resistance 000 0R R R 001 4R R R 010 8R R R 8 to 1 selecter R R R Step = 2R Step = 1R R R R R R R In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which are generated by the ladder resistors. There are six types of reference voltage (VIN1 to VIN6) and totally 48 divided voltages can be selected in one ladder resistor. Following figure explains the relationship between the micro-adjusting register and the selecting voltage. Postive polarity Negative polarity Registor Selected voltage Registor Selected voltage PKP[20] VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 PKN[20] VINN1 VINN2 VINN3 VINN4 VINN5 VINN6 000 KVP1 KVP9 KVP17 KVP25 KVP33 KVP KVN1 KVN9 KVN17 KVN25 KVN33 KVN KVP2 KVP10 KVP18 KVP26 KVP34 KVP KVN2 KVN10 KVN18 KVN26 KVN34 KVN KVP3 KVP11 KVP19 KVP27 KVP35 KVP KVN3 KVN11 KVN19 KVN27 KVN35 KVN KVP4 KVP12 KVP20 KVP28 KVP36 KVP KVN4 KVN12 KVN20 KVN28 KVN36 KVN KVP5 KVP13 KVP21 KVP29 KVP37 KVP KVN5 KVN13 KVN21 KVN29 KVN37 KVN KVP6 KVP14 KVP22 KVP30 KVP38 KVP KVN6 KVN14 KVN22 KVN30 KVN38 KVN KVP7 KVP15 KVP23 KVP31 KVP39 KVP KVN7 KVN15 KVN23 KVN31 KVN39 KVN KVP8 KVP16 KVP24 KVP32 KVP40 KVP KVN8 KVN16 KVN24 KVN32 KVN40 KVN48 SSD2123 Rev 0.50 P 47/75 Mar 2008 Solomon Systech

49 Grayscale Grayscale Grayscale Formula Formula voltage voltage voltage Formula V0 VINP(N)0 V43 (V32-V80)*(37/48)+V80 V86 (V80-V176)*(90/96)+V176 V1 (V0-V4)*(30/40)+V4 V44 (V32-V80)*(36/48)+V80 V87 (V80-V176)*(89/96)+V176 V2 (V0-V4)*(20/40)+V4 V45 (V32-V80)*(35/48)+V80 V88 (V80-V176)*(88/96)+V176 V3 (V0-V4)*(10/40)+V4 V46 (V32-V80)*(34/48)+V80 V89 (V80-V176)*(87/96)+V176 V4 VINP(N)1 V47 (V32-V80)*(33/48)+V80 V90 (V80-V176)*(86/96)+V176 V5 (V4-V32)*(174/192)+V32 V48 (V32-V80)*(32/48)+V80 V91 (V80-V176)*(85/96)+V176 V6 (V4-V32)*(156/192)+V32 V49 (V32-V80)*(31/48)+V80 V92 (V80-V176)*(84/96)+V176 V7 (V4-V32)*(138/192)+V32 V50 (V32-V80)*(30/48)+V80 V93 (V80-V176)*(83/96)+V176 V8 (V4-V32)*(120/192)+V32 V51 (V32-V80)*(29/48)+V80 V94 (V80-V176)*(82/96)+V176 V9 (V4-V32)*(113/192)+V32 V52 (V32-V80)*(28/48)+V80 V95 (V80-V176)*(81/96)+V176 V10 (V4-V32)*(106/192)+V32 V53 (V32-V80)*(27/48)+V80 V96 (V80-V176)*(80/96)+V176 V11 (V4-V32)*(99/192)+V32 V54 (V32-V80)*(26/48)+V80 V97 (V80-V176)*(79/96)+V176 V12 (V4-V32)*(92/192)+V32 V55 (V32-V80)*(25/48)+V80 V98 (V80-V176)*(78/96)+V176 V13 (V4-V32)*(85/192)+V32 V56 (V32-V80)*(24/48)+V80 V99 (V80-V176)*(77/96)+V176 V14 (V4-V32)*(78/192)+V32 V57 (V32-V80)*(23/48)+V80 V100 (V80-V176)*(76/96)+V176 V15 (V4-V32)*(71/192)+V32 V58 (V32-V80)*(22/48)+V80 V101 (V80-V176)*(75/96)+V176 V16 (V4-V32)*(64/192)+V32 V59 (V32-V80)*(21/48)+V80 V102 (V80-V176)*(74/96)+V176 V17 (V4-V32)*(60/192)+V32 V60 (V32-V80)*(20/48)+V80 V103 (V80-V176)*(73/96)+V176 V18 (V4-V32)*(56/192)+V32 V61 (V32-V80)*(19/48)+V80 V104 (V80-V176)*(72/96)+V176 V19 (V4-V32)*(52/192)+V32 V62 (V32-V80)*(18/48)+V80 V105 (V80-V176)*(71/96)+V176 V20 (V4-V32)*(48/192)+V32 V63 (V32-V80)*(17/48)+V80 V106 (V80-V176)*(70/96)+V176 V21 (V4-V32)*(44/192)+V32 V64 (V32-V80)*(16/48)+V80 V107 (V80-V176)*(69/96)+V176 V22 (V4-V32)*(40/192)+V32 V65 (V32-V80)*(15/48)+V80 V108 (V80-V176)*(68/96)+V176 V23 (V4-V32)*(36/192)+V32 V66 (V32-V80)*(14/48)+V80 V109 (V80-V176)*(67/96)+V176 V24 (V4-V32)*(32/192)+V32 V67 (V32-V80)*(13/48)+V80 V110 (V80-V176)*(66/96)+V176 V25 (V4-V32)*(28/192)+V32 V68 (V32-V80)*(12/48)+V80 V111 (V80-V176)*(65/96)+V176 V26 (V4-V32)*(24/192)+V32 V69 (V32-V80)*(11/48)+V80 V112 (V80-V176)*(64/96)+V176 V27 (V4-V32)*(20/192)+V32 V70 (V32-V80)*(10/48)+V80 V113 (V80-V176)*(63/96)+V176 V28 (V4-V32)*(16/192)+V32 V71 (V32-V80)*(9/48)+V80 V114 (V80-V176)*(62/96)+V176 V29 (V4-V32)*(12/192)+V32 V72 (V32-V80)*(8/48)+V80 V115 (V80-V176)*(61/96)+V176 V30 (V4-V32)*(8/192)+V32 V73 (V32-V80)*(7/48)+V80 V116 (V80-V176)*(60/96)+V176 V31 (V4-V32)*(4/192)+V32 V74 (V32-V80)*(6/48)+V80 V117 (V80-V176)*(59/96)+V176 V32 VINP(N)2 V75 (V32-V80)*(5/48)+V80 V118 (V80-V176)*(58/96)+V176 V33 (V32-V80)*(47/48)+V80 V76 (V32-V80)*(4/48)+V80 V119 (V80-V176)*(57/96)+V176 V34 (V32-V80)*(46/48)+V80 V77 (V32-V80)*(3/48)+V80 V120 (V80-V176)*(56/96)+V176 V35 (V32-V80)*(45/48)+V80 V78 (V32-V80)*(2/48)+V80 V121 (V80-V176)*(55/96)+V176 V36 (V32-V80)*(44/48)+V80 V79 (V32-V80)*(1/48)+V80 V122 (V80-V176)*(54/96)+V176 V37 (V32-V80)*(43/48)+V80 V80 VINP(N)3 V123 (V80-V176)*(53/96)+V176 V38 (V32-V80)*(42/48)+V80 V81 (V80-V176)*(95/96)+V176 V124 (V80-V176)*(52/96)+V176 V39 (V32-V80)*(41/48)+V80 V82 (V80-V176)*(94/96)+V176 V125 (V80-V176)*(51/96)+V176 V40 (V32-V80)*(40/48)+V80 V83 (V80-V176)*(93/96)+V176 V126 (V80-V176)*(50/96)+V176 V41 (V32-V80)*(39/48)+V80 V84 (V80-V176)*(92/96)+V176 V127 (V80-V176)*(49/96)+V176 V42 (V32-V80)*(38/48)+V80 V85 (V80-V176)*(91/96)+V176 V128 (V80-V176)*(48/96)+V176 SSD2123 Rev 0.50 P 48/75 Mar 2008 Solomon Systech

50 Grayscale Grayscale Grayscale Formula Formula voltage voltage voltage Formula V129 (V80-V176)*(47/96)+V176 V172 (V80-V176)*(4/96)+V176 V215 (V176-V224)*(9/48)+V224 V130 (V80-V176)*(46/96)+V176 V173 (V80-V176)*(3/96)+V176 V216 (V176-V224)*(8/48)+V224 V131 (V80-V176)*(45/96)+V176 V174 (V80-V176)*(2/96)+V176 V217 (V176-V224)*(7/48)+V224 V132 (V80-V176)*(44/96)+V176 V175 (V80-V176)*(1/96)+V176 V218 (V176-V224)*(6/48)+V224 V133 (V80-V176)*(43/96)+V176 V176 VINP(N)4 V219 (V176-V224)*(5/48)+V224 V134 (V80-V176)*(42/96)+V176 V177 (V176-V224)*(47/48)+V224 V220 (V176-V224)*(4/48)+V224 V135 (V80-V176)*(41/96)+V176 V178 (V176-V224)*(46/48)+V224 V221 (V176-V224)*(3/48)+V224 V136 (V80-V176)*(40/96)+V176 V179 (V176-V224)*(45/48)+V224 V222 (V176-V224)*(2/48)+V224 V137 (V80-V176)*(39/96)+V176 V180 (V176-V224)*(44/48)+V224 V223 (V176-V224)*(1/48)+V224 V138 (V80-V176)*(38/96)+V176 V181 (V176-V224)*(43/48)+V224 V224 VINP(N)5 V139 (V80-V176)*(37/96)+V176 V182 (V176-V224)*(42/48)+V224 V225 (V224-V252)*(188/192)+V252 V140 (V80-V176)*(36/96)+V176 V183 (V176-V224)*(41/48)+V224 V226 (V224-V252)*(184/192)+V252 V141 (V80-V176)*(35/96)+V176 V184 (V176-V224)*(40/48)+V224 V227 (V224-V252)*(180/192)+V252 V142 (V80-V176)*(34/96)+V176 V185 (V176-V224)*(39/48)+V224 V228 (V224-V252)*(176/192)+V252 V143 (V80-V176)*(33/96)+V176 V186 (V176-V224)*(38/48)+V224 V229 (V224-V252)*(172/192)+V252 V144 (V80-V176)*(32/96)+V176 V187 (V176-V224)*(37/48)+V224 V230 (V224-V252)*(168/192)+V252 V145 (V80-V176)*(31/96)+V176 V188 (V176-V224)*(36/48)+V224 V231 (V224-V252)*(164/192)+V252 V146 (V80-V176)*(30/96)+V176 V189 (V176-V224)*(35/48)+V224 V232 (V224-V252)*(160/192)+V252 V147 (V80-V176)*(29/96)+V176 V190 (V176-V224)*(34/48)+V224 V233 (V224-V252)*(156/192)+V252 V148 (V80-V176)*(28/96)+V176 V191 (V176-V224)*(33/48)+V224 V234 (V224-V252)*(152/192)+V252 V149 (V80-V176)*(27/96)+V176 V192 (V176-V224)*(32/48)+V224 V235 (V224-V252)*(148/192)+V252 V150 (V80-V176)*(26/96)+V176 V193 (V176-V224)*(31/48)+V224 V236 (V224-V252)*(144/192)+V252 V151 (V80-V176)*(25/96)+V176 V194 (V176-V224)*(30/48)+V224 V237 (V224-V252)*(140/192)+V252 V152 (V80-V176)*(24/96)+V176 V195 (V176-V224)*(29/48)+V224 V238 (V224-V252)*(136/192)+V252 V153 (V80-V176)*(23/96)+V176 V196 (V176-V224)*(28/48)+V224 V239 (V224-V252)*(132/192)+V252 V154 (V80-V176)*(22/96)+V176 V197 (V176-V224)*(27/48)+V224 V240 (V224-V252)*(128/192)+V252 V155 (V80-V176)*(21/96)+V176 V198 (V176-V224)*(26/48)+V224 V241 (V224-V252)*(121/192)+V252 V156 (V80-V176)*(20/96)+V176 V199 (V176-V224)*(25/48)+V224 V242 (V224-V252)*(114/192)+V252 V157 (V80-V176)*(19/96)+V176 V200 (V176-V224)*(24/48)+V224 V243 (V224-V252)*(107/192)+V252 V158 (V80-V176)*(18/96)+V176 V201 (V176-V224)*(23/48)+V224 V244 (V224-V252)*(100/192)+V252 V159 (V80-V176)*(17/96)+V176 V202 (V176-V224)*(22/48)+V224 V245 (V224-V252)*(93/192)+V252 V160 (V80-V176)*(16/96)+V176 V203 (V176-V224)*(21/48)+V224 V246 (V224-V252)*(86/192)+V252 V161 (V80-V176)*(15/96)+V176 V204 (V176-V224)*(20/48)+V224 V247 (V224-V252)*(79/192)+V252 V162 (V80-V176)*(14/96)+V176 V205 (V176-V224)*(19/48)+V224 V248 (V224-V252)*(72/192)+V252 V163 (V80-V176)*(13/96)+V176 V206 (V176-V224)*(18/48)+V224 V249 (V224-V252)*(54/192)+V252 V164 (V80-V176)*(12/96)+V176 V207 (V176-V224)*(17/48)+V224 V250 (V224-V252)*(36/192)+V252 V165 (V80-V176)*(11/96)+V176 V208 (V176-V224)*(16/48)+V224 V251 (V224-V252)*(18/192)+V252 V166 (V80-V176)*(10/96)+V176 V209 (V176-V224)*(15/48)+V224 V252 VINP(N)6 V167 (V80-V176)*(9/96)+V176 V210 (V176-V224)*(14/48)+V224 V253 (V252-V255)*(20/30)+V255 V168 (V80-V176)*(8/96)+V176 V211 (V176-V224)*(13/48)+V224 V254 (V252-V255)*(10/30)+V255 V169 (V80-V176)*(7/96)+V176 V212 (V176-V224)*(12/48)+V224 V255 VINP(N)7 V170 (V80-V176)*(6/96)+V176 V213 (V176-V224)*(11/48)+V224 V171 (V80-V176)*(5/96)+V176 V214 (V176-V224)*(10/48)+V224 SSD2123 Rev 0.50 P 49/75 Mar 2008 Solomon Systech

51 Reference voltage of positive polarity Reference Formula Micr0-adjusting rgister Reference voltage KVP0 VLCD255 - V x VRP0 / SUMRP -- VINP0 KVP1 VLCD255 - V x (VRP0 + 5R) / SUMRP PKP0[20] = 000 KVP2 VLCD255 - V x (VRP0 + 9R) / SUMRP PKP0[20] = 001 KVP3 VLCD255 - V x (VRP0 + 13R) / SUMRP PKP0[20] = 010 KVP4 VLCD255 - V x (VRP0 + 17R) / SUMRP PKP0[20] = 011 KVP5 VLCD255 - V x (VRP0 + 21R) / SUMRP PKP0[20] = 100 VINP1 KVP6 VLCD255 - V x (VRP0 + 25R) / SUMRP PKP0[20] = 101 KVP7 VLCD255 - V x (VRP0 + 29R) / SUMRP PKP0[20] = 110 KVP8 VLCD255 - V x (VRP0 + 33R) / SUMRP PKP0[20] = 111 KVP9 VLCD255 - V x (VRP0 + 33R + VRHP) / SUMRP PKP1[20] = 000 KVP10 VLCD255 - V x (VRP0 + 34R + VRHP) / SUMRP PKP1[20] = 001 KVP11 VLCD255 - V x (VRP0 + 35R + VRHP) / SUMRP PKP1[20] = 010 KVP12 VLCD255 - V x (VRP0 + 36R + VRHP) / SUMRP PKP1[20] = 011 KVP13 VLCD255 - V x (VRP0 + 37R + VRHP) / SUMRP PKP1[20] = 100 VINP2 KVP14 VLCD255 - V x (VRP0 + 38R + VRHP) / SUMRP PKP1[20] = 101 KVP15 VLCD255 - V x (VRP0 + 39R + VRHP) / SUMRP PKP1[20] = 110 KVP16 VLCD255 - V x (VRP0 + 40R + VRHP) / SUMRP PKP1[20] = 111 KVP17 VLCD255 - V x (VRP0 + 45R + VRHP) / SUMRP PKP2[20] = 000 KVP18 VLCD255 - V x (VRP0 + 46R + VRHP) / SUMRP PKP2[20] = 001 KVP19 VLCD255 - V x (VRP0 + 47R + VRHP) / SUMRP PKP2[20] = 010 KVP20 VLCD255 - V x (VRP0 + 48R + VRHP) / SUMRP PKP2[20] = 011 KVP21 VLCD255 - V x (VRP0 + 49R + VRHP) / SUMRP PKP2[20] = 100 VINP3 KVP22 VLCD255 - V x (VRP0 + 50R + VRHP) / SUMRP PKP2[20] = 101 KVP23 VLCD255 - V x (VRP0 + 51R + VRHP) / SUMRP PKP2[20] = 110 KVP24 VLCD255 - V x (VRP0 + 52R + VRHP) / SUMRP PKP2[20] = 111 KVP25 VLCD255 - V x (VRP0 + 68R + VRHP) / SUMRP PKP3[20] = 000 KVP26 VLCD255 - V x (VRP0 + 69R + VRHP) / SUMRP PKP3[20] = 001 KVP27 VLCD255 - V x (VRP0 + 70R + VRHP) / SUMRP PKP3[20] = 010 KVP28 VLCD255 - V x (VRP0 + 71R + VRHP) / SUMRP PKP3[20] = 011 KVP29 VLCD255 - V x (VRP0 + 72R + VRHP) / SUMRP PKP3[20] = 100 VINP4 KVP30 VLCD255 - V x (VRP0 + 73R + VRHP) / SUMRP PKP3[20] = 101 KVP31 VLCD255 - V x (VRP0 + 74R + VRHP) / SUMRP PKP3[20] = 110 KVP32 VLCD255 - V x (VRP0 + 75R + VRHP) / SUMRP PKP3[20] = 111 KVP33 VLCD255 - V x (VRP0 + 80R + VRHP) / SUMRP PKP4[20] = 000 KVP34 VLCD255 - V x (VRP0 + 81R + VRHP) / SUMRP PKP4[20] = 001 KVP35 VLCD255 - V x (VRP0 + 82R + VRHP) / SUMRP PKP4[20] = 010 KVP36 VLCD255 - V x (VRP0 + 83R + VRHP) / SUMRP PKP4[20] = 011 KVP37 VLCD255 - V x (VRP0 + 84R + VRHP) / SUMRP PKP4[20] = 100 VINP5 KVP38 VLCD255 - V x (VRP0 + 85R + VRHP) / SUMRP PKP4[20] = 101 KVP39 VLCD255 - V x (VRP0 + 86R + VRHP) / SUMRP PKP4[20] = 110 KVP40 VLCD255 - V x (VRP0 + 87R + VRHP) / SUMRP PKP4[20] = 111 KVP41 VLCD255 - V x (VRP0 + 87R + VRHP + VRLP) / SUMRP PKP5[20] = 000 KVP42 VLCD255 - V x (VRP0 + 91R + VRHP + VRLP) / SUMRP PKP5[20] = 001 KVP43 VLCD255 - V x (VRP0 + 91R + VRHP + VRLP) / SUMRP PKP5[20] = 010 KVP44 VLCD255 - V x (VRP0 + 99R + VRHP + VRLP) / SUMRP PKP5[20] = 011 KVP45 VLCD255 - V x (VRP R + VRHP + VRLP) / SUMRP PKP5[20] = 100 VINP6 KVP46 VLCD255 - V x (VRP R + VRHP + VRLP) / SUMRP PKP5[20] = 101 KVP47 VLCD255 - V x (VRP R + VRHP + VRLP) / SUMRP PKP5[20] = 110 KVP48 VLCD255 - V x (VRP R + VRHP + VRLP) / SUMRP PKP5[20] = 111 KVP49 VLCD255 - V x (VRP R + VRHP + VRLP) / SUMRP -- VINP7 SUMRP Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1 V Voltage difference between VLCD255 and of GND. SSD2123 Rev 0.50 P 50/75 Mar 2008 Solomon Systech

52 Reference voltage of negative polarity Reference Formula Micr0-adjusting rgister Reference voltage KVN0 VLCD255 - V x VRN0 / SUMRN -- VINN0 KVN1 VLCD255 - V x (VRN0 + 5R) / SUMRN PKN0[20] = 000 KVN2 VLCD255 - V x (VRN0 + 9R) / SUMRN PKN0[20] = 001 KVN3 VLCD255 - V x (VRN0 + 13R) / SUMRN PKN0[20] = 010 KVN4 VLCD255 - V x (VRN0 + 17R) / SUMRN PKN0[20] = 011 KVN5 VLCD255 - V x (VRN0 + 21R) / SUMRN PKN0[20] = 100 VINN1 KVN6 VLCD255 - V x (VRN0 + 25R) / SUMRN PKN0[20] = 101 KVN7 VLCD255 - V x (VRN0 + 29R) / SUMRN PKN0[20] = 110 KVN8 VLCD255 - V x (VRN0 + 33R) / SUMRN PKN0[20] = 111 KVN9 VLCD255 - V x (VRN0 + 33R + VRHN) / SUMRN PKN1[20] = 000 KVN10 VLCD255 - V x (VRN0 + 34R + VRHN) / SUMRN PKN1[20] = 001 KVN11 VLCD255 - V x (VRN0 + 35R + VRHN) / SUMRN PKN1[20] = 010 KVN12 VLCD255 - V x (VRN0 + 36R + VRHN) / SUMRN PKN1[20] = 011 KVN13 VLCD255 - V x (VRN0 + 37R + VRHN) / SUMRN PKN1[20] = 100 VINN2 KVN14 VLCD255 - V x (VRN0 + 38R + VRHN) / SUMRN PKN1[20] = 101 KVN15 VLCD255 - V x (VRN0 + 39R + VRHN) / SUMRN PKN1[20] = 110 KVN16 VLCD255 - V x (VRN0 + 40R + VRHN) / SUMRN PKN1[20] = 111 KVN17 VLCD255 - V x (VRN0 + 45R + VRHN) / SUMRN PKN2[20] = 000 KVN18 VLCD255 - V x (VRN0 + 46R + VRHN) / SUMRN PKN2[20] = 001 KVN19 VLCD255 - V x (VRN0 + 47R + VRHN) / SUMRN PKN2[20] = 010 KVN20 VLCD255 - V x (VRN0 + 48R + VRHN) / SUMRN PKN2[20] = 011 KVN21 VLCD255 - V x (VRN0 + 49R + VRHN) / SUMRN PKN2[20] = 100 VINN3 KVN22 VLCD255 - V x (VRN0 + 50R + VRHN) / SUMRN PKN2[20] = 101 KVN23 VLCD255 - V x (VRN0 + 51R + VRHN) / SUMRN PKN2[20] = 110 KVN24 VLCD255 - V x (VRN0 + 52R + VRHN) / SUMRN PKN2[20] = 111 KVN25 VLCD255 - V x (VRN0 + 68R + VRHN) / SUMRN PKN3[20] = 000 KVN26 VLCD255 - V x (VRN0 + 69R + VRHN) / SUMRN PKN3[20] = 001 KVN27 VLCD255 - V x (VRN0 + 70R + VRHN) / SUMRN PKN3[20] = 010 KVN28 VLCD255 - V x (VRN0 + 71R + VRHN) / SUMRN PKN3[20] = 011 KVN29 VLCD255 - V x (VRN0 + 72R + VRHN) / SUMRN PKN3[20] = 100 VINN4 KVN30 VLCD255 - V x (VRN0 + 73R + VRHN) / SUMRN PKN3[20] = 101 KVN31 VLCD255 - V x (VRN0 + 74R + VRHN) / SUMRN PKN3[20] = 110 KVN32 VLCD255 - V x (VRN0 + 75R + VRHN) / SUMRN PKN3[20] = 111 KVN33 VLCD255 - V x (VRN0 + 80R + VRHN) / SUMRN PKN4[20] = 000 KVN34 VLCD255 - V x (VRN0 + 81R + VRHN) / SUMRN PKN4[20] = 001 KVN35 VLCD255 - V x (VRN0 + 82R + VRHN) / SUMRN PKN4[20] = 010 KVN36 VLCD255 - V x (VRN0 + 83R + VRHN) / SUMRN PKN4[20] = 011 KVN37 VLCD255 - V x (VRN0 + 84R + VRHN) / SUMRN PKN4[20] = 100 VINN5 KVN38 VLCD255 - V x (VRN0 + 85R + VRHN) / SUMRN PKN4[20] = 101 KVN39 VLCD255 - V x (VRN0 + 86R + VRHN) / SUMRN PKN4[20] = 110 KVN40 VLCD255 - V x (VRN0 + 87R + VRHN) / SUMRN PKN4[20] = 111 KVN41 VLCD255 - V x (VRN0 + 87R + VRHN + VRLN) / SUMRN PKN5[20] = 000 KVN42 VLCD255 - V x (VRN0 + 91R + VRHN + VRLN) / SUMRN PKN5[20] = 001 KVN43 VLCD255 - V x (VRN0 + 95R + VRHN + VRLN) / SUMRN PKN5[20] = 010 KVN44 VLCD255 - V x (VRN0 + 99R + VRHN + VRLN) / SUMRN PKN5[20] = 011 KVN45 VLCD255 - V x (VRN R + VRHN + VRLN) / SUMRN PKN5[20] = 100 VINN6 KVN46 VLCD255 - V x (VRN R + VRHN + VRLN) / SUMRN PKN5[20] = 101 KVN47 VLCD255- V x (VRN R + VRHN + VRLN) / SUMRN PKN5[20] = 110 KVN48 VLCD255 - V x (VRN R + VRHN + VRLN) / SUMRN PKN5[20] = 111 KVN49 VLCD255 - V x (VRN R + VRHN + VRLN) / SUMRN -- VINN7 SUMRN Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 V Voltage difference between VLCD255 and of GND. SSD2123 Rev 0.50 P 51/75 Mar 2008 Solomon Systech

53 12 Block Function Description 12.1 Serial Interface Serial Interface 4-wires (8 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB.SDC determinate the data of SDI which is register or data. Transfer starts Transfer ends Transfer starts Transfer ends Transfer starts Transfer ends CSB SDC SCK SDI MSB DB DB DB DB DB DB DB LSB DB 0 MSB DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 LSB DB 8 MSB DB 7 LSB DB DB DB DB DB DB DB Register Data Data Example of 4-wires (8 bits) Frame 1 (Command 10h) Frame 2 (Data 5Ah) Transfer starts Transfer ends Transfer starts Transfer ends CSB CSB SDC SDC SCK SCK SDI SDI CSB Transfer starts Frame 3 (Data 78h) Transfer ends SDC SCK SDI SSD2123 Rev 0.50 P 52/75 Mar 2008 Solomon Systech

54 Serial Interface 3-wires (9 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB. DC bit determinate the data of SDI which is register or data. Transfer starts Transfer ends Transfer starts Transfer ends Transfer starts Transfer ends CSB SCK SDI MSB LSB C DB DB DB DB DB DB DB DB MSB D DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 LSB DB 8 MSB D DB DB DB DB DB DB DB LSB DB 0 Register Data Data Example of 3-wires (9 bits) Frame 1 (Command 10h) Frame 2 (Data 5Ah) Transfer starts Transfer ends Transfer starts Transfer ends CSB CSB SCK SCK SDI SDI CSB Transfer starts Frame 3 (Data 78h) Transfer ends SCK SDI SSD2123 Rev 0.50 P 53/75 Mar 2008 Solomon Systech

55 Serial Interface 3-wires (24 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI), and serial output data (SDO). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB. DC bit determinate the data of SDI which is register or data. RW bit determinate the read / write operation. Write Transfer starts CSB Transfer ends SCK SDI ID DC RW MSB DB 15 DB 14 DB 13 DB 2 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 LSB DB 0 Device ID code Start byte DC RW Index register setting / Instruction, Read 32Bits SPI interface for read cycle Transfer starts Transfer ends CSB SCK MSB LSB SDI ID D R x x x x x x x x x x x x x x x x x x x x x x x x Device ID DC RW code Start byte SDO RSDO=1 MSB x x x x x x x x MSB GPI GPI GPI GPI x x x x GPI[30] LSB x x x x x x x x LSB SDO RSDO=0 x MTP MTP MTP MTP MTP MTP MTP[60] MTP 0 x x x x x x x x MTP 7 6 MTP 5 4 MTP 3 2 MTP 1 MTP[70] MTP 0 Command Code 1. R28hx0006h enable R2x command 2. R2Bhx8540h enable SDO read 3. R2EhxB544h enable MTP read status (RSDO=0) or R2EhxB564h enable GPI read status (RSDO=1) SSD2123 Rev 0.50 P 54/75 Mar 2008 Solomon Systech

56 12.2 Data Control The display data and frame position information from the controller is synchronized with the Gate Drive circuit and shift registered for the Source Driver circuit Booster and Regulator Circuit These two functional blocks generate the voltage of V GH, V GL, V COM and V LCD255 which are necessary for operating a TFT LCD Shift Register The shift registers control the direction of line scanning of source and gate Data Latches This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the Source Driver to output the required voltage level Reset Circuit This block is integrated into the Interface Logic which includes Power On Reset circuitry and the hardware reset pin, RES. Both of these having the same reset function. Once the RES pin receives a negative reset pulse, all internal circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 10us. The status of the chip after reset is given in Command Table SSD2123 Rev 0.50 P 55/75 Mar 2008 Solomon Systech

57 13 DC CHARACTERISTICS DC Characteristics (Unless otherwise specified, Voltage Referenced to V SS, T A = -40 to 85 o C) Symbol Parameter Test Condition Min Typ Max Unit V DDIO Power supply pin of IO pins Recommend Operating Voltage Possible Operating Voltage V V CI Booster Reference Supply Voltage Recommend Operating Voltage Range (3) Possible Operating Voltage 2.5 or V DDIO V I sleep1 Sleep mode current (VCI pin) ua VDDEXT=VDDIO=3.3V, VCI=3.3V I sleep2 Sleep mode current (VDDIO) ua I dp Operating mode current 100pF loading at Source output VDDEXT=VDDIO=3.3V, VCI=3.3V ma V CIM Negative V CI Output Voltage No panel loading -V CI - - V 1 No panel loading, ITO for CYP, CYN, AVDD, 91 - % AV DD AV DD x 2 primary booster efficiency VCI and VCHS = 10 Ohm V No panel loading; 4x booster; ITO for CYP, CYN, AVDD, VCI and VCHS = 10 Ohm TBA % V GH Gate driver High Output Voltage No panel loading; 5x booster; ITO for CYP, Booster efficiency 2 CYN, AVDD, VCI and VCHS = 10 Ohm TBA % No panel loading; 6x booster; ITO for CYP, TBA 80 - % CYN, AVDD, VCI and VCHS = 10 Ohm V GL Gate driver Low Output Voltage V V COMH VCOM High Output Voltage V V COML VCOM Low Output Voltage V CIM V V COMA VCOMA V V COMH - V COML V V LCD255 V LCD255 Output Voltage V V LCD255 Max. Source Voltage Variation -2-2 % VOH1 Logic High Output Voltage Iout=-100 A 0.9 * V DDIO - V DDIO V VOL1 Logic Low Output Voltage Iout=100 A * V DDIO V VIH1 Logic High Input voltage 0.8 * V DDIO - V DDIO V VIL1 Logic Low Input voltage * V DDIO V I OH Logic High Output Current Source Vout = V DDIO-0.4V µa I OL Logic Low Output Current Drain Vout = 0.4V µa I OZ Logic Output Tri-state Current Drain Source -1-1 µa I IL/I IH Logic Input Current -1-1 µa C IN Logic Pins Input Capacitance pf R SON Source drivers output resistance kω R GON Gate drivers output resistance Ω R CON VCOM output resistance Ω TC Temperature Coefficient % Note1 AV DDX2 efficiency = AV DD /(2 x V CI) x 100% Note2 V GH efficiency = V GH/(V CI x n) x 100% (where n = booster factor) Note3 AVDD VLCD V SSD2123 Rev 0.50 P 56/75 Mar 2008 Solomon Systech

58 14 AC CHARACTERISTICS 14.1 Display signal output timing 1 Frame Row 0 Row 1 Row 271 Row 0 Row 1 VSYNC HSYNC Polarity GR0 GG0 GB0 GR1 GG1 GB1... GRn GGn GBn Sm (All black pattern) t vbp t HSYN t Sm t vfp t VSYNC Figure 14-1 Gate and source output timing ( inversion) Symbol Parameter Min Typ Max Unit t VSYNC 1 / Frame Frequency ms t HSYNC 1 / Frequency us t Sm 1 / Source Frequency us t vbp Time for Vertical back porch in each frame Hsync t vfp Time for Vertical front porch in each frame Hsync 14.2 SSD2123 Rev 0.50 P 57/75 Mar 2008 Solomon Systech

59 Figure Example of color filter arrangement GR0 GG0 GB0 GR2 GG2 GB2 GR1 GG1 GB1 GR3 GG3 GB3 GR268 GG268 GB268 GR270 GG270 GB270 GR269 GG269 GB269 GR271 GG271 GB271 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S467 S468 S469 S470 S471 S472 S473 S474 S475 S476 S477 S478 S Display General Information AC Characteristics (Unless otherwise specified, Voltage Referenced to V SS, V DDIO = 3.3V, T A = -40 to 85 o C) 14.4 Display General Information VSYNC t vsys t vsyh 0.1V DDIO 0.1VDDIO t hsys t hsyh HSYNC 0.1VDDIO t hv t DOTCLK DOTCLK 0.9VDDIO 0.9VDDIO 0.9VDDIO 0.9VDDIO 0.1VDDIO 0.1VDDIO 0.1VDDIO t CKL t CKH t r t ds t dh Pixel Data DATA 0.1VDDIO 0.9VDDIO 0.1VDDIO 0.9VDDIO 0.1VDDIO DATA DATA t r / t f Figure Pixel Clock Timing Characteristics DOTCLK Frequency DOTCLK Period Target Target Target Symbol Min Typ Max 24 bits parallel f DOTCLK 8 bits serial bits parallel t 8 bits serial DOTCLK Units MHz nsec SSD2123 Rev 0.50 P 58/75 Mar 2008 Solomon Systech

60 Pixel Clock Period 24 bits parallel t 8 bits serial PIXCLK t DOTCLK Pixel Clock Freq. 24 bits parallel 8 bits serial f PIXCLK MHz Vertical Sync Setup Time t vsys nsec Vertical Sync Hold Time t vsyh nsec Horizontal Sync Setup Time t hsys nsec Horizontal Sync Hold Time t hsyh nsec Phase difference of Sync Signal Falling Edge t hv t DOTCLK DOTCLK Low Period t CKL nsec DOTCLK High Period t CKH nsec Data Setup Time t ds nsec Data hold Time t dh nsec Reset pulse width t RES usec Rise / Fall time t r / t f 5-25 nsec Note External clock source must be provided to DOTCLK pin of SSD2123Z. The driver will not operate if absent of the clocking signal. SSD2123 Rev 0.50 P 59/75 Mar 2008 Solomon Systech

61 CM HSYNC VSYNC Color Mode 16.7M color mode 8 color mode 16.7M color mode Figure 14-4 Color Mode Conversion Timing Note The color mode conversion starts at the first falling edge of VSYNC after stage change of CM. SSD2123 Rev 0.50 P 60/75 Mar 2008 Solomon Systech

62 V DDIO V DDEXT V CI RES SHUT >1ns >1us 10 us DOTCLK >1 CLK VGH < 10 frames < 10 frames < 10 frames V GH Output ~Vci Figure 14-5 VGH Output against SHUT & RESB Note1 Note2 The minimum cycle time of SHUT is frames. DOTCLK must be provided for boosting of V GH. The above timing diagram assumed voltages and DOTCLK are continuous supplied after power on. Note3 V GH will be forced to V CI at the low stage of RES. Note4 The minimum pulse width of RESET is 10us. SSD2123 Rev 0.50 P 61/75 Mar 2008 Solomon Systech

63 VCI VDDIO VDDEXT 0ms RESB >1ns SHUT tp-shut DOTCLK tclk- HSYNC VSYNC 1st 10th Display High Voltage tshut- tshut-on Display ON Figure Power Up Sequence Characteristics Symbol Target Target Target Min Typ Max Units V DDEXT / V DDIO on to falling edge of SHUT tp-shut µsec Start of DOTCLK to SHUT low tclk-shut DOTCLK Falling edge of SHUT to LCD power on tshut-lcd msec Falling edge of SHUT to display start frame -- 1 line 512 clk tshut-on -- 1 frame 278 line msec -- PIXCLK = 8.5MHz Note1 Note2 It is necessary to input DOTCLK before the falling edge of SHUT. Display starts at 10 th falling edge of VSTNC after the falling edge of SHUT. SSD2123 Rev 0.50 P 62/75 Mar 2008 Solomon Systech

64 V DD V DDIO V CI >1ns 0ms RES SHUT DOTCLK HSYNC VSYNC 1st 2nd Display High Voltage tofftshut-offt Display ON OFF Figure Power Down Sequence Characteristics Symbol Target Min Target Typ Target Max Units Rising edge of SHUT to display off frame -- 1 line 512 clk tshut-off -- 1 frame 278 line msec -- PIXCLK = 8.5 MHz Input-signal-off to V DDEXT / V DDIO off toff-vdd µsec Note1 Note2 Note3 DOTCLK must be maintained at lease 2 frames after the rising edge of SHUT. Display become off at the 2 nd falling edge of VSTNC after the falling edge of SHUT. If RESET signal is necessary for power down, provide it after the 2-frames-cycle of the SHUT period. SSD2123 Rev 0.50 P 63/75 Mar 2008 Solomon Systech

65 CS SCL tcss First Transmission (Register) tsl tsh tcsh SDI ID DC RW CS SCL Second Transmission (Data) tcsd SDI ID DC RW tds tdh Figure SPI Interface Timing Diagram & Transaction Example Characteristics Symbol Target Target Target Min Typ Max Units Serial Clock Frequency fclk MHz Serial Clock Cycle Time tclk nsec Clock Low Width tsl nsec Clock High Width tsh nsec Chip Select Setup Time tcss nsec Chip Select Hold Time tcsh nsec Chip Select High Delay Time tcsd nsec Data Setup Time tds nsec Data Hold Time tdh nsec Note1 SPID pin connected to VSS. SSD2123 Rev 0.50 P 64/75 Mar 2008 Solomon Systech

66 bit Serial Interface HV SYNC Mode YSYNC HSYNC DEN Mode t DEN DEN RR[70] n t V HV SYNC Mode HSYNC DOTCLK t HBP DEN Mode DEN Without Dummy RR[70] Invalid Data R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 Figure bit Serial Interface Timing Diagram & Transaction Example Characteristics HV SYNC Mode Symbol Without Dummy Units Serial Clock Frequency 1/t DOTCLK MHz One Period t H 1536 t DOTCLK Horizontal Active Data Period t data 1440 Horizontal Back Porch t HBP 48 t DOTCLK t DOTCLK Horizontal Front Porch t HFP 48 t DOTCLK One Field Period t V 278 t H Vertical Active period t AL 272 Vertical Back Porch t VBP 4 t H t H Vertical Front Porch t VFP 2 t H 14.6 SSD2123 Rev 0.50 P 65/75 Mar 2008 Solomon Systech

67 bit RGB Interface HV SYNC Mode YSYNC HSYNC DEN Mode t D5 50 DEN RR[70] n GG[70] n BB[70] n t V HV SYNC Mode HSYNC DOTCLK t HBP DEN Mode DEN RR[70] Invalid Data R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 GG[70] BB[70] Invalid Data Invalid Data G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G20 G21 G22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Figure bit Serial Interface Timing Diagram & Transaction Example Characteristics Symbol HV SYNC Mode Units Serial Clock Frequency 1/t DOTCLK 8.54 MHz One Period t H 512 t DOTCLK Horizontal Active Data Period t data 480 Horizontal Back Porch t HBP 16 t DOTCLK t DOTCLK Horizontal Front Porch t HFP 16 t DOTCLK One Field Period t V 278 t H Vertical Active period t AL 272 Vertical Back Porch t VBP 4 t H t H Vertical Front Porch t VFP 2 t H SSD2123 Rev 0.50 P 66/75 Mar 2008 Solomon Systech

68 15 ITO RESISTANCE REQUIREMENT Pin Suggested maximum resistance V COM, V CHS, AVDD, AVDDG, V CI, V CIM 10 ohm V SS, AV SS, V SSRC, CSSRC 10 ohm V CORE, V REGC, V DDIO, V CIP 20 ohm C11P, C11N, C12P, C12N, C13P, C13N, C1N, C1P, C2N, C2P, C3P, C3N, CXP, CXN, V GH, V GL, V LCD255, V COMH, V COML, VCOM 10 ohm TESTA, TESTB 100 ohm DOTCLK, RR[70], BB[70], GG[70], VSYNC, HSYNC 50 ohm X400, DENMODE, SRGB, GAMAS, SHUT, RL, TB, BGR, REV, SPID, RESB, CM, STYPE1, STYPE0, GPI0, GPI1, GPI2, GPI3, SDO, CSB, SCK, SCI, SDC, 100 ohm DEN Note ITO resistance and capacitance of DOTCLK, RR[70], BB[70], GG[70], VSYNC, HSYNC is suggested to be the same to prevent mismatch SSD2123 Rev 0.50 P 67/75 Mar 2008 Solomon Systech

69 16 SSD2123Z OUTPUT VOLTAGE RELATIONSHIP Figure LCD Driving Voltage Relationship VGH X3 AVDD VCI VLCD (AVDD 0.1V max) V COMH VSS V COM Amplitude V COML VCIM VGL Note The above voltages level assumed 100% efficiency of the internal booster. There has no voltage drop due to resistance from ITO trace of the panel. SSD2123 Rev 0.50 P 68/75 Mar 2008 Solomon Systech

70 17 INTERFACE MAPPING 17.1 Mapping for Writing an Instruction Hardware pins Interface Cycle BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0 24 bits IB23 IB22 IB21 IB20 IB19 IB18 IB17 IB16 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 1 st IB23 IB22 IB21 IB20 IB19 IB18 IB17 IB16 8 bits 2 nd IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 3 rd IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Remark Not connected pins 17.2 Mapping for Writing Pixel Data(s) Hardware pins Interface Color mode Cycle BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0 Parallel 16.7M B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 8 color B7 x x x x x x x G7 x x x x x x x R7 x x x x x x x 1 st R7 R6 R5 R4 R3 R2 R1 R0 Serial 16.7M 8 color 2 nd G7 G6 G5 G4 G3 G2 G1 G0 3 rd B7 B6 B5 B4 B3 B2 B1 B0 1 st R7 x x x x x x x 2 nd G7 x x x x x x x 3 rd B7 x x x x x x x Remark x Not connected pins Don't care SSD2123 Rev 0.50 P 69/75 Mar 2008 Solomon Systech

71 18 APPLICATION CIRCUIT Figure Application Diagram SSD2123 Rev 0.50 P 70/75 Mar 2008 Solomon Systech