Thiscontrolerdatasheetwasdownloadedfrom htp:/ a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K Color

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1 Crystalfontz Thiscontrolerdatasheetwasdownloadedfrom htp:/wwwcrystalfontzcom/controlers/ a-si TFT LC Single Chip river 240RGBx320 Resolution and 262K Color atasheet Version: V007 ocument No: _S_V007pdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 302, Taiwan, ROC Tel ; Fax

2 Section Table of Contents Introduction 7 2 Features 8 3 Block iagram 0 4 Pin escriptions 5 Pad Arrangement and Coordination 5 6 Block escription 24 7 System Interface 26 Page 2 of 27 V007 Page 7 Interface Specifications Input Interfaces i80/8-bit System Interface i80/6-bit System Interface i80/9-bit System Interface i80/8-bit System Interface Serial Peripheral Interface (SPI) bit 4 wires Serial Peripheral Interface wire 9-bit Serial Interface wire 8-bit Serial Interface VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface CABC (Content Adaptive Brightness Control) 54 8 Register escriptions 55 8 Registers Access Instruction escriptions Index (IR) I code (R00h) river Output Control (R0h) LC riving Wave Control (R02h) Entry Mode (R03h) bits ata Format Selection (R05h) isplay Control (R07h) isplay Control 2 (R08h) 68

3 829 isplay Control 3 (R09h) isplay Control 4 (R0Ah) RGB isplay Interface Control (R0Ch) Frame Marker Position (R0h) RGB isplay Interface Control 2 (R0Fh) Power Control (R0h) Power Control 2 (Rh) Power Control 3 (R2h) Power Control 4 (R3h) GRAM Horizontal/Vertical Address Set (R20h, R2h) Write ata to GRAM (R22h) Read ata from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R30h ~ R3h) Horizontal and Vertical RAM Address Position (R50h, R5h, R52h, R53h) Gate Scan Control (R60h, R6h, R6Ah) SPI Read/Write Control (R66h, Write Only) Partial Image isplay Position (R80h) Partial Image RAM Start/End Address (R8h, R82h) Partial Image 2 isplay Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control (R90h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RAh) OTP VCM Status and Enable (RA2h) OTP Programming I Key (RA5h) Write isplay Brightness Value (RBh) Read isplay Brightness Value (RB2h) Write CTRL isplay Value (RB3h) Read CTRL isplay Value (RB4h) Write Content Adaptive Brightness Control Value (RB5h) Read Content Adaptive Brightness Control Value (RB6h) Write CABC Minimum Brightness (RBEh) Read CABC Minimum Brightness (RBFh) CABC Control (RC7h) CABC Control (RC8h) 92 Page 3 of 27 V007

4 8248 CABC Control 2 (RC9h) CABC Control 3 (RCAh) CABC Control 4 (RCBh) CABC Control 5 (RCCh) CABC Control 6 (RCh) CABC Control 7 (RCEh) 98 9 OTP Programming Flow 99 0 GRAM Address Map & Read/Write 00 Window Address Function 05 2 Gamma Correction 06 3 Application 4 3 Configuration of Power Supply Circuit 4 32 isplay ON/OFF Sequence 6 33 Standby and Sleep Mode 7 34 Power Supply Configuration 8 35 Voltage Generation 9 36 Applied Voltage to the TFT panel Partial isplay Function 20 4 Electrical Characteristics 22 4 Absolute Maximum Ratings C Characteristics Reset Timing Characteristics AC Characteristics i80-system Interface Timing Characteristics Serial ata Transfer Interface Timing Characteristics RGB Interface Timing Characteristics 25 5 Revision History 27 Page 4 of 27 V007

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 27 FIGURE2 8-BIT SYSTEM INTERFACE ATA FORMAT 28 FIGURE3 6-BIT SYSTEM INTERFACE ATA FORMAT 29 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 30 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE 6 ATA FORMAT OF SPI INTERFACE 33 FIGURE7 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 34 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= AN FM= 0 ) 35 FIGURE9 ATA TRANSMISSION THROUGH VSYNC INTERFACE) 40 FIGURE0 MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 40 FIGURE OPERATION THROUGH VSYNC INTERFACE 4 FIGURE2 TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 43 FIGURE3 RGB INTERFACE ATA FORMAT 44 FIGURE4 GRAM ACCESS AREA BY RGB INTERFACE 45 FIGURE5 TIMING CHART OF SIGNALS IN 8-/6-BIT RGB INTERFACE MOE 46 FIGURE6 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 47 FIGURE7 EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 48 FIGURE8 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 5 FIGURE9 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 52 FIGURE20 RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 53 FIGURE2 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 55 FIGURE22 REGISTER SETTING WITH I80 SYSTEM INTERFACE 56 FIGURE 23 REGISTER REA/WRITE TIMING OF I80 SYSTEM INTERFACE 57 FIGURE24 GRAM ACCESS IRECTION SETTING 63 FIGURE25 6-BIT MPU SYSTEM INTERFACE ATA FORMAT 64 FIGURE26 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 65 FIGURE 27 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/6-/9-/8-BIT INTERFACE MOE 77 FIGURE 28 GRAM ATA REA BACK FLOW CHART 78 FIGURE 29 GRAM ACCESS RANGE CONFIGURATION 8 FIGURE30 GRAM REA/WRITE TIMING OF I80-SYSTEM INTERFACE 00 FIGURE3 I80-SYSTEM INTERFACE WITH 8-/6-/9-BIT ATA BUS (SS= 0, BGR= 0 ) 02 FIGURE32 I80-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS= 0, BGR= 0 ) 03 FIGURE 33 I80-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 04 FIGURE 34 GRAM ACCESS WINOW MAP 05 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 06 FIGURE 36 GRAYSCALE VOLTAGE AJUSTMENT 07 FIGURE 37 GAMMA CURVE AJUSTMENT 08 FIGURE 38 EXAMPLE OF RMP(N)0~5 EFINITION 0 Page 5 of 27 V007

6 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 3 FIGURE 40 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 3 FIGURE 4 POWER SUPPLY CIRCUIT BLOCK 4 FIGURE 42 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 6 FIGURE 43 STANY/SLEEP MOE REGISTER SETTING SEQUENCE 7 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE 8 FIGURE 45 VOLTAGE CONFIGURATION IAGRAM 9 FIGURE 46 VOLTAGE OUTPUT TO TFT LC PANEL 20 FIGURE 47 PARTIAL ISPLAY EXAMPLE 2 FIGURE 48 I80-SYSTEM BUS TIMING 24 FIGURE 49 SPI SYSTEM BUS TIMING 25 FIGURE50 RGB INTERFACE TIMING 26 Page 6 of 27 V007

7 Introduction a-si TFT LC Single Chip river is a 262,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 72,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit has five kinds of system interfaces which are i80-system MPU interface (8-/9-/6-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [7:0]), serial data transfer interface (SPI), RGB 6-/6-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [7:0]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern Page 7 of 27 V007

8 2 Features Single chip solution for a liquid crystal QVGA TFT LC display 240RGBx320-dot resolution capable with real 262,44 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 72,800 bytes graphic RAM CABC (Content Adaptive Brightness Control) System interfaces i80 system interface with 8-/ 9-/6-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/6-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [7:0]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,44 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 65V ~ 33 V (interface I/O) VCI = 25V ~ 33 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 60 VCL GN = -20V ~ -30V VCI VCL 60V Gate driver output voltage VGH - GN = 0V ~ 20V VGL GN = -5V ~ -5V Page 8 of 27 V007

9 VGH VGL 30V VCOM driver output voltage VCOMH = (VCI+02)V ~ (VH-02)V VCOML = (VCL+02)V ~ 0V VCOMH-VCOML 60V a-tft LC storage capacitor: Cst only Page 9 of 27 V007

10 3 Block iagram a-si TFT LC Single Chip river IOVCC IM[3:0] nreset Index Register (IR) ncs nwr/scl nr RS SI SO MPU I/F 8-bit 6-bit 9-bit 8-bit 8 7 Control Register (CR) Address Counter (AC) LC Source river S[720:] [7:0] HSYNC VSYNC OTCLK ENABLE TEST TEST2 TEST3 TS[8:0] SPI I/F RGB I/F 8-bit 6-bit 6-bit VSYNC I/F 8 8 Graphics Operation Read Latch 8 8 Write Latch 8 V63 ~ 0 Grayscale Reference Voltage VREGOUT VGS Graphics RAM (GRAM) UMMY20~27 VCC V GN LEPWM LEON Regulator RC-OSC Timing Controller Brightness control CABC Block LC Gate river G[320:] UMMY~5 VCI VCI GN Charge-pump Power Circuit VCOM Generator VCOM A C B C H V A 2 C B 2 C A 3 C B 3 C L C V A 2 C B 2 C A 2 C B 2 C H G V L G V H M O C V L M O C V Page 0 of 27 V007

11 4 Pin escriptions ncs RS Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3 IM2 IM IM0 MPU-Interface Mode Pin in use IM3, IM2, IM, IM0/I nwr/scl nr nreset SI / SA SO [7:0] I I I I I I I/O O I/O IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc Setting invalid Setting invalid i80-system 6-bit interface [7:0], [8:] 0 0 i80-system 8-bit interface [7:0] 0 0 I Serial Peripheral Interface (SPI) bit 3 wires Serial Peripheral Interface 0 8-bit 4 wires Serial Peripheral Interface Setting invalid 0 0 Setting invalid SI, SO SA, SCL, ncs 0 0 i80-system 8-bit interface [7:0] 0 i80-system 9-bit interface [7:9] * * Setting invalid SA, SCL, ncs, RS (/CX) When the serial peripheral interface is selected, IM0 pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to either IOVcc or GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to either IOVcc or GN level when not in use SPI Mode: Synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GN level when not in use A reset pin Initializes the ILI9325B with a low input Be sure to execute a power-on reset after supplying power SPI interface input pin The data is latched on the rising edge of the SCL signal In the 8/9-bit serial peripheral interface, this pin is used as bi-directional data pin SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as floating when not used An 8-bit parallel bi-directional data bus for MPU system interface mode Page of 27 V007

12 Pin Name I/O Type escriptions 8-bit I/F: [7:0] is used 9-bit I/F: [7:9] is used 6-bit I/F: [7:0] and [8:] is used 8-bit I/F: [7:0] is used 8-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [7:2] are used 6-bit RGB I/F: [7:3] and [:] are used 8-bit RGB I/F: [7:0] are used ENABLE I MPU IOVcc Unused pins must be fixed to GN level ata ENEABLE signal for RGB interface operation Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal OTCLK VSYNC HSYNC FMARK LEPWM/ TESTO LEON/ TESTO2 I I I O O O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc VCI VCI S720~S O LC G320~G O LC VCOM VCOMH O O TFT common electrode Stabilizing capacitor Stabilizing capacitor Fix to either IOVcc or GN level when not in use ot clock signal for RGB interface operation PL = 0 : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to the GN level when not in use Frame synchronizing signal for RGB interface operation VSPL = 0 : Active low VSPL = : Active high Fix to the GN level when not in use Line synchronizing signal for RGB interface operation HSPL = 0 : Active low HSPL = : Active high Fix to the GN level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use PWM signal output to control LE driver for LE brightness dimming This pin is connected to external LE driver It s a LE driver control pin which is used for turning ON/OFF of LE backlight LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS = 0, the data in the RAM address h00000 is output from S SS =, the data in the RAM address h00000 is output from S720 S, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = 0) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage VCOML O The low level of VCOM AC voltage Adjust the VCOML level with the VV bits VGS I GN or Reference level for the grayscale voltage generating circuit The Page 2 of 27 V007

13 Pin Name I/O Type escriptions external resistor VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit Vci I Power A supply voltage to the analog circuit Connect to an external supply power supply of 25 ~ 33V GN I Power GN for the analog side: GN = 0V In case of COG, connect to supply GN on the FPC to prevent noise Vci O An internal reference voltage for the step-up circuit The amplitude between Vci and GN is determined by the VC[2:0] bits Make sure to set the Vci voltage so that the VH, VGH and VGL voltages are set within the respective specification VH O Stabilizing capacitor Power supply for the source driver and Vcom drive VGH O Stabilizing capacitor Power supply for the gate driver VGL O Stabilizing capacitor Power supply for the gate driver VCL O Stabilizing VcomL driver power supply capacitor VCL = 05 ~ VCI Place a stabilizing capacitor between GN C+, C- I/O Step-up capacitor Capacitor connection pins for the step-up circuit C3+, C3- Step-up C2+, C2- I/O capacitor C22+, C22- Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREGOUT IOVcc I/O I Stabilizing capacitor Power supply V O Power GN UMMY3~ 5 UMMY20 ~ 27 I Power supply - - The voltage level is set with the VRH bits VREGOUT is () a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREGOUT = 30 ~ (VH 02)V Power Pads A supply voltage to the interface pins: IM[3:0], nreset, ncs, nwr, nr, RS, [7:0], VSYNC, HSYNC, OTCLK, ENABLE, SCL, SI, SO IOVcc = 65 ~ 33V and Vcc IOVcc In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise igital circuit power pad Connect these pins with the uf capacitor GN = 0V IOGNUM O GN GN pin Test Pads ummy pad Leave these pins as open TESTO~6 O Open Test pins Leave them open TEST, 2, 3 I IOGN Test pins (internal pull low) Connect to GN or leave these pins as open TS0~8 I OPEN Test pins (internal pull low) Leave them open TSO O OPEN Test output pin Let it open TEST_EN I OPEN Test pins Enable (internal pull low) Leave them open Page 3 of 27 V007

14 Liquid crystal power supply specifications Table No Item escription TFT Source river 720 pins (240 x RGB) 2 TFT Gate river 320 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) S ~ S720 V0 ~ V63 grayscales 4 Liquid Crystal rive Output G ~ G320 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVcc 65 ~ 330V VCI 250 ~ 330V VH 45V ~ 60V VGH 0V ~ 20V 6 Liquid Crystal rive Voltages VGL -5V ~ -5V VCL -9V ~ -30V VGH - VGL Max 30V VCI - VCL Max 60V VH VCI x2 7 Internal Step-up Circuits VGH VCI x4, x5, x6 VGL VCI x-3, x-4, x-5 VCL VCI x- Page 4 of 27 V007

15 5 Pad Arrangement and Coordination Page 5 of 27 V007

16 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y TEST_EN TS VCOML C C TEST TS VCOML C UMMY IOGNUM TS VCOML C UMMY LEPWM / TESTO TS VCOML C UMMY LEON / TESTO TS VREGOUT VGL G TESTO TSO VREGOUT VGL G IM0/I IOVCC VREGOUT VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G TEST IOVCC VCL VGL G TESTO IOVCC VCL VGL G TESTO V VCL VGL G TESTO V VCL VGL G TESTO V VCL GN G TESTO V VH GN G TESTO V VH GN G TESTO V VH VGH G nreset V VH VGH G nreset V VH VGH G VSYNC V VH VGH G HSYNC V VCI VGH G OTCLK V VCI VGH G ENABLE UMMY VCI UMMY G GN VCI UMMY G GN VCI C G GN VCI C G GN VCI C G GN VCI C G TESTO GN VCI C G GN VCI C G GN VCI C G VGS VCI C G VGS VCI C G GN VCI C G TEST GN VCI C G TESTO GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN UMMY C G GN UMMY C G UMMY C C G TESTO UMMY C C G SO UMMY C C G SI VCOM C C G nr VCOM C C G nwr/scl VCOM C C G RS VCOM C C G ncs VCOM C C G TESTO VCOM C C G TESTO VCOM C C G FMARK VCOMH C C G TESTO VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G Page 6 of 27 V007

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 30 G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G UMMY S S S G UMMY S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S Page 7 of 27 V007

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 60 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S UMMY S S S S UMMY S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 8 of 27 V007

19 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 90 S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S UMMY G S S S UMMY G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G Page 9 of 27 V007

20 No Name X Y No Name X Y 20 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G UMMY G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 20 of 27 V007

21 Page 2 of 27 V007

22 S ~ S720 G ~ G320 UMMY20~27 9 (No 244 ~ 29) 9 8 Unit: um 50 x 50 I/O Pads (No ~ 243) p m u P d a P p m u P d a P 0 8 y X=20, 30, 35 Unit: um Y=70, 80, 85 Page 22 of 27 V007

23 Alignment mark Alignment mark X Y Page 23 of 27 V007

24 6 Block escription MPU System Interface supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 6-, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:0] pins has a 6-bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (RR) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The RR is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the RR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/6-/8-bit bus width) I80 Function RS nwr nr Write an index to IR register 0 0 Write to control registers or the internal GRAM by R register 0 Read from the internal GRAM by RR register 0 Registers selection by the SPI system interface Function R/W RS Write an index to IR register 0 0 Write to control registers or the internal GRAM by R register 0 Read from the internal GRAM by RR register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (7-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 24 of 27 V007

25 Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 72,800 (240 x 320x 8/8) bytes with 8 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,44 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LC river Circuit The LC driver circuit of consists of a 720-output source driver (S ~ S720) and a 320-output gate driver (G~G320) isplay pattern data are latched when the 720 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for Page 25 of 27 V007

26 driving an LC 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [7:0] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode RAM Access Setting (RM) isplay Operation Mode (M[:0]) Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) System interface (RM = 0) RGB interface (RM = ) System interface (RM = 0) System interface (RM = 0) Internal operating clock (M[:0] = 00) RGB interface (M[:0] = 0) RGB interface (M[:0] = 0) VSYNC interface (M[:0] = 0) Note ) Registers are set only via the system interface Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 26 of 27 V007

27 Figure System Interface and RGB Interface connection 72 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:0] pins The system interface is used for setting registers and GRAM access IM3 IM2 IM IM0/I Interface Mode Pin Setting invalid Setting invalid i80-system 6-bit interface [7:0], [8:] 0 0 i80-system 8-bit interface [7:0] 0 0 I Serial Peripheral Interface (SPI) SI, SO ([:0]) bit 3 wires Serial Peripheral Interface SA, SCL, ncs 0 8-bit 4 wires Serial Peripheral Interface SA, SCL, ncs, RS (/CX) Setting invalid 0 0 Setting invalid 0 0 i80-system8-bit interface [7:0] 0 i80-system 9-bit interface [7:9] * * Setting invalid Page 27 of 27 V007

28 72 i80/8-bit System Interface The i80/8-bit system interface is selected by setting the IM[3:0] as 00 levels Figure2 8-bit System Interface ata Format Page 28 of 27 V007

29 722 i80/6-bit System Interface The i80/6-bit system interface is selected by setting the IM[3:0] as 000 levels The 262K or 65K color can be display through the 6-bit MPU interface When the 262K color is displayed, two transfers ( st transfer: 2 bits, 2 nd transfer: 6 bits or st transfer: 6 bits, 2 nd transfer: 2 bits) are necessary for the 6-bit CPU interface TRI FM 6-bit MP U S ys te m Inte rfa ce a ta Forma t system 6-bit interface ( transfers/pixel) 65,536 colors 0 * s t Tra ns fe r R 5 R 4 R3 R 2 R R 0 G5 G4 G3 G 2 G G 0 B5 B4 B3 B2 B B0 80-system 6-bit interface (2 transfers/pixel) 262,44 colors st Transfer nd Tra ns fe r 7 6 R 5 R 4 R3 R 2 R R 0 G5 G4 G3 G 2 G G 0 B5 B4 B3 B2 B B0 80-system 6-bit interface (2 transfers/pixel) 262,44 colors st Transfer nd Tra ns fe r R 5 R 4 R3 R 2 R R 0 G5 G4 G3 G 2 G G 0 B5 B4 B3 B2 B B0 Figure3 6-bit System Interface ata Format Page 29 of 27 V007

30 723 i80/9-bit System Interface The i80/9-bit system interface is selected by setting the IM[3:0] as 0 and the 7~9 pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:0] pins must be tied to GN Figure4 9-bit System Interface ata Format 724 i80/8-bit System Interface The i80/8-bit system interface is selected by setting the IM[3:0] as 00 and the 7~0 pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:0] pins must be tied to GN Page 30 of 27 V007

31 TRI FM 8-bit MP U S ys te m Inte rfa ce a ta Forma t system 8-bit interface (2 transfers/pixel) 65,536 colors 0 * st Transfer nd Transfe r R5 R 4 R 3 R 2 R R 0 G5 G 4 G 3 G 2 G G 0 B5 B4 B3 B2 B B0 80-system 8-bit interface (3 transfers/pixel) 262,44 colors 0 st Transfer nd Tra nsfer rd Tra nsfer R5 R 4 R 3 R 2 R R 0 G5 G 4 G 3 G 2 G G 0 B5 B4 B3 B2 B B0 80-system 8-bit interface (3 transfers/pixel) 262,44 colors 7 6 s t Tra ns fe r nd Tra ns fe r rd Tra ns fe r R5 R 4 R 3 R 2 R R 0 G5 G 4 G 3 G 2 G G 0 B5 B4 B3 B2 B B0 Figure5 8-bit System Interface ata Format Page 3 of 27 V007

32 73 Serial Peripheral Interface (SPI) bit 4 wires Serial Peripheral Interface The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as 00x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification code The [7:0] pins, which are not used, must be tied to GN The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS = 0, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is 0 and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are 6-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 6-bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W 0 0 I /0 /0 Note: I bit is selected by setting the IM0/I pin RS and R/W Bit Function RS R/W Function 0 0 Set an index register 0 Read a status 0 Write a register or GRAM data Read a register or GRAM data Page 32 of 27 V007