SIMULATION OF 2.4 GHz LOW-POWER CMOS LC QUADRATURE VOLTAGE CONTROLLED OSCILLATOR

Transcription

1 IJSS : 6(), 0, pp SIMULTION OF.4 GHz LOW-POWER CMOS LC QUDRTURE VOLTGE CONTROLLED OSCILLTOR Srja B.S and Radha S. Sathyabama Univrsity, srjaabs@gmail.cm Dpartmnt f ECE, SSN Cllg f Enginring, radhas@ssn.du.in bstract: This papr prsnts th simulatin analysis f a.4 GHz Quadratur Vltag Cntrlld Oscillatr (QVCO), fr lw-pwr, lw-vltag applicatins. Crss cupld LC VCO (Inductr-Capacitr Vltag Cntrlld Oscillatr) tplgy is utilizd t raliz QVCO. With th passiv cupling achivd frm th MOS transistrs, pwr cnsumptin is minimizd whil maintaining a small chip ara. Th variabl capacitrs and th inductrs ar dsignd using NSYS and imprtd thrugh DC cmpnnts in DS (dvancd Dsign sftwar). ccurat simulatin f th QVCO is prfrmd in th sftwar nvirnmnts and th rsults ar prvidd. This QVCO prvids quadratur signals at.4 GHz, achivs a pak t pak vltag f 0.65 vlts with a simulatd lw pwr cnsumptin f 5.8 m frm a pwr supply vltag f 0.6 vlts. Th simulatd QVCO prducs frquncy tuning frm. GHz t.60 GHz (0.83%) with a cntrl vltag varying frm vlts. Th utput pwr lvl f th QVCO is -7 dbm, with an imprvd prdictd quality factr f 60 and a phas nis f -34 dbc/hz, MHz far frm th carrir frquncy. Kywrds: Variabl capacitr, utput vltag swing, lw pwr cnsumptin, ultra lw supply vltag, Quadratur Vltag Cntrlld Oscillatr, passiv cupling. INTRODUCTION Th fast grwing markt in wirlss cmmunicatins has ld t th nd fr lw-pwr, lw-nis vltag cntrlld scillatrs. Espcially fr mbil wirlss cmmunicatins, lw pwr pratins ar f vry imprtanc as th battry liftim dpnds n th pwr cnsumptin. Quadratur signals can b gnratd by fding th diffrntial utputs f th VCO t a ply phas filtr [,], ltting th VCO wrk at dubl th dsird frquncy and pass thrugh frquncy divisin [3,4], and cupling idntical LC VCO circuits [5,6] t ach thr. Th ply phas filtr apprach intrducs substantial pwr cnsumptin du t th attnuatin by th rsistanc and th capacitanc in th circuit. Th frquncy dividing apprach avids th pushing/ pulling ffct n th VCO, hwvr, th xistnc f frquncy dividr and high frquncy VCO rsult in incrasd pwr cnsumptin. mr attractiv apprach t dirct quadratur synthsis rlis n th pssibility f ffctiv cupling f tw idntical LC VCO circuits. Th first cupling apprach is th bst knwn paralll cupling [7], whr cupling btwn th tw VCOs is nfrcd by transistrs. Whil this cupling dlivrs lw pwr, lw amplitud and phas rrrs, it prducs high phas nis. Intrducing a phas shiftr as rprtd in [8] ffrs bttr phas nis prfrmanc, hwvr it incrass th pwr cnsumptin. Svral thr cupling tchniqus hav bn rprtd lik back gat cupling [9], supr-harmnic cupling [0], and transfrmr cupling []. In additin t this currnt rusd QVCOs ar als prpsd []. Hwvr ths apprachs hav thir wn mrits and dmrits, th urg f lw pwr dsign f QVCO whil maintaining lw phas and amplitud rrrs still xists. In this wrk an attmpt is mad t mak us f th VCO, rprtd [3,4], t dsign a lw pwr QVCO.. PROPOSED QVCO TOPOLOGY Th QVCO is dsignd t scillat at.4 GHz, and t dtrmin th impact n th prfrmanc paramtrs. Figur 3(a) shws th LC VCO mplyd in this wrk. LC VCO prvids utstanding phas nis and jittr prfrmanc at high frquncis cmpard t thr tplgis. Crss cupld pair LC VCO tplgy is slctd fr this dsign du t its high utput vltag swing, balancd diffrntial utput and symmtrical structur. Frm th wll knwn thry f scillatrs, th psitiv fdback transistrs M 3 and M 4 ar usd t achiv ngativ input rsistanc, with which psitiv rsistanc f LC rsnant circuit might b

2 3 Srja B.S. and Radha S. liminatd bringing n zr-dampn scillating prprty. PMOS transistrs M and M ar usd t gnrat th rquird bias currnt. Hwvr, this tplgy prvids th abv mrits, it cntains an inductr and a varactr in its tank circuit which ar larg ara cmpnnts. In rdr t rduc th di ara f th rsnant circuit, MWCNT basd puls inductr is intgratd with Micr scal varactr. In rdr t rduc th rquird supply vltag and t liminat additinal nis cntributin, th tail currnt transistrs in a cnvntinal crss-cupld VCO can b rplacd by n-chip inductrs [5]. (a) th VCO is nhancd, lading t a suprir cls-in phas nis. Sinc th fdback capacitrs ar mplyd in th surc trminals f th crss-cupld transistrs, a mr ffctiv cntrlld mchanism f th tank rsnanc is prsntd. Thrfr, a rasnabl frquncy tuning rang can b achivd vn with a rducd vltag rang fr th cntrlld signal. Th variabl capacitrs C, C B and C C rprsnt th Micr scal varactr and C B is mdlld as tw sris capacitancs, t maintain th symmtry f th circuit. L and L ar mdlld as n-chip inductrs. Figur 3(b) shws th circuit diagram f th quadratur LC VCO. Tw idntical LC VCO circuits tgthr with th cupling structur as shwn in Figur, ar utilizd t gnrat quadratur phas sinusidal signals. Th transistrs ar biasd at zr dc currnt and prat as passiv lmnts. Nt that th cupling transistr is rplacd by paralll RC ntwrk in Figur. Th dsign paramtrs f th simulatd VCO ar listd in Tabl. (b) Figur : Shmatic f th Cupling Structur f QVCO (b) Equivalnt Circuit Mdl f th Cupling Structur (a) Figur : Simplifid Half Circuit Mdl f th Prpsd VCO In this wrk th tail currnt transistrs ar rplacd with MWCNT bundl basd inductr. Fr an nhancd vltag swing undr an ultra-lw supply vltag, th capacitiv-fdback tchniqu can b mplyd [6]. Th capacitiv fdback lp is stablishd by C and C. Du t th us f th n-chip inductr and th capacitiv fdback lp, th drain and surc vltags can swing abv th supply vltag and blw th grund ptntial. Cnsquntly, th utput swing f Figur 3: (b) (a) Shmatic f th prpsd LC CMOS VCO Shwing th Rplacmnt f Tail Currnt Transistrs and th Fdback Gat Capacitanc (b) QVCO Structur

3 Simulatin f.4 GHz Lw-Pwr CMOS LC Quadratur Vltag Cntrlld Oscillatr 33 Paramtr Using laplac transfrm analysis th apprximatd transfr functin (singl ndd utput t input) can b drivd as, V0 ( s) g ( g s b s b ) V ( s) a s a s a s a s a i m whr th cfficints f th numratr and dnminatr ar as fllws: a C C // C R // C b b b 0 B L L R R C L L R L R R L L R R C C C 0 a L L C ( R C R C R C ) a R R C ( L C L C L C ) a C ( L R L R g L R R ) 3 m a C R R 4 (9) (0) () Th circuit scillats if quatin (9) is qual t, and at th scillatin frquncy, g ( b jb b ) a ja 4 3 m 0 0 a ja a 3 4 () With prpr assumptins and simplificatins th scillatin frquncy can b apprximatd as g m Tabl Dsign Paramtrs C ( C C ) L C Dsign Valus MOS Transistrs M m/0.6nm N = 50 M m/0.6um N = 50 6 m/0.6nm N = 30 M 6 m/0.6nm N = 30 M Cupling Transistr 40 µm/ 0.0um L P 0.6 nh Micr Scal varactr 9 pf C 0 µf I bias.8 m R P 50 g m 6.67 ms + (safty factr.5) L C C B a C ( L R R L ) RR ( L L ) b (3) (4) ssuming L = L = L P and R = R = R P quatin (3) and (4) can b simplifid as, g m C( C C ) L C C C P 4( C / C ) R C L ( C / C ) P p (5) Frm quatin (3) it is sn that th scillatin frquncy has tw parts, in its thrtical drivatin. s cnvntinal LC Vltag Cntrlld Oscillatrs, L C cntributs th majr part f th scillatin frquncy and th scnd part C( C C ) C C furthr nhancs th scillatin frquncy. Hwvr, th fixd capacitanc C dgrads th scillatin frquncy cmpard t [8], culd b still imprvd by th numratr part (C + C ). Frm quatin (5) it is nticd that th fixd capacitanc C incrass (sinc < ) th trans-cnductanc which hlps us t initiat succssful scillatins. Thrfr, a dsign trad ff is stablishd btwn th tuning rang and th transcnductanc basd n C. Mrvr, g m shuld b maintaind t a valu with which scillatins can ccur. Hwvr a rasnabl tuning rang can b btaind using th fur plat Micr scal varactr. It can b cncludd that by slcting suitabl and ptimal valus fr th capacitrs bttr thrtical prfrmanc can b sn frm th dsignd scillatr.. LYOUT DESIGN Layut f th prpsd QVCO is dsignd using a 90nm CMOS prcss in Micrwind nvirnmnt. Th CMOS sctin f th QVCO structur is symmtrical. Th activ layut ara f th QVCO is 70um 760um, including th bnding pads. Th distanc btwn th cmpnnts is minimizd in rdr t rduc th phas nis, and th layut is mad as symmtrical and cmpact as pssibl t nsur diffrntial pratin and rduc parasitic inductanc r capacitanc. 3. SIMULTION RESULTS ND DISCUSSION Th tim rfrncd scillatin shwn in Figur 4 is gnratd in DS nvirnmnt using th QVCO tplgy. Th scillatin frquncy is masurd as.40 GHz, with th variabl capacitr tuning vltag v (actuatin vltag f th capacitr) at 0.07 vlts, and v (actuatin vltag f th capacitr) at 0.9 vlts. ll simulatins ar prfrmd with 0.6 vlts pwr supply vltag and a currnt cnsumptin f 5.8 m in th cr circuit.

4 34 Srja B.S. and Radha S. (a) Figur 4: Output Oscillatins f QVCO Circuit Simulatd Using DS Th simulatin rsults f phas nis using HB mthd with DS is shwn in Figur 5. Sinc th prpsd QVCO is pratd undr ultra lw dc vltag, th crss cupld transistrs ar ptntially biasd in th wak invrsin rgin. Th phas nis is simulatd as -34 dbc/hz at an ffst frquncy f MHz frm th carrir frquncy. It is ntd that, fr lw pwr pratins th crss cupld transistrs may cntribut mr nis t th LC tank as th supply vltag dcrass. Hnc, it impss a fundamntal limiatin n th phas nis f th QVCO fr ultra lw pwr and lw vltag applicatin. (b) Figur 6: (a) Simulatd Frquncy Zm Viw (b) Output Oscillatins f QVCO Layut Simulatd Using Micrwind- Cntrl Vltag V Varis frm 0 Vlts t 0.9 Vlts and V is Kpt at 0.9 Vlts Figur 5: DS Simulatd Phas Nis as Functins f Offst and Nis Frquncy Th tstd circuit is tranfrrd t th layut fr furthr simulatin. Layut shwn in Figur 4 is simulatd, and th simulatin rsults ar shwn frm Figur 6 t Figur 8. Figur 6 shws th simulatin rsults whn v is varid frm v and v is kpt at 0.9 v. Whn th cntrl vltag is incrasd abv V dd / (0.3 v) th dvic stps scillating, and a dc vltag f 0.6 vlts is prducd as utput vltag. Thus th maximum lvl f th cntrl vltag is V dd /. Figur 7 and Figur 8 shws th currnt wavfrms f PMOS and NMOS transistrs rspctivly. Th transistrs ar sizd t achiv th dsign spcificatins. Th pwr cnsumptin f th dvic with a supply vltag f 0.6 vlts is apprximatly 5.8 mw. Th dvic is simulatd with a pwr supply vltag f. vlts and th currnt cnsumptin is fund t b.9 m. ls during th simulatins it was ntd that th phas nis has an invrs rlatin with th supply vltag. Th phas nis may b imprvd at highr supply vltags. Figur 7: Output Vltag and Currnt Wavfrm (PMOS) f QVCO Layut Simulatd Using Micrwind- Cntrl Vltag Varis frm 0 Vlts t 0.3 Vlts Tabl shws th prfrmanc charactristics and th dsign variabls f th QVCO. s in th tabl, th dsignd QVCO xibits a tuning frquncy rang f 500 MHz, with.4 GHz as cntr frquncy which lads a tuning prcntag f Bcaus f th trad-ff btwn th phas nis and th tuning frquncy rang, that th phas nis f th scillatr is invrsly prprtinal t th tuning frquncy rang, th tuning frquncy rang is limitd. Th tank circuit impdanc xhibits an invrsly prprtinal rlatinship with th scillatin frquncy.

5 Simulatin f.4 GHz Lw-Pwr CMOS LC Quadratur Vltag Cntrlld Oscillatr 35 Paramtrs Tabl Simulatd Rsults f QVCO Tuning Rang 0.83% Quality factr (QVCO) Cntr Frquncy Phas Nis Pwr Cnsumptin Simulatd Rsuts 60 (@.4 GHz, V QCONTROL = 0.56 vlts).40 GHz 34 MHz 5.8 mw Output Pwr 8 dbm ( at 50 lad) Chip Siz 70 µm 760 µm Supply Vltag 0.6 vlts Tuning Band width 500 MHz (. GHz.6 GHz) Tank- Inductanc Tank-Capacitanc Tuning Vltag Rang Quality factr(rsnant Ciruit) nh 0.3 pf vlts Whn th tank circuit impdanc is lwrd, th start-up gain gain is rducd as wll as utput vltag swing. Hnc th valu f th tank circuit impdanc is carfully chsn t avid ths issus. Th quality factr f th rsnant circuit at.4 GHz is calculatd as 69, which prvids a quality factr f 63 fr th QVCO at th sam frquncy. With th additinal circuitry includd, th quality factr f th QVCO has bn prdictd as 60 at.4 GHz. Th gat-surc and th drain surc capacitanc f th PMOS and NMOS transistrs ar masurd btwn 0 t 3.5 ff. Figur 8: Output Vltag and Currnt Wavfrms (NMOS) f QVCO Layut Simulatd Using Micrwind- Cntrl Varis frm 0 Vlts t 0.9 Vlts 4. CONCLUSION.4 GHz QVCO is simulatd and th rsults f th simulatin ar analysd. Th rsults indicat QVCO pratin at a cntr frquncy f.4 GHz with a quality factr f 60. Th chip siz is 70 µm 760 µm. Th simulatin prdicts phas nis f 34 dbc/hz at a pwr supply vltag f 0.6 V. Th simulatd scillatin amplitud is maintaind slightly abv Vdd using th fdback capacitrs. Th simulatin pratinal cnditins indicat that th dvic cnsums ultra lw pwr at 5.8 mw, including th buffr. Furthr th fabricatin f th QVCO is xpctd. REFERENCES [] M.S.J. Styart, J. Janssns, B. D Mur, M. Brrmans, and N. Ith, -V CMOS Cllular Transcivr Frnt-nd, IEEE J. Slid-Stat Circuits, 35(), pp , Dc [] F. Bhbahani, Y. Kishigami, J. Lt, and.. bidi, CMOS Mixrs and Plyphas Filtrs fr Larg Imag Rjctin, IEEE J. Slid-Stat Circuits, 36(6), pp , Jun. 00. [3] Ravi, K. Sumyanath, L.R. Carly, and R. Bishp, n Intgratd 0/5 GHz Injctin-lckd Quadratur LC VCO in a 0.8 µm Digital CMOS Prcss, in Prc. IEEE Eur. Slid-Stat Circuits Cnf., Sp. 00, pp [4] J.P. Maligrgs and J.R. Lng, Lw-vltag GHz Imagrjct Rcivr with Wid Dynamic Rang, IEEE J. Slid-Stat Circuits, 35, pp , Dc [5] D. Ham and. Hajimiri, Cncpts and Mthds in Optimizatin f Intgratd LC VCOs, IEEE J. Slid-Stat Circuits, 36, pp , Jun 00. [6] M. Tibut, Lw-pwr Lw-phas-nis Diffrntially Tund Quadratur VCO Dsign in Standard CMOS, IEEE J. Slid-Stat Circuits, 36, pp , July 00. [7]. Rfugaran, J. Ral, M. Rfugaran, and. bidi, 900 MHz CMOS LC-scillatr with Quadratur Outputs, in Prc. ISSCC 996, Fb. 996, pp [8] P. van d Vn, J. van dr Tang, D. Kasprkvitz, and. van Rrmund, n Optimally Cupld 5 GHz Quadratur LC Oscillatr, in Prc. 00 Symp. VLSI Circuits, Jun 00, pp [9] H.R. Kim, C.Y. Cha, S.M. Oh, M.S. Yang, and S.G. L, Vry Lw-pwr Quadratur VCO with Back-gat Cupling, IEEE J. Slid-Stat Circuits, 39(6), pp , Jun [0] S.L.J. Girkink, S. Lvantin, R.C. Fry, C. Samri, and V. Bccuzzi, Lw-phas-nis 5-GHz CMOS Quadratur VCO Using Suprharmnic Cupling, IEEE J. Slid-Stat Circuits, 38(7), pp , Jul []. Ravi, K. Sumyanath, R.E. Bishp, B.. Blchl, and L.R. Carly, n Optimally Transfrmr Cupld, 5 GHz Quadratur VCO in a 0.8 µm

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