GENERATING GAUSSIAN FUNCTIONS USING LOW- VOLTAGE MOS-TRANSLINEAR CIRCUITS

Transcription

1 ENERATN AUSSAN FUNCTONS USN O- OTAE MOS-TRANSNEAR CRCUTS SANCHEZ-OPEZ CAROS 1, AZ-SANCHEZ AEJANRO, TEO-CUAUTE ESTEBAN Elctronics partmnt NAOE uis Enriqu Erro no. 1. P.O.Box 51 and MEXCO Abstract: - Th dsign of a gaussian function (F) implmntd in a CMOS standard tchnology, is prsntd. Th proposd dsign is basd on th Translinar Principl (TP) using MOS transistors (MOSTs) biasd in wak-invrsion. Simulation rsults using HSPCE for a.6um tchnology of AMS, dmonstrat th suitability and appropriatnss of th proposd dsign to b usd in lowvoltag and low-powr applications,.g. in wavlts procssing. Ky-ords: - Analog sign, MOS Translinar Circuits, ow-oltag, avlts. 1 ntroduction Th dmand of portabl systms hav bn mad possibl th dvlopmnt of nw dsignmthodologis for low-voltag applications [1]- [3], using th TP [4]-[8]. Th main advantag of Translinar Circuits (TCs), is that thy inhrntly prsnt a vry-low snsitivity to tmpratur variations. MOS-TCs hav svral advantags with rspct to BJT-TCs, namly: thy do not prsnt finit currnt-gain, thy prsnt low saturation-voltags, which is quit convnint for low-voltag applications, and thy hav an xtra-dpndnc on th draincurrnt [6]. Bsids, th body-ffct (BE) rprsnts a srious limitation, it can b rducd by conncting th Bulk and Sourc togthr using a tchnology of two-wlls []. n this mannr, th dsign of a MOS-circuit for gnrating Fs, basd on th TP, is prsntd. Th mathmatical rprsntation of a F, is givn in sction. Svral implmntations ar listd in sction 3. A tchniqu for offst and BE compnsation, is introducd in sction 4. Th proposd dsign and its simulation rsults using HSPCE, ar givn in sction 5. Finally, th conclusions ar listd in sction 6. Mathmatical Rprsntation Th bhavior of a F [7]-[8] is givn by: 1 1 t τ S hs, τ ( t) = S (1) S rprsnts a scal-factor, τ rprsnts th translation in tim. Equation (1) rprsnts th bhavior of a normalizd F which associats th optimum tim-bandwidth product. 3 Translinar Circuits Thr xist a plthora of circuits basd on th TP using BJTs [4]. That circuits can b ralizd using a CMOS standard tchnology biasing th MOSTs in wak-invrsion. n this mannr, th drain currnt of an NMOS is []-[3] = O ( n 1 ) nt S TH 1 S t S + () th is th bulk-sourc voltag (BE), TH thrshold voltag, t th thrmal voltag, th Early voltag, and n th slop factor, usually lss than, and 1 for larg valus of. is a currnt associatd to th transconductanc paramtr K by [3]: K ( nt) (3) Minimizing th BE, quation () is rducd to: S TH O (4) 3.1 Circuit of Quadratur A MOS-basd quadratur-circuit, ralizd by M1-M5, is shown in Fig. 1. Equation (4) is usd to minimiz th BE, but satisfying (5). y + α > (5) Using th TP it can b dmonstratd that d1 * d o = (6) α By applying KC through M1-M on gt y d 1 = α + y d = α (7) 1 Sánchz-ópz holds a scholarship from CONACyT.

2 Sinc y = ( x u), quation (6) rsults in ( x u) r = (8) 4α M6-M7 mirror r to M7, thy form a basic Translinar oop [4]. r is usd to dvlop th xponntial ralization of quation (1). and u control th pak-gain and man-valu or translation-paramtr. α controls th scal or standard dviation. Figur. F using a floating rsistor. Figur 1. A currnt-mod quadratur-circuit. 3. Circuits for Ralizing Fs Svral topologis basd in BJTs has bn prsntd in [4]. That topologis can b rplacd by MOSTs, as shown in Fig.. As on ss, r flows through th rsistor whr: g = Rg * r (9) Thn, x is: x = S1 Rgr (1) S1 = TH1 + nt * n (11) OM1 M 1 M convrts x into a currnt xprssd by M TH 1 TH Rgr M = (1) M1 M 1 f M1=M, quation (1) is rducd to Rgr nt = (13) Using (8) in (13) it rsults in ( ) Rg x u 4nt α = (14) An implmntation using a groundd rsistor, is shown in Figur 3. r flows trough R, M convrts this voltag into a currnt givn by (13). Using (8), on gt (14) again. Equation (14) is modling a gaussian-window with paramtrs controlld by currnt sourcs. Figur 3. F using a groundd rsistor. 3.3 Activ Rsistors. Using th TP, on may dsign activ rsistors, as shown in Figur 4. Th input-signal is xtndd through th diffrntial-pairs, rducing th unbalancd voltag. Th input rsistanc is: 4nt Rin = (15) Figur 4. Activ Rsistor with high linarity. Using (15) in (14), on gt th currnt of th F. f B is proportional to th scal control-currnt B

3 α B = 4, on gt: *( x u ) α = (16) 3.4 Enrgy Normalization To prsrv th nrgy of th gaussian-window, th output-currnt is adjustd by varying th scal factor statd in quation (1); thn must 1 1 = b proportional to α S. An fficint schm for low-voltag applications is shown in Figur 5 [4]. Th rsulting F normalizd in currnt-mod is rprsntd by 3 1 *( x u ) α = (17) α nonlinarity in th output-currnt. Th drain currnt of th MOSTs that do not suffr th BE ar modld using quation (4), th ons prsnting th BE ar modld by S TH = O A (18) ( n 1) A = nt incrmnts th drain currnt du to th BE, tnding to 1 whn. Anothr circuit minimizing th offst is shown in Figur 7. From th offst prsntd at th output currnt, th voltag at nod x is varying whn y taks valus according to (5). MA stabilizs nod x as y bcoms varying. Figur 5. nrating at low-voltag. 4 Body Effct Th circuit shown in Figur 1, prsnts highr dviation du to th BE. An improvd dsign is shown in Figur 6. Th offst gnratd by th BE is rducd by adding a currnt-controlld currnt-sourc in th gat of M5. Sinc y varis according to (5) th currnt in M4 also varis, and th offst is rducd. Figur 6. Offst compnsation du to th BE. M is changd by a PMOST but kping th TP, bcaus th NMOST producs a Figur 7. Modification of th quadratur circuit 5 AUSSAN FUNCTON Th proposd dsign of th circuit gnrating Fs, implmntd in a standard CMOS tchnology, was ralizd using a tchnology of a singl-wll for.6um of AMS. 5.1 mplmntation n Figur 8 it is shown th circuit gnrator of th F, whil in Tabl 1 ar shown th rangs of th input currnt. Th proposd circuit is composd of thr basic blocks, namly: Th circuit of quadratur, Th activ rsistor, and Th circuit gnrator of th Fs. 1.5 Powr Consumption.843u 1n-6n α 4n-8n y (-8n)-(+8n) Tabl 1. Biasing conditions for th circuit gnrator of a F. n Figur 9 is shown th circuit gnrator of th F bing normalizd, whil in Tabl ar shown th rangs of th control-currnts. This

4 circuit is composd of four blocks: Th thr blocks listd abov plus a gnrator for. 1.5 Powr consumption µ α 4n -- 16n y -16n -- 16n 1 4n Tabl. Biasing conditions for th circuit gnrator of th normalizd F. 5. Simulation Rsults n Figur 1 ar shown th simulation rsults of th circuits shown in Figurs 6 and 7. As on ss from Figur 1.b, whil th proposd configuration dos not rduc compltly th offst, it is controlld within an accptabl rang. Th simulation rsult of th F bing normalizd, is shown in th Figur 11. Finally, th rsult by making a translation by varying u is shown in Figur 1. Th rangs of th control currnts ar listd in Tabls 1 and. x and u must b kpt within th rang imposd by y. 6 CONCUSONS. Along th papr it was discussd th dsign of a low-voltag circuit suitabl for th ralization of Fs by applying th TP, using MOSTs biasd in wak-invrsion. Th proposd dsign was ralizd using a standard CMOS tchnology of.6um of AMS having a singl-wll. To raliz th quadratur function, a circuit orintd to compnsat th offst du to th BE of th MOSTs, was proposd. Th two proposd circuits, to normaliz th nrgy in th implmntation of th normalizd F, ar fully-programmabls using controlcurrnts which ar listd in Tabls 1 and. Finally, simulation rsults using Hspic validat thortical dvlopmnts. 7 REFERENCES [1]. A Srdjin, C. J. M. rhovn and A. H. M. Rormund ds., Analog C Tchniqus for ow- oltag ow-powr Elctronics, lf Univrsity Prss: Th Nthrlands, [] R.. igr, P. E. Alln, and N. R. Sytradr, S sign Tchniqus for Analog and igital Circuits. McRaw-Hill, N. Y [3]. A. Andras, A. B. Kwabna, and O. P. Philipp, Currnt mod subthrshold MOS circuits for analog S nural systms. EEE Transaction On Nural Ntworks pp. 5-13, [4] Migul Mlndz Rodriguz, sign of ow oltag ow Powr Translinar Circuits for Ral Tim Signal Procssing Applications, Thsis of octor in Elctronics, nstitut National of Astrophysical, Optical and Elctronic, Publa, Mxico, April 1. [5] T. Srrano otarrdona, B. inrs Barranco and A.. Androu, A gnral translinar principl for subthrshold MOS transistors, EEE T. on Circuits and Systms, vol. 46, no. 5, pp , May [6] outr A. Srdijn and Jan Muldr, Rsarch Prspctivs on ynamic Translinar and og- omain Circuits, Kluwr Acadmic Publishrs, Boston, vol., no. & 3, March. [7] Y. Shng, avlt transform, in chaptr 1 of A.. Poularikas, ds., Th Transforms and Applications Handbook, EEE PRESS, [8] R.K. Young, avlt, thory and applications, Kluwr Acadmic Publishrs, Figur 11. Simulation rsults of th normalizd F Figur 1. Simulation rsults du to th translation

5 Figur 8. Proposd circuit for th ralization of a F implmntd in a standard CMOS tchnology. Figur 9. Proposd circuit for th ralization of a normalizd F. Figur 1. Circuit of quadratur: (a) Compnsating th offst and (b) Controlling th voltag at th drain of M5.