Analytical Modelling of conventional DMG-SOI MOSFET using Different Gate Dielectric Material

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1 Intrnational Journal of Enginring Tchnology, Managmnt and Applid Scincs May 017, olum 5, Issu 5, ISSN Analytical Modlling of convntional DMG-SOI MOSFET using Diffrnt Gat Dilctric Matrial a Sourav Guha, b Shubhradip Goswami, c Sayan Bhattacharya, d Sayan Bos, Tiya Dy Malakar RCC Institut of Information Tchnology, Dpartmnt of Elctronics & Communication Enginring, Bliaghata, Kolkata ABSTRACT In a Dual Matrial Gat Silicon on Insulator MOSFET, th short channl ffcts hav bn studid aftr crating a -D analytical modl by varying th insulating matrial undrnath th gat with a highr dilctric constant.in this modl silicon dioxid is rplacd by ZrO which has a highr dilctric constant. This modl has includd th mathmatical calculation rlatd to surfac potntial from which lctric fild along th channl and thrshold voltag ar calculatd by using th minimum surfac potntial. Ky Word: DMG SOI MOSFET, Short Channl Effcts(SCE s), high K dilctric INTRODUCTION Th futur trnd as prdictd by ITRS (Intrnational Tchnology Roadmap for Smiconductors), dimnsional and lctrostatic limitations facd by convntional fabrication tchnology will rquir dimnsional scaling of CMOS dvics [1]. CMOS tchnology volution in th fast fw dcads has followd th dvic scaling to achiv dnsity, spd and powr improvmnt by an xponntial growth in th numbr of transistors pr intgratd circuit as prdictd by Moor s law [].. With continuous rduction of dvic gomtrics on thrshold voltag causs strong dviations from long channl MOSFET prformanc. Th ffct of such dcras in channl lngth is calld SCE (Short channl Effct). Fiv diffrnt short-channl ffcts ar Drain Inducd Barrir lowring and Punch through,locity Saturation, Impact ionization, Surfac Scattring, Hot Elctron.[3 6]Som rigorous rsarch activitis on som innovativ non classical gomtry MOS structurs has lad to th foundation of Fully Dpltd Silicon On Insulator (FDSOI) MOSFET. Howvr, th nano scald SOI MOSFETs suffr from dgradation of thrshold voltag with dcrasing channl lngth and DIBL ffcts [7]. In this papr, w hav utilizd a high K dilctric matrial Zro(Zirconium Dioxid) which hav a maximum dilctric constant of 3 in rplac of convntional gat oxid Silicon Dioxid. In Silicon dvic manufacturing and tchnology, th rfrnc valu of k is takn that of silicon dioxid, SiO, which is 3.9. Dilctric matrial having k>3.9 ar rfrrd to as high-k dilctric.howvr th shrinking of dvic dimnsion lads to rduction of gat oxid thicknss. As a rsult of this th undsirabl hot lctron ffct and th gat tunnlling currnt is incrasd. In ordr to ovrcom this drawback high-k matrials ar usd instad of silicon dioxid as th insulating matrial undrnath th gat. In this papr ZrO is usd as th high-k dilctric matrial. Th aim of this papr is to rduc th short channl ffcts in th DMG SOI MOSFET by using th high-k dilctric matrial. So, using th Poisson s -D quations an analytical modlling of surfac potntial is don from which lctric fild and thrshold voltag of th DMG SOI MOSFET is calculatd. ANALYTICAL MODELLING This is a cross sctional viw of th DMG SOI MOSFET.M 1 and M ar th mtal gats with lngths l1 and l, rspctivly. Th work functions of mtal gats M 1 and M ar 4.8 and 4.6, rspctivly. L is th channl lngth in th DMG structur which is th sum of lngths l1 and l.t oxid is th oxid thicknss h d is th dpltion width,tsi is 15 Sourav Guha, Shubhradip Goswami, Sayan Bhattacharya, Sayan Bos, Tiya Dy Malakar

2 Intrnational Journal of Enginring Tchnology, Managmnt and Applid Scincs May 017, olum 5, Issu 5, ISSN th thicknss of th silicon layr, t box is th thicknss of th burid oxid. Fig 1. Cross sctional viw of DMG SOI MOSFET Th potntial distribution in th thin film of silicon bfor strong invrsion could b mad is givn by Poisson s quation[8] x,y x,y si x y Th dpltion width is givn by w d = si( F b) () qna qna whr F is th Frmi potntial givn by t ln (N A /n i ).N A is th accptor concntration and n i is th intrinsic concntration. Lt, th potntial profil in th vrtical dirction b givn as [1] x,y = s (x)+b 1 (x)y+b (x)y (3) In DMG MOSFET thr ar two diffrnt matrials with diffrnt work functions which ar M1 and M. Thus, th flat band voltags of th two gats can b writtn as FB1 = SM1 = M1 - S and FB= SM = M - S whr S is known to b th work function of th smiconductor which is Eg writtn as S = si F, whr si is th q lctron affinity, E g is th nrgy band gap of silicon and q is th lctron charg.hnc, th diffrntial quation for th two diffrnt matrials will b ( x, y) x b x y b x y ; S x l1, 0 y h d (4) And ( x, y) S x b1 x y b x y ; l1 x l1+l, 0 y h d (5) Boundary conditions for our proposd structur ar as follows : 1) At th intrfac of th two mtals, surfac potntial is continuous. 1( l1,0) ( l,0) l1 (6) ) At th dpltion dg, potntial is 1( x, hd) ( x, hd) (7) 3) Elctric flux is continuous at th junction of two mtals. d ( x, y) at x=l1 is qual to d ( x, y) x=l 1 (8) 4) At th junction of gat/oxid, lctric fild is continuous for both th mtal gats For y=0 d x y x si toxid (, ) x s1( ) GS1 d( x, y) ( x) GS t whr t (9) x s1 (10) si oxid x is th dilctric constant of th oxid and oxid is th thicknss of th gat oxid also GS1 = GS FB1 and GS = GS FB (11) whr GS is th gat to sourc bias voltag and FB1 and FB ar th front channl flat band voltags of th mtal 1 and mtal. 5) At th dpltion dg, lctric fild is zro. d( x, y) d( x, y) at y= h 0 d (1) dy dy 6) At th sourc nd, potntial is 1(0,0) S1(0) bi (13) whr bi is th built in potntial, whr N D is th doping concntration of th sourc/drain. 7) At th drain nd, potntial is ( L,0) S ( L) bi DS (14) at 16 Sourav Guha, Shubhradip Goswami, Sayan Bhattacharya, Sayan Bos, Tiya Dy Malakar

3 Intrnational Journal of Enginring Tchnology, Managmnt and Applid Scincs May 017, olum 5, Issu 5, ISSN whr L= l 1 + l, DS is th applid drain to sourc voltag. Th xprssions of th constants that ar b 11,b 1, b 1 and b can b found by applying th boundary conditions 4) and 5) aftr diffrntiating quation (4) and thn substituting th valus of constants in quations (4) and (5) and thn in (1), w gt th surfac potntial as follows x () x A B S1 1 1 Similarly, for th othr mtal x () x A B S x (15) x (16) By using boundary condition (1),( 6) and (7), th xprssions for th constants A 1,B 1,A and B can b writtn as l1 ( bi 1) ( L1 1) A 1 l1 1 l1 l1 ( bi 1) ( L1 1) B1 l1 1 A B L ( bi DS L1 ) ( ) L l1 l1 L)] Ll1)] ( bi DS ) ( L1 ) L l1 Th xprssion for L1 is givn by l1 L l1) l1 L l1 l1 ( bi DS ) ( bi ) L l1 L1 l1 l1 L 1 l1 L l1 1 (17) Th xprssion for th lctric fild can b obtaind by diffrntiating th quation (15) and (16)and th lctric filds ar givn by RESULTS AND DISCUSSION: In this prsnt work w hav analytically modlld DMG SOI MOSFET for two diffrnt gat dilctric matrial with two mtal gat having work function of 4.8v and 4.6 v rspctivly. Th paramtr usd for simulation is givn in tabl 1 as follows PARAMETER L1 L T ox ᶲ M1 ᶲ M ᶲ B 0 ALUE 50 nm 50nm nm ϵ Si 11.7*8.85*10-1 ϵ ZrO 3*8.85*10-1 Eg t N A 10 1 cm -3 N D 10 6 cm -3 n i 1.5*10 16 cm -3 Tabl 1. vaus of paramtr usd for simulation For our modl GS1 is givn by d( x, y) x x E1 A1 B1 0 x l1 (18) And at y=0 for d ( x, y) x x E A B at y=0 for l1 x L (19) For our proposd modl GS1 is givn by GS1 qn Xmin Xmin F C1 C3 A sitoxidhd [ ] 1 Xmin Xmin si x 4 C C As w know that, Thrshold voltag Th FB1 GS1 Hnc, Th FB1 F [ 1 Xmin Xmin C1 C3 A sitoxidhd Xmin C C4 Xmin qn si ] x (1) (0) 17 Sourav Guha, Shubhradip Goswami, Sayan Bhattacharya, Sayan Bos, Tiya Dy Malakar

4 Intrnational Journal of Enginring Tchnology, Managmnt and Applid Scincs May 017, olum 5, Issu 5, ISSN to th incras of th voltag drop on th smiconductor whn insulators with high prmittivity ar usd. Prmittivity of a substanc rfrs to its ability to rsists th lctric fild. So as prmittivity incrass, th lctric fild dcrass. Th prsnc of th dilctric dcrass th lctric fild producd by a givn charg dnsity. Th factor k by which th ffctiv fild is dcrasd by th polarization of th dilctric is calld th dilctric constant of th matrial. Fig.. ariation of th surfac potntial with channl lngth L (=L1 + L) for DMG-SOI MOSFET. In fig th lctrostatic surfac potntial of th DG MOSFET for low K and high-k dilctric matrials is shown Figur shows th ris in channl potntial whn th matrial of highr dilctric constant is usd. It is obsrvd that th lctrostatic potntial along th channl incrass by rplacing th high-k dilctric matrial as a gat oxid matrial in DG MOSFET. Th lctrostatic potntials nar th drain also incrasd lading to rduction in Drain Inducd Barrir Lowring. Thus, this ris in channl potntial nhancs th dvic prformanc by rduction in th thrshold voltag, short channl ffcts and incras in drain currnt. Fig. 4. ariation of thrshold voltag with channl lngth L (=L1 + L) for DMG-SOI. It can b sn from th figur 4 that as dilctric incrass th thrshold voltag dcrass. This is du th fact that th capacitanc of dilctric is dirctly proportional to its prmittivity and high capacitanc influncs mor charg at th silicon surfac and thrby lads to arly invrsion of carrirs in th dvic. Thus, an optimization of gat dilctric thicknss yilds as a hlping aid in dvic fabrication with targtd thrshold voltags. Fig. 3. ariation of th lctric fild with channl lngth L (=L1 + L) for DMG-SOI MOSFET. From fig 3 it is sn that Si0 has an incras in th lvl of lctric fild than ZrO. Rduction in th lctric fild rducs th hot carrir ffct, which is anothr important short channl ffct. This is du Fig. 5. ariation of thrshold voltag with Gat work function diffrnc for DMG-SOI MOSFET. 18 Sourav Guha, Shubhradip Goswami, Sayan Bhattacharya, Sayan Bos, Tiya Dy Malakar

5 Intrnational Journal of Enginring Tchnology, Managmnt and Applid Scincs May 017, olum 5, Issu 5, ISSN Fig 5 shows th ffct of gat matrial nginring on th thrshold voltag for a DMG-SOI MOSFET with a channl lngth L = 100 nm. It is vidnt from th figur that as th work function diffrnc btwn th mtal gats incrass th thrshold voltag incrass. Significant chang has occurrd du to th us of highr K dilctric oxid. CONCLUSION Th ffctivnss of Dual Mtal Gat MOSFET with high k dilctric ZrO as th oxid mtal has bn analysd. Th analytical thrshold voltag modl of novl structur dvic is prsntd. As xpctd th us of high K dilctric significantly rducs th short channl ffcts. W hav dmonstratd that th DMG structur lads to rducd short channl ffcts as th surfac potntial incrass, which rducs drain conductanc and DIBL. W dmonstrat that th surfac potntial in th channl rgion xhibits a stppd potntial variation by th gat nar th drain, rsulting in supprssd SCEs.Th DMG SOI MOSFET with high k dilctric shows bttr prformanc in supprssing DIBL. Th DIBL is rducd with incrasing dilctric constant. Th analytical thrshold voltag modl is in good agrmnt with th two-dimnsional dvic. Morovr, th lctric fild is rducd, minimizing th hot carrir ffct. Significant chang was obsrvd in th thrshold voltag with th us of high k dilctric ZrO matrial.thus it is concludd that high k dilctric can b usd instad of SiO which furthr rducs short channl ffcts. REFERENCE: [1] Th Intrnational Tchnology Roadmap for Smiconductor, 011, Emrging Rsarch Dvics. [] S. M. Sz, Physics of Smiconductor Dvics, nd d. 1981, p [3] Coling J P. Silicon on insulator tchnology: matrials to LSI. nd d. Norwll, MA: Kluwr: Kluwr Acadmic Publishrs; [4] Mitiko Miura-Mattausch, Hans Jürgn Mattausch, Tatsuya Ezaki, Th Physics and Modling of MOSFET, World Scintific Publishing Co. Pt. Ltd., Singapor,008. [5] G. nkatshwar Rddy and M. Jagadsh Kumar, A Nw Dual-Matrial Doubl-Gat (DMDG) Nanoscal SOI MOSFET Two-Dimnsional Analytical Modling and Simulation, IEEE Transactions on Elctron Dvics, vol..4, no., pp.60-68, 005 [6] TiyaDyMalakar, Partha Bhattacharyya, Subir Kumar Sarkar Analytical Surfac Potntial Modling Basd Small Signal Analysis and RF Prformanc Charactrization of DMG SOI MOSFET for Bttr RFIC Application IETE Tchnical Rviw. [7] N.H.E. Wst, K. Eshraghian, Principls of CMOS LSI Dsign, A Systm Prspctiv, Parson Education, 003 (Chaptr ). [8] K.K. Young, Short-channl ffcts in fully dpltd SOI MOSFET s, IEEE Trans. Elctron Dv. 36,pp , Sourav Guha, Shubhradip Goswami, Sayan Bhattacharya, Sayan Bos, Tiya Dy Malakar

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