Numbering Systems Basic Building Blocks Scaling and Round-off Noise. Number Representation. Floating vs. Fixed point. DSP Design.

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1 Numbring Systms Basic Building Blocks Scaling and Round-off Nois Numbr Rprsntation Viktor Öwall Floating vs. Fixd point In floating point a valu is rprsntd by mantissa dtrmining th rsolution/prcision xponnt dtrmining th dynamic rang Binary numbrs, unsignd intgrs MSB = Most Significant Bit LSB = Last Significant Bit In fixd point w only hav a singl valu Floating point givs highr dynamic rang but th cost is high in nrgy ara calculation tim For nrgy fficint implmntations fixd point is prfrrd N bits N ord () () () () (4) (5) (6) (7)

2 Dynamic rang and Rsolution Nr. of Nr. of Rsolution Dynamic Rang bits lvls V fs =.5V V LSB = V.5V 8 56 mv 8V 496.mV 8V μV 4V How do w us th bits? Dpnds on th application! Unsignd Numbr Rprsntation Fixd radix (bas) systms Th digits a {,,,... r } in a radix r systm: l i r ai = i= k = rk a k l k r ak r a r a r a r a l dscribd in a fixd point positional numbr systm: ai ai aa. a a l Fractional part Exampl: Unsignd Numbr l i ai = { a {,,,... 9} in radix } i= k = k a k l k ak a a a a l Exampl: Unsignd Numbr l i ai = { a {,} in radix } i= k = k a k l k ai a a a a l l i ai = { a {,} in radix } i= k = k a k l k ai a a a a l. 4 i + i + i + i + i + i + i + i =

3 Signd Digit Numbr Rprsntation Th digits a { α,, r α } in a radix r systm: l i r ak i= k Exampl Radix : a { 4,,, 4,5} ( 5) = + 5 = + 5 = 95 (. 5) = + 5 =.+.5 =.95 Signd Numbr Rprsntation Sign Magnitud On s Complmnt Two s Complmnt Signd Magnitud Unsignd numbrs with a sign-bit On s Complmnt Signd numbrs by invrting (Complmnt) - - Signd Magnitud - - Two Zros + Low Powr? + Easy to convrt to Ngativ - On's Complmnt Two Zros + Easy to convrt to Ngativ

4 - - Two s Complmnt Most widly usd fixd point numbring systm Two's Complmnt Complmnt + LSB + On Zro + Easy Addition - Not so asy to convrt to Ng Two s Complmnt Th digits a {, } in a radix systm: l k a i k + ai = i= k = k a k l k ak a a a a l dscribd in a fixd point positional numbr systm: ak ak aa. a a l Sign Bit Fractional part Exampl: s complmnt Sign Extnsion in Two s Complmnt. 4 i + i + i + i + i + i + i + i = k a k k + ak a + a = ka k k k a + k + ak a + a = k+ a k k k k + ak a k ak a a Exampl: = = = = = = = = 4

5 h Th Wordlngth, i.. nr of bits D D D h h UMTS-filtr float h Evry xtra bit costs nrgy/powr dlay ara th wordlngth has to b rducd 7bits Th Wordlngth, i.. nr of bits h D D D h h Th output of addr output nds an xtra bit to b sur of no ovrflow,.g. dcimal: + = 4 binary: += h multiplir MxN bits M+N bits for full prcision Prcision has to b limitd Basic Building Blocks D D D h h h h Basic Building Blocks In th FIR filtr addrs multiplirs rgistrs in othr algrithms also: shift, minus, division,... lft shift is multiply by right shift is a divd by but is low complxity! 5

6 Comparing Basic Building Blocks High Complxity Dividr Multiplir Addr/Subtarct a b a b a b a a b a b a b a b a b a b a b a b a b a b a b b a b Scaling and Round-off Nois Shiftr a b a b a b a b p 6 p 5 p 4 p p p p Low a a b a b s b s a b s s Quantization Quantization Two Typs Cofficint Quantization Non-Idal Transfr Function Compar to analog componnt variations Signal Quantization Round-off Nois Limit Cycls Round-off Nois Affct th output as a random disturbanc Limit Cycl Oscillations Undsird priodic componnts Du to non-linar bhavior in th fdback (rounding or ovrflow) 6

7 Quantization Analysis Using ral rounding, truncation, and ovrflow Giv xact rsult Tricky - nd intgr rprsntation Using nois modls Floating point rprsntation can still b usd Suitabl for Matlab, C/C++... Rounding Truncation Rounding/Truncation is always thr! Espcially ncssary in rcursiv systms Q Without quantization - infinit wordlngth Multiplication n+m output bits Addition n+ output bits Truncation and Rounding Lvl X+ Lvl X+ Truncation Rounding Truncation Rounding No nrgy addd to th systm Oftn usd in rcursiv algorithms Truncation towards zro Lvl X Lvl X Truncation All valus approximatd in th sam dirction Max rror = LSB Avrundning Valus approximatd up or down Max rror = / LSB DC rror Roundd to vn Add LSB bfor truncation if ngativ 7

8 Scaling Exampl Whr Scaling is Ndd Adjust signal rang to fit th hardwar Unchangd transfr function (Scald cofficints might mov th pol-zros) -.5 un ( ) = ± 4 Trad-off Scal up to rduc roundoff nois Scal down to avoid ovrflow But you loos prcision! Ovrflow β f(n) f(n) Scaling β Saf scaling if = f ( i) i= Whr f(i) is th unit sampl rspons β /7 Exampl: Saf Scaling β = i= f(i) = = xn ( ) and yn ( ) 7 giv saf scaling h(n) Incrasd roundoff nois Intrnal scaling might improv 7/ (Linar phas FIR. Not th strngth rduction) 8

β Exampl: Saf Scaling i = i= f(i) = i= ( 5. ) = 5 + 5 + 5 + = =. 5 (. ) (. ) (. ) Gomtric sris -.5 -.

with β = ±n Easy to do - a shift Incrasd intrnal wordlngth an altrnativ Original filtr with ovrflow.

9 β Exampl: Saf Scaling i = i= f(i) = i= ( 5. ) = = =. 5 (. ) (. ) (. ) Gomtric sris Scaling Saf scaling is pssimistic Altrnativ is scaling with β = i ( f ( i ) ) = In practic: Scaling with β = ±n Easy to do - a shift Incrasd intrnal wordlngth an altrnativ Original filtr with ovrflow.5 Pacmakr xampl Th Elctrocardiogram (EGM) tim [ms] 9

10 Th Intrfrd signal Filtring Prformanc EGM + Intrfrnc from AC hand drill db SNR T().5 Output of th GLRT and thrshold tim, [ms] EGM with addd intrfrnc Wavlt Filtrbank Bit-optimization Signals hav bn monitord to dtrmin th uppr bound of th wordlngth Comparison of worst-cas wordlngth and implmntd wordlngth at th wavlt output: F ( z) = + z + z + z G ( ) b z = + z y y y y 4 y 5 y 6 N wc N+6 N+7 N+ N+ N+4 N+5 N Imp N+ N+ N+ N+ N+ N+

11 Exampl: Intrnal Scaling VHDL bit-lvl simulation 4-point FFT Compard with Matlab floating-point simulation Optimizd intrnal scaling A 6-point Radix- FFT W W 4 W Basic Buttrfly unit W Data In Radix Radix Radix Radix Radix Data Out W 6 W 8 W W 4 Countr Stag 5 Stag 4 Stag Stag Stag W W W W W W 4 Clock W 4 W 5 W W Whit nois input Sourc: Frdrik Kristnsn W 6 W 7 W 4 W 6 W W 4 Data In Exampl: Intrnal Scaling VHDL bit-lvl simulation 4-point FFT Compard with Matlab floating-point simulation Optimizd intrnal scaling 8-bits -bits -bits 4-bits 4-bits -bits Radix Radix Radix Radix Radix Data Out Limit Cycls Countr Stag 5 Stag 4 Stag Stag Stag Clock Whit nois input Sourc: Frdrik Kristnsn

12 Limit Cycls Exampl: zro input oscillations in nd ordr IIR b Q Limit Cycls Zro Input Exampl: zro input oscillations Rounding aftr multiplication X(n) Q b Truncation aftr multiplication b = =.9565; b = = Sourc: Lars Wanhammar, DSP Intgratd circuits Limit Cycls.8 Pols clos to th unity circl Matlab: zplan(,[ ]) Limit Cycls Changing th prcision mov th pols! Zro input oscillations Oftn not accptd in audio Vry difficult problm Ral Part In gnral, no solutions for structurs > nd ordr Can b limitd by incrasd intrnal wordlngth Can in som nd ordr structurs b liminatd by pol positioning nd ordr Wav Digital Filtrs ar fr from parasitic oscillations Imaginary Part Imaginary Part Pols clos to th unity circl Matlab: zplan(,[ ]) zplan(,[ ]) Ral Part Imaginary Part Ral Part

Ovrflow Oscillations Saturation Arithmtic C out-msb = NOF From Addr -bit two s complmnt sum Corrct sum Oscillations ar limitd by saturation -bit saturatd sum C out-msb C in-msb C in-msb = POF Signbit

13 Ovrflow Oscillations Saturation Arithmtic C out-msb = NOF From Addr -bit two s complmnt sum Corrct sum Oscillations ar limitd by saturation -bit saturatd sum C out-msb C in-msb C in-msb = POF Signbit Saturatd Output Ovrflow chang th sign Corrct sum Ovrflow if C out-msb diffrs from C in-msb Limit Cycls du to ovrflow Zro Input Two s Complmnt Arithmtic Saturatd Arithmtic Amplitud 5-5 Limit cycls du to ovrflow Lab Exampl Tim Saturation input unquantizd output quantizd output Amplitud 5-5 Wrap around Lab Exampl input unquantizd output quantizd output Sourc: Lars Wanhammar, DSP Intgratd circuits Tim

14 Limit cycls du to ovrflow 5 Lab Exampl input unquantizd output quantizd output Wrap around Amplitud -5 5 Lab Exampl input unquantizd output quantizd output Simpl Nois Analysis Tim Saturation Amplitud Tim Scaling and Whit Nois Input β = δ β = f (), i Saf scaling i = f (), i possibl ovrflow i = ( ) = unit sampl rspons, ( ) = Varianc whit nois input i= f i f i 5 bits Q 8 bits a 8 bits Rounding (n) Modl a Saf scaling but not guarantd δ sts th probability for an ovrflow Typically on ovrflow vry 6 sampl is accptd in audio [Wanhammar] 4

15 5 bits Q 8 bits a 8 bits Rounding ( ) ( ) u n (n) n ( ) = u n un ( ) Modl Modld with addd nois as an input rror a Roundoff Nois If th quantization rror probability is uniformly distributd in th intrval Δ Δ ( W ) n ( ) whr Δ = W is th numbr of bits aftr th rounding Δ P () ½LSB Δ Δ Roundoff Nois Man valu = E[( n)] = Δ / Varianc = E[ ( ) ] = ( ) P ( ) d = [ = ] Δ / Δ / W Δ /8 Δ /8 Δ = = = Δ Δ Δ/ Δ P () ½LSB Δ Δ Exampl: Roundoff Nois In th cas of rounding (man=) th varianc and th avrag powr ar th sam, i.. if a valu is roundd th quantization nois bcoms: σ = W If w scal down on bit: ( W ) W = = 4 σ 5

16 Signal to Nois Ratio (SNR) On xtra bit rducs quantization rror by a factor 4 Signal to Nois Ratio (SNR) Signal powr (varianc) SNR = log 4σ = 6. σ db SNR σ = log = log σ W x σ x Good to rmmbr: 6 db incras in SNR pr bit Roundoff rror powr (varianc) Signal to Nois Ratio (SNR) Exampl: Full scal sinus wav roundd to 8 bits A SNR = log = 5 db; - A 8 Roundoff Nois: Addition E[( ) + ] = E[ + + ] = = E[ ] + E[ ] + E[ ] = zro if u and u indpndnt u (n) u (n) (n) = E[ ] + E[ ] (n) 6

17 Exampl: Roundoff Nois First ordr IIR-filtr, th varianc is: σ f () i = σ ( ( ) ( ) ( ) ) i + a + a + a = σ = a a =..σ a a =.5.σ a = σ Narrow band filtr (n) i= No fdback a =.998 Exampl: SNR Exampl: Full scal sinus, roundd to 8 bits in IIR σ f ( i) = σ a SNR 5 σ = 5dB SNR = db (n) a 7

Numbering Systems. Computational Platforms. Scaling and Round-off Noise. Special Purpose. here that is dedicated architecture

Numbering Systems. Computational Platforms. Scaling and Round-off Noise. Special Purpose. here that is dedicated architecture Computational Platforms Numbering Systems Basic Building Blocks Scaling and Round-off Noise Computational Platforms Viktor Öwall viktor.owall@eit.lth.seowall@eit lth Standard Processors or Special Purpose