6. Negative Feedback in Single- Transistor Circuits
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- Lorin Wheeler
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1 Lctur 8: Intrductin t lctrnic analg circuit Ngativ Fdback in Singl- Tranitr ircuit ugn Paprn, 2008 Our aim i t tudy t ffct f ngativ fdback n t mall-ignal gain and t mall-ignal input and utput impdanc f t ingl-tranitr circuit. Our tudy will b bad n gnric functinal mdl f t circuit ( Fig Singl-tranitr circuit wit n fdback Lt u tart frm analyzing t mall-ignal gain f a circuit wit n fdback [ Fig. (a], ( dc < dc < dc L< v v f b r g m v R i b R in r xampl v wr i t mall-ignal input tranmiin R in r R in g m (R r, (2 i t ignal urc valu, i t ignal at t cntrl prt f t dpndnt urc f t tranitr mdl, and i t mall-ignal pn-lp gain. (3 dc < Σ (a dc < Σ dc L< dc < dc < dc < quatin ( w tat t mall-ignal gain i dirctly prprtinal t t mall-ignal pn-lp gain. Ti may b a riu diadvantag bcau dpnd n t tranitr mall-ignal paramtr, wic ar vry nitiv t t tranitr tcnlgy and tmpratur. On t tr and, ti can b an advantag if t maximum gain i rquird and it xact valu i nt imprtant. W will al latr wn tudying pitiv fdback, tat t circuit wit n fdback i alway tabl prvidd it and gain ar tabl. In t nxt cur n lctrnic analg circuit, yu will a wll tat adding ngativ fdback can limit t frquncy rang f t circuit Singl-tranitr circuit wit fdback Lt u nw find t cld-lp gain f a ingl-tranitr circuit wit fdback [ Fig. (b] Fig.. Functinal (blck diagram f lctrnic circuit (a witut and (b wit fdback. D (b D, (4 RR wr i t mall-ignal fdback tranmiin f t fdback ntwrk, i t mall-ignal fdfrward tranmiin f t fdback ntwrk,
2 Lctur 8: Intrductin t lctrnic analg circuit i t rturn rati, i t mall-ignal dirct tranmiin, and RR (5 D (6 (7 i t dnitivity factr r t amunt f fdback. W will dfin a fdback a ngativ r pitiv if it dcra r incra, crrpndingly, t cld lp gain rlativ t. It viu frm (4 tat > crrpnd t a ngativ fdback, < crrpnd t a pitiv fdback, and crrpnd t n fdback. dvantag f ngativ fdback Frm matmatical pint f vw, bt t advantag and diadvantag f ngativ fdback ar rlatd t t dnminatr, r, in (4. Fr >>, t cld lp gain bcm innitiv t t pn-lp gain : Ti man tat t rlativ cang in y a factr f lwr tan t rlativ cang in. Nt tat wit n fdback, lik t ca f Fig. (a, δ δ. Du t t ngativ fdback, bcm by a factr f l nitiv t. T main diadvantag f t ngativ fdback i rlatd t t frquncy dpndnc f t rturn rati. If tr i a frquncy wr, tn in (4, ; t fdback turn ut t b pitiv, and t circuit (amplifr bcm untabl: it can prduc a utaind utput, fr xampl, utaind cillatin, wit n input. W will tudy uc a bavir f tranitr circuit in t lctur ddicatd t pitiv fdback cillatr. Finding partial gain T dfin t partial gain in (4 (7 in trm f t ignal at t circuit input,, utput,, and t cntrl trminal f t dpndnt urc,, w firt aum tat in a gnric ingl-tranitr circuit ( Fig. 2 tr i nly a ingl dpndnt urc and, tn, w will lv ti circuit by applying uprpitin. Y, w will apply uprpitin dpit t fact tat n in t urc in Fig. 2 dpnd n t tr. Hwvr, w will d it carfully.. (8 mainly dpnd n t mall-ignal input tranmiin and t tranmiin and f t fdback circuit. Fr an arbitrary rturn rati, w can find t nitivity f t a fllw: d d 2 ( ( 2 2 ( ( 2 ( if >> D (. (9 d d, r δ δ
3 Lctur 8: Intrductin t lctrnic analg circuit W av n difficulty t find t cntributin f t urc t all t tr ignal in Fig. 2(a. T d ti, w imply uppr t dpndnt urc a wn in Fig. 2(b. Hwvr, wn w ar finding t cntributin f t dpndnt urc a, w cannt imply uppr t indpndnt urc. Ti i bcau zring t urc al zr t a urc and it cntribut nting. T lt t dpndnt urc a t cntribut t am way it d in Fig. 2(a, bfr applying uprpitin, w av t "rmind" t a urc in Fig. 2(c it riginal valu a, wic it ad in Fig. 2(a. [If yu d nt lik t wrd t "rmind" mting t a dpndnt urc, yu can rplac it in Fig. 2(d wit an quivalnt indpndnt urc aving t valu a. Or yu can aum tat t dpndnt urc in Fig. 2(c till dpnd n t riginal valu f in Fig. 2(a.] W nw can dfin a D Singl-tranitr circuit (a ' a 0 ' ', (0 D, ( Singl-tranitr circuit (b, (2 " a, (3 0 " RR. (4 In a gnral ca, t numbr f indpndnt ignal urc in a ingl-tranitr circuit can b gratr tan n, but by applying uprpitin, t circuit can alway b lvd fr ac f tm paratly. ac indpndnt urc i will av diffrnt i,, and D i gain, wr i i t dpndnt urc numbr. Individual cld-lp gain can b fund in ti ca a 0 Singl-tranitr circuit (c " a " i i Di. (5 It imprtant t nt tat t lutin fr t dpndnt urc rmain t am, and and in (3 uld b fund nly nc. T vry imprtant advantag f t nw gnric apprac ar tat it allw fr: rcgnizing t fdback in a ingl-tranitr circuit, finding t partial tranmiin and gain f t circuit, ditinguiing btwn ngativ an pitiv fdback, Singl-tranitr circuit (d Fig. 2. Finding partial mall-ignal tranitin and gain f a ingl-tranitr circuit. lving t circuit in t implt way: ac tim it i lvd fr a ingl urc nly (ti apprac i mt pwrful and inigtful in n analyi, wn quit a fw indpndnt quivalnt n urc ar cnnctd t t circuit and cntributin f all f tm
4 Lctur 8: Intrductin t lctrnic analg circuit uld b fund paratly t idntify t dminant n urc. V Finding cld-lp gain: xampl circuit Lt u nw t lv t lmntary amplifr ( Fig. 3 fr t cld-lp gain: v V R v O b, ( v v v R r, (2 b i' b v f v v i f ( R, (3 R r RR ib R f. (4 i R v i' b f 0 v v f( R R f R. (5 v 0 i" b R f r v' In t xam, yu d nt av t implify any lutin fr, but w will d it r t b ur tat t nw lutin i idntical t tat btaind in Lctur 3. R r v" Fig. 3. xampl circuit : t lmntary amplifr, lvd wit t π mdl f t tranitr.
5 Lctur 8: Intrductin t lctrnic analg circuit ( R f R f R R f R f f v r v R r R ( f f ( f r ( r f. (6 R r r f r i' b r f 0 v R r R r v' Finding cld-lp gain: xampl circuit 2 Lt u nw find t cld-lp gain fr t am circuit but by uing t T mdl fr t tranitr. i" b f b, ( v r v v 0 r v" v R r, (2 b i' b R r RR v i b 0, (3 ib f. (4 i Fig. 4. xampl circuit 2: t lmntary amplifr, lvd wit t T mdl f t tranitr. RFRNS [] P. R. ray, P. J. Hurt, S. H. Lwi, and R.. Myr., nalyi and Dign f nalg Intgratd ircuit. (4t ditin. r 0 f r. (5 R r
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