AON679 3V NChannel SRFET General Description Trench Power αmos Technology Low R DS(ON) Low Gate Charge High Current Capability RoHS and HalogenFree Compliant Product Summary V DS I D (at V GS =V) R DS(ON) (at V GS =V) R DS(ON) (at V GS =.5V) 3V 85A <.8mΩ < 3.5mΩ Applications DC/DC Converters in Computing Isolated DC/DC Converters in Telecom and Industrial % UIS Tested % Rg Tested Top View DFN5X6 Bottom View Top View D 3 8 7 6 SRFET TM Soft Recovery MOSFET: Integrated Schottky Diode PIN PIN 5 G S Orderable Part Number Package Type Form Minimum Order Quantity AON679 DFN 5x6 Tape & Reel 3 Absolute Maximum Ratings T A =5 C unless otherwise noted Parameter DrainSource Voltage GateSource Voltage Avalanche energy L=.5mH V DS Spike C Symbol V DS V GS I DM I AS E AS V SPIKE Maximum 3 Continuous Drain T C =5 C 85 I Current G D T C = C 6 Pulsed Drain Current C 9 Continuous Drain Current Avalanche Current C µs Power Dissipation B T C = C 7 Power Dissipation A T A =5 C T A =7 C T C =5 C T A =5 C T A =7 C Junction and Storage Temperature Range T J, T STG 55 to 5 Thermal Characteristics Parameter Symbol Typ Maximum JunctiontoAmbient A t s 5 Maximum JunctiontoAmbient A D R θja SteadyState Maximum JunctiontoCase SteadyState R θjc. P D ± 37 I DSM 3 36 P DSM 6. Max 5 3 Units V V A A A mj V W W C Units C/W C/W C/W Rev..: October www.aosmd.com Page of 6
Electrical Characteristics (T J =5 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage ID=mA, VGS=V 3 V I DSS V DS =3V, V GS =V.5 Zero Gate Voltage Drain Current ma T J =55 C I GSS GateBody leakage current V DS =V, V GS =±V ± na V GS(th) Gate Threshold Voltage V DS =V GS, I D =5µA..5.9 V R DS(ON) V GS =V, I D =A.3.8 mω Static DrainSource OnResistance T J =5 C 3.. V GS =.5V, I D =A.8 3.5 mω g FS Forward Transconductance V DS =5V, I D =A 67 S V SD Diode Forward Voltage I S =A,V GS =V.5.7 V I S Maximum BodyDiode Continuous Current 3 A DYNAMIC PARAMETERS C iss Input Capacitance 5 pf C oss Output Capacitance V GS =V, V DS =5V, f=mhz 7 pf C rss Reverse Transfer Capacitance 7 pf R g Gate resistance f=mhz.9.8.7 Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 37.5 nc Q g (.5V) Total Gate Charge 7 nc V GS =V, V DS =5V, I D =A Q gs Gate Source Charge 5 nc Q gd Gate Drain Charge 5 nc t D(on) TurnOn DelayTime 7 ns t r TurnOn Rise Time V GS =V, V DS =5V, R L =.75Ω, 3.5 ns t D(off) TurnOff DelayTime R GEN =3Ω 36 ns t f TurnOff Fall Time 6 ns t rr Body Diode Reverse Recovery Time I F =A, di/dt=5a/µs 5.5 ns Q rr Body Diode Reverse Recovery Charge I F =A, di/dt=5a/µs 33 nc A. The value of R θja is measured with the device mounted on in FR board with oz. Copper, in a still air environment with T A =5 C. The Power dissipation P DSM is based on R θja t s and the maximum allowed junction temperature of 5 C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) =5 C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Single pulse width limited by junction temperature T J(MAX) =5 C. D. The R θja is the sum of the thermal impedance from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3µs pulses, duty cycle.5% max. F. These curves are based on the junctiontocase thermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) =5 C. The SOA curve provides a single pulse rating. G. The maximum current rating is package limited. H. These tests are performed with the device mounted on in FR board with oz. Copper, in a still air environment with T A =5 C. THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Rev..: October www.aosmd.com Page of 6
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS.5V V DS =5V 8 3V 8 I D (A) 6 V I D (A) 6 5 C 5 C V GS =.5V 3 5 V DS (Volts) Figure : OnRegion Characteristics (Note E) 3 5 V GS (Volts) Figure : Transfer Characteristics (Note E) 5.8 R DS(ON) (mω) 3 V GS =.5V V GS =V Normalized OnResistance.6.. V GS =V I D =A V GS =.5V I D =A 5 5 5 3 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage (Note E).8 5 5 75 5 5 75 Temperature ( C) Figure : OnResistance vs. Junction Temperature (Note E) I D =A.E 8.E 5 C R DS(ON) (mω) 6 5 C I S (A).E.E.E3 5 C 5 C.E 6 8 V GS (Volts) Figure 5: OnResistance vs. GateSource Voltage (Note E).E5....6.8. V SD (Volts) Figure 6: BodyDiode Characteristics (Note E) Rev..: October www.aosmd.com Page 3 of 6
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 V DS =5V I D =A 3 5 C iss V GS (Volts) 6 Capacitance (pf) 5 C oss 5 C rss 3 Q g (nc) Figure 7: GateCharge Characteristics 5 5 5 3 V DS (Volts) Figure 8: Capacitance Characteristics I D (Amps).... R DS(ON) limited DC µs µs µs ms ms Power (W) 5 3 T J(Max) =5 C T C =5 C. T J(Max) =5 C T C =5 C... V DS (Volts) V GS > or equal to.5v Figure 9: Maximum Forward Biased Safe Operating Area (Note F)..... Figure : Single Pulse Power Rating Junctionto Case (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =3 C/W Single Pulse In descending order D=.5,.3,.,.5,.,., single pulse P D T on T...... Figure : Normalized Maximum Transient Thermal Impedance (Note F) Rev..: October www.aosmd.com Page of 6
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 5 8 Power Dissipation (W) 3 Current rating I D (A) 6 5 5 75 5 5 5 5 75 5 5 T CASE ( C) Figure : Power Derating (Note F) T CASE ( C) Figure 3: Current Derating (Note F) T A =5 C Power (W)... Figure : Single Pulse Power Rating JunctiontoAmbient (Note H) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja =5 C/W Single Pulse In descending order D=.5,.3,.,.5,.,., single pulse P D T on T..... Figure 5: Normalized Maximum Transient Thermal Impedance (Note H) Rev..: October www.aosmd.com Page 5 of 6
Gate Charge Test Circuit & Waveform Qg V Qgs Qgd Ig RL Resistive Switching Test Circuit & Waveforms Charge Rg 9% % td(on) t r t d(off) t f t on t off Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L E = / LI AR AR BV DSS Rg Id Id I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr Rev..: October www.aosmd.com Page 6 of 6