Physics 3150, Laboratory 9 Clocked Digital Logic and D/A Conversion

Transcription

1 Nots: Physis 0, Lortory Clok Diitl Loi n D/A Convrsion Mrh n 0, 0 By E Eylr n Gor Gison, s in prt on Hys n Horowitz Lst rvis Mrh, 0, y E Eylr () Thr will only on mor orniz l sssion, on April n. Th rst o th smstr will vot to your inl projts. () I you think tht your svn-smnt isply will usul or your inl projt, it s O to lv it wir on ror tr th l ns. Purpos:. To us inry or hip to riv svn-smnt numri isply tht n us or utur projts.. To stuy squntil loi y uilin ountrs, irst with lip-lops, thn with it ountr hip. Your isply n us to show th hnin ount vlus.. To us DAC t th ountr output, nrtin 0-stp or -stp nlo rmp. Rrns: Chptr o Elston; Chptr o Myr; Dt shts on th Rsours stion o th ours w p. Equipmnt:. Diitl osillosop.. Bror with loi swiths, loi initor LEDs, n V supplis.. A or LS or/rivrs.. DL0R or MANA or LNGA svn-smnt LED isply.. LS or CD0 or LS -it ountrs.. LS or lip-lops.. TLC -it DACs n LF op mps.. Douplin pitors, 0.0 F or 0. F.

2 I. Drivin svn-smnt isply A typil LED isply hip onsists o svn LED lin smnts plus iml point, ll shrin ommon no. Normlly th no is onnt to +V supply throuh urrnt-limitin rsistor o out ohms. Thn whn th pin orrsponin to ny o th lin smnts is pull low, th smnt is illumint. (Th rihtnss will oviously vry pnin on th numr o smnts illumint; or mor uniorm intnsity, sprt pullup rsistors oul us or h smnt.) To isply numrs in th wy w r us to sin thm, w n n rry o ts tht trmin whih smnts r to lit. This woul lrly lot o work i you uilt it up rom NAND ts. But ortuntly just suh n rry is provi or you in th A or th vry similr LS, mmrs o ro lss o hips sri s ors, whih monitor two or mor input lins n ssrt vrious omintions o output lins s on th input t n th intrnl loi mp. (Inintlly, ritrrily omplx tsks o this typ n prorm y prormml t rrys, or ltrntivly y mmory hips i thy r prormm so th t t h rss orrspons to th sir output or th omintion o input lins sltin tht prtiulr rss.) Th outputs o th A n sink nouh urrnt in thir low stt to irtly riv th isply, whih is why it s ll or-rivr hip. In on ornr o your ror, wir up your isply to th rivr s shown, thn tst it y ssrtin th tiv-low tst input on pin thr. All svn smnts shoul thn illumint to orm th numr. I you lik, ply with th inputs y rounin thm or lttin thm lot hih to isply vrious othr numrs. Inputs Gn to tst A 0 A A A LT A BI/RBO RBI Gn 0 DL0R no 0 00, LNGA no p p 00,0 Dor/rivr Dor/rivr n -smnt n -smnt isplys. Th isply MANA is pin-omptil with DL0R i its xtr pins r inor.

3 II. Bsi ountr usin lip-lops Th J- lip-lop, whih is not vry wily us ny mor, ors lot o vrstility with its svrl oprtin mos. In this l you n to know only two o thm: whn J n r oth hih, th output will hn stt, or tol, with vry lok puls. By ontrst, whn thy r oth low, th output will rmin unhn whn th lok input is puls. W will us th LS (or ), whih hs n unusul pinout, s shown in th iur. Not tht ths r - pin pks. Th pins r still numr ountrlokwis roun th hip. J S R J S R 0 Not th non-stnr powr suppy pins Gn (Wir S,R hih i unus.) LSA lip-lop Thr r two kins o ountrs, rippl n synhronous. In oth ss, h lip-lop ountr st ivis y, so th outputs onstitut inry numr ountin th numr o lok pulss. W will uil ountr with just two sts, so w n only ount rom zro to thr. By simpy in mor sts, you n ount hihr. A. Rippl ountr In rippl ountr, th lok puls or ny lip-lop is riv rom th prvious st, n so th lok puls J 0 J rippls throuh th iruit n th outputs o not Clk hn simultnously. Cution: Countrs r vry susptil to nois. B sur to us ypss pitors rom th powr supply pin to roun, n us ln lyout or th lok sinls. Also, wir ll our o th S n R inputs hih, so tht thy will not us rrti rsts u to nois pikup. ) Buil th iruit n lok it with squr wv input. Exmin th outputs with sop or y onntin thm to your isply rivr. ) Trir your osillosop with th lok n s i you n tt th ly in th trnsition o. B. Synhronous ountr In th synhronous ountr, h lip-lop is lok with th input lok, n h o th outputs is immitly upt, s n, pnin on th stt o th prvious st. Buil two-st ountr s init, n try to vriy tht thr is no rippl ly. Clk J 0 J

4 ustion: ) Explin how h ountr works. III. Up-own ountr Cution: Ths ountrs r prtiulrly susptil to nois pulss. B sur to ollow th vi ivn in Stion II.A ov. Th LS n LS r vry similr nrl-purpos ourit ountrs, vryin only in tht th ounts in BCD, so th nxt output tr is 0, not 0A hximl. Th CD0 is nwr CMOS vrint o th LS, with similr proprtis whn oprt with V powr supply. Th ountrs hv prlo inputs (whih w won t us), so tht spii initil vlu n lo whn n. It lso hs rry n orrow outputs, so tht n ritrrily lr ountr n uilt y sin ths hips, onntin rry to th Count Up (CPU) input o th nxt st n orrow to th Count Down (CPD) input. To Disply Drivr Count Up Count Down From lok or oun push utton CP U CP D MR 0 PL TP U LS TP D P 0 P P P Gn 0 Crry Borrow To CP U, CP D o nxt st Prlos (inor) Wir up your ountr usin ithr hip, in sur to st Mstr Rst (MR) low so th ountr is nl. You shoul lso st th Lo input ( PL ) hih, tothr with whihvr lok input (CPU or CPD) you r not usin t th momnt. In prti thy will lot hih or th LS vrsions o th hips, ut not or th CMOS vrsion, n vn or th LS vrsion thr will prolms with nois-inu hns o stt i ths inputs r lt isonnt. Usin your svn-smnt isply rivr, isply th outputs 0- whil ountin up n own usin slow lok. I you us LS, wht hppns to th isply whn you ount throuh th stts orrsponin to iits lrr thn nin? Dtrmin whthr th MR input is synhronous or synhronous y ssrtin it twn lok yls. Why o you think this hoi ws m y th hip sinrs?

5 IV. Diitl to nlo onvrtr Convrt th ountr you just uilt to low-rsolution rmp nrtor y usin iitl-to-nlo onvrtr hip. Th TLC is tritionl urrnt-swith DAC. It lso uss ur iitl input with lths, to ilitt omputr us intrin, ut w will mk th lths trnsprnt y tivtin th hip nl n writ pins simultnously. This prtiulr DAC hs its o rsolution, so unlss you hv tim to wir nothr ountr hip, you shoul just us th our most siniint its. Th DAC swiths rsistor lr s on its inputs, so with th ition o rrn volt on pin, it ts s urrnt sour. It n lso us kwrs s stn-lon volt sour, s shown in Fi. o its spiition sht (s th Rsours stion o th ours w p). Howvr, whn volt sour is n, th DAC is most otn us to riv n op mp s shown low. Dt in rom ountr + or +V (Sts output rn) Powr: ± or ± V On pins, On your DAC is onnt, wth it stp throuh th ountr output vlus, thn st th lok str to mk sixtn-lvl rmp. At vry hih lok sps, you will proly s lr lith rom th DAC vry tim it swiths. Wht o you think uss this?