MC74VHCT157A. Quad 2 Channel Multiplexer

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Eugenia Quinn
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1 MTA Quad hannel Multiplexer The MTA is an advanced high speed MO quad channel multiplexer fabricated with silicon gate MO technology. It achieves high speed operation similar to equivalent Bipolar chottky TT while maintaining MO low power dissipation. It consists of four input digital multiplexers with common select () and enable (E) inputs. When E is held igh, selection of data is inhibited and all the outputs go ow. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The T inputs are compatible with TT levels. This device can be used as a level converter for interfacing. to.0 because it has full.0 MO level output swings. The TA input structures provide protection when voltages between 0 and. are applied, regardless of the supply voltage. The output structures also provide protection when = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. The inputs tolerate voltages up to.0, allowing the interface of.0 systems to.0 systems. Features igh peed: t PD =. ns (Typ) at =.0 ow Power Dissipation: I = A (Max) at T A = TT ompatible Inputs: I = 0.8 ; I =.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for.0 to. Operating Range ow oise: OP = 0.8 (Max) Pin and Function ompatible with Other tandard ogic Families atchup Performance Exceeds 00 ma ED Performance: uman Body Model > 000 ; Machine Model > 00 hip omplexity: 8 FETs or 0 Equivalent Gates Pb Free Packages are Available* OI D FFIX AE B TOP DT FFIX AE 98F OEIAJ M FFIX AE 9 MARKIG DIAGRAM TAG AWYWW T A AYW A = Assembly ocation W, = Wafer ot Y = Year WW, W = Work Week G or = Pb Free Package (ote: Microdot may be in either location) FTIO TABE T AYWG Inputs Outputs E Y0 Y X A0 A B0 B A0 A, B0 B = the levels of the respective Data Word Inputs. *For additional information on our Pb Free strategy and soldering details, please download the O emiconductor oldering and Mounting Techniques Reference Manual, ODERRM/D. ORDERIG IFORMATIO ee detailed ordering and shipping information in the package dimensions section on page of this data sheet. emiconductor omponents Industries,, 00 December, 00 Rev. Publication Order umber: MTA/D

2 MTA A0 E B0 A Y0 B A Y B A Y 0 B GD 8 9 Y Figure. Pin Assignment A0 B0 Y0 IBBE IPT A B A B 0 9 Y Y DATA OTPT E A B Y Figure. Expanded ogic Diagram E A0 B0 A B A B A B 0 E G MX 9 Figure. IE ogic ymbol Y0 Y Y Y This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GD ( in or out ). nused inputs must always be tied to an appropriate logic voltage level (e.g., either GD or ). nused outputs must be left open.

3 MTA MAXIMM RATIG (ote ) ymbol Parameter alue nit Positive D upply oltage 0. to +.0 I Digital Input oltage 0. to +.0 OT D Output oltage Output in tate igh or ow tate 0. to to +0. I IK Input Diode urrent 0 ma I OK Output Diode urrent 0 ma I OT D Output urrent, per Pin ma I D upply urrent, and GD Pins ma P D Power Dissipation in till Air OI Package 00 mw TOP 80 T TG torage Temperature Range to +0 ED ED Withstand oltage uman Body Model (ote ) >000 Machine Model (ote ) harged Device Model (ote ) >00 >000 I ATP atchup Performance Above and Below GD at (ote ) 00 ma JA Thermal Resistance, Junction to Ambient OI Package TOP Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditions.. Tested to EIA/JED A A. Tested to EIA/JED A A. Tested to JED 0 A. Tested to EIA/JED8 /W REOMMEDED OPERATIG ODITIO ymbol haracteristics Min Max nit D upply oltage.. I D Input oltage 0. OT D Output oltage Output in tate igh or ow tate 0 T A Operating Temperature Range, all Package Types t r, t f Input Rise or Fall Time = ns/ DEIE JTIO TEMPERATRE ER TIME TO 0.% BOD FAIRE Junction Temperature Time, ours Time, Years 80,0, , , , ,000. 0, ,900.0 ORMAIZED FAIRE RATE FAIRE RATE OF PATI = ERAMI TI ITERMETAI OR TJ = 0 TJ = 0 TJ = 0 TJ = 00 TJ = 90 TJ = TIME, YEAR Figure. Failure Rate vs. Time Junction Temperature

4 MTA D ARATERITI (oltages Referenced to GD) T A = T A 8 T A ymbol Parameter ondition () Min Typ Max Min Max Min Max nit I Minimum igh evel Input. to 0.8 oltage. I O Maximum ow evel Input oltage Maximum igh evel Output oltage. to I = I or I I O = 0 A..... I = I or I I O = 8 ma O Maximum ow evel Output oltage I = I or I I O = 0 A I = I or I I O = 8 ma I I Input eakage urrent I =. or GD 0 to. ±0. ±.0 ±.0 A I I T Maximum Quiescent upply urrent Additional Quiescent upply urrent (per Pin) I = or GD A Any one input: I =. All other inputs: I = or GD.... A I OPD Output eakage urrent OT = A A EETRIA ARATERITI (Input t r = t f =.0ns) Î T A ÎÎ ÎÎ T A = Î T A = 8 ÎÎ ÎÎ Î ymbolîî Parameter Test onditions Min Typ ÎÎ Max ÎÎ Min Max Min MaxÎÎ nit t Î P, Maximum Propagation Delay; t P ÎÎ =. ± 0. = pf A to B to Y ÎÎ. ÎÎ.0 ÎÎ ÎÎ ns = 0pF ÎÎ =.0 ± 0. = pf ÎÎ = 0pF ÎÎ ÎÎ.. ÎÎ. 8. ÎÎ ÎÎ Î t P, ÎÎ Maximum Propagation Delay; =. ± 0. = pf t Î P to Y ÎÎ ÎÎ. ÎÎ. ÎÎ ÎÎ ns = 0pF ÎÎ ÎÎ =.0 ± 0. = pf = 0pF ÎÎ ÎÎ..8 ÎÎ ÎÎ ÎÎ Î t P, ÎÎ Maximum Propagation Delay; =. ± 0. = pf ÎÎ. ÎÎ. ÎÎ ÎÎ ns t Î P E to Y ÎÎ = 0pF ÎÎ =.0 ± 0. = pf = 0pF ÎÎ ÎÎ.. ÎÎ ÎÎ ÎÎ Maximum Input apacitanceîî ÎÎ 0 Î 0 ÎÎ 0 ÎÎ pf I PD Power Dissipation apacitance (ote ) =.0. PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I (OPR) = PD f in + I. PD is used to determine the no load dynamic power consumption; P D = PD f in + I. OIE ARATERITI (Input t r = t f =.0ns, = 0pF, =.0 ) ymbol haracteristic 0 T A = OP Quiet Output Maximum Dynamic O O Quiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage.0 ID Maximum ow evel Dynamic Input oltage 0.8 Typ Max pf nit

5 MTA A, B or 0% t P t P GD A, B or 0% t P t P GD Y 0% Y 0% Figure. witching Waveform Figure. Inverting witching TET POIT DEIE DER TET OTPT * IPT *Includes all probe and jig capacitance Figure. Test ircuit Figure 8. Input Equivalent ircuit ORDERIG IFORMATIO Device Package hipping MTAD OI 8 nits / Rail MTADG OI 8 nits / Rail MTADR OI 00 Tape & Reel MTADRG OI 00 Tape & Reel MTADT TOP * 9 nits / Rail MTADTG TOP * 9 nits / Rail MTADTR TOP * 00 Tape & Reel MTADTRG TOP * 00 Tape & Reel MTAM OEIAJ 0 nits / Rail MTAMG OEIAJ 0 nits / Rail MTAME OEIAJ 000 Tape & Reel MTAMEG OEIAJ 000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging pecifications Brochure, BRD80/D. *This package is inherently Pb Free.

6 MTA PAKAGE DIMEIO OI D FFIX AE B 0 IE J A 9 8 B P 8 P 0. (0.00) M B OTE:. DIMEIOIG AD TOERAIG PER AI Y.M, 98.. OTROIG DIMEIO: MIIMETER.. DIMEIO A AD B DO OT IDE MOD PROTRIO.. MAXIMM MOD PROTRIO 0. (0.00) PER IDE.. DIMEIO D DOE OT IDE DAMBAR PROTRIO. AOWABE DAMBAR PROTRIO A BE 0. (0.00) TOTA I EXE OF TE D DIMEIO AT MAXIMM MATERIA ODITIO. T EATIG PAE G K D P 0. (0.00) M T B A M R X J F MIIMETER IE DIM MI MAX MI MAX A B D F G. B 0.00 B J K M 0 0 P R TOP DT FFIX AE 98F 0 IE A 0. (0.00) T 0. (0.00) T 0.0 (0.00) T EATIG PAE PI IDET. D X / X K REF 0.0 (0.00) M T 9 8 A G B J J F DETAI E DETAI E K K ÇÇÇ ÉÉÉ ÇÇÇ ETIO 0. (0.00) M W OTE:. DIMEIOIG AD TOERAIG PER AI Y.M, 98.. OTROIG DIMEIO: MIIMETER.. DIMEIO A DOE OT IDE MOD FA. PROTRIO OR GATE BRR. MOD FA OR GATE BRR A OT EXEED 0. (0.00) PER IDE.. DIMEIO B DOE OT IDE ITEREAD FA OR PROTRIO. ITEREAD FA OR PROTRIO A OT EXEED 0. (0.00) PER IDE.. DIMEIO K DOE OT IDE DAMBAR PROTRIO. AOWABE DAMBAR PROTRIO A BE 0.08 (0.00) TOTA I EXE OF TE K DIMEIO AT MAXIMM MATERIA ODITIO.. TERMIA MBER ARE OW FOR REFEREE OY.. DIMEIO A AD B ARE TO BE DETERMIED AT DATM PAE W. MIIMETER IE DIM MI MAX MI MAX A B D F G 0. B 0.0 B J J K K B 0. B M

7 MTA PAKAGE DIMEIO OEIAJ M FFIX AE 9 0 IE A 0. (0.00) T 0. (0.00) T 0.0 (0.00) T EATIG PAE PI IDET. D X / X K REF 0.0 (0.00) M T 9 8 A G B J J F DETAI E DETAI E K K ÇÇÇ ÉÉÉ ETIO 0. (0.00) M W OTE:. DIMEIOIG AD TOERAIG PER AI Y.M, 98.. OTROIG DIMEIO: MIIMETER.. DIMEIO A DOE OT IDE MOD FA. PROTRIO OR GATE BRR. MOD FA OR GATE BRR A OT EXEED 0. (0.00) PER IDE.. DIMEIO B DOE OT IDE ITEREAD FA OR PROTRIO. ITEREAD FA OR PROTRIO A OT EXEED 0. (0.00) PER IDE.. DIMEIO K DOE OT IDE DAMBAR PROTRIO. AOWABE DAMBAR PROTRIO A BE 0.08 (0.00) TOTA I EXE OF TE K DIMEIO AT MAXIMM MATERIA ODITIO.. TERMIA MBER ARE OW FOR REFEREE OY.. DIMEIO A AD B ARE TO BE DETERMIED AT DATM PAE W. MIIMETER IE DIM MI MAX MI MAX A B D F G 0. B 0.0 B J J K K B 0. B M O emiconductor and are registered trademarks of emiconductor omponents Industries, (I). I reserves the right to make changes without further notice to any products herein. I makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does I assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in I data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. I does not convey any license under its patent rights nor the rights of others. I products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the I product could create a situation where personal injury or death may occur. hould Buyer purchase or use I products for any such unintended or unauthorized application, Buyer shall indemnify and hold I and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that I was negligent regarding the design or manufacture of the part. I is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PBIATIO ORDERIG IFORMATIO ITERATRE FFIMET: iterature Distribution enter for O emiconductor P.O. Box, Phoenix, Arizona 808 A Phone: or Toll Free A/anada Fax: or Toll Free A/anada orderlit@onsemi.com. American Technical upport: Toll Free A/anada Japan: O emiconductor, Japan ustomer Focus enter 9 Kamimeguro, Meguro ku, Tokyo, Japan 00 Phone: 8 80 O emiconductor Website: Order iterature: For additional information, please contact your local ales Representative. MTA/D

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