PCB Effects for Power Integrity

Transcription

1 PCB Effects for Power Integrity Bruce Archambeault, PhD IEEE Fellow, MST Adjunct Professor IBM Distinguished Engineer Emeritus

2 PCB Issues for Optimum Power Integrity Inductance dominates performance Which inductance? Under what circumstances? Effect of capacitance value Effect of number of capacitors Effect of capacitor density Effect of capacitor via configuration Case Study November 2016 Dr. Bruce Archambeault 2

3 Impedance at Port #1 Single 0.01 uf Capacitor at Various Distances (35mil Dielectric) Impedance (dbohms) no caps 300 mils 500 mils 700 mils 1000 mils E E E E+10 Frequency (Hz) November 2016 Dr. Bruce Archambeault 3

4 2 Z11 Phase Comparison as Capacitor distance Varies for 35 mils FR4 ESL = 0.5nH Phase (rad) mils 200 mils 300 mils 400 mils 1000 mils 2000 mils E E E E+09 Frequency (Hz) November 2016 Dr. Bruce Archambeault 4

5 Design Geometry, Current Path, and Z PDN Input Impedance at IC port [Ω] C = C + C eq 10 0 planes decoupling Step1-1 Capacitor Step2-19 Capacitors Step3-43 Capactors LIC + Lplanes + LDecaps + Mij L high November 2016 Frequency[GHz] 5

6 Model for Plane Recharge Investigations ε r = 4.5 b = 10 Port2 (4,5) Port3 (4,4.95) Cdec (4.05,5) Port1 (8,7) d = 35 mil a = 12 Vdc I input Decoupling Capacitor : C = 1uF ESR = 30mOhm ESL = 0.5nH DC voltage used to charge the power plane Port 2 represents IC current draw November 2016 Dr. Bruce Archambeault 6

7 Charge Between Planes vs.. Charge Drawn by IC Board total charge : C*V = 3.5nF*3.3V = 11nC Pulse charge 5A peak : I*dt/2 = (1ns*5A)/2=2.5nC November 2016 Dr. Bruce Archambeault 7

8 Triangular pulses (5 Amps Peak) November 2016 Dr. Bruce Archambeault 8

9 Charge Depletion vs. Capacitor Distance November 2016 Dr. Bruce Archambeault 9

10 Charge Depletion for 400 mils for Various connection Inductance November 2016 Dr. Bruce Archambeault 10

11 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=1uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =4.5 November 2016 Dr. Bruce Archambeault 11 12

12 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=0.5uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =4.5 November 2016 Dr. Bruce Archambeault 12 12

13 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=0.25uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =4.5 November 2016 Dr. Bruce Archambeault 13 12

14 Constant Capacitance 800 mil Distance November 2016 Dr. Bruce Archambeault 14

15 Constant Capacitance 800 mil Distance November 2016 Dr. Bruce Archambeault 15

16 Effect of Capacitor Value?? Need enough charge to supply need Depends on connection inductance November 2016 Dr. Bruce Archambeault 16

17 Noise Voltage is INDEPENDENT of Amount of Capacitance! Dist=400 mils ESR=30mOhms ESL=0.5nH As long as there is enough charge November 2016 Dr. Bruce Archambeault 17

18 What Happens if a 2 nd Decoupling Capacitor is placed near the First Via #1 Observation Point Capacitor? distance 500 mils Via #2 Moved in arc around Observation point while maintaining 500 mil distance to observation point November 2016 Dr. Bruce Archambeault 18

19 Second Via Around a circle d d Port = R ( x, y ) θ = 2 R sin 2 d 2 d 1 θ Port 2 Port 1 R R: distance between Port 1 and Port 2 in mil r: radius for all ports in mil d: thickness of dielectric layer in mil d1: distance between Port 3 and Port 1 in mil d2: distance between Port 2 and Port 3 in mil theta: angle as shown in the figure in degree 2 d1 + r 2 2 ln µ d ( R + r) ( d ) 1 + r µ d R + r ln 3 4π ( ) r d + r d + r 2 4π 2 ln r 4 ( R + r ) ( ) 2R sin( θ / 2) + r µ d ln 4 π r = 3 Courtesy of Jingook Kim, Jun Fan, Jim Drewniak Missouri University of Science and Technology November 2016 Dr. Bruce Archambeault 19

20 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Equal Distance Around Circle Plane Seperation = 35 mil -- Via Diameter = 20 mil Inductnace (ph) mil 500mil 750 mil 1000 mil Angle (degrees) November 2016 Dr. Bruce Archambeault 20

21 500 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Equal Distance Around Circle Plane Seperation = 10 mil -- Via Diameter = 20 mil Inductnace (ph) mil 250 mil 750 mil 1000 mil Angle (degrees) November 2016 Dr. Bruce Archambeault 21

22 Second Via Along Side R: distance between Port 1 and Port 2 in mil Port 3 ( x, y ) d 1 d 2 Port 1 R Port 2 r: radius for all ports in mil d: thickness of dielectric layer in mil d1: distance between Port 3 and Port 1 in mil d2: distance between Port 2 and Port 3 in mil = R d 2 d + November 2016 Dr. Bruce Archambeault 22

23 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Positioned Adjacent to First Capacitor Plane Seperation = 35 mil -- Via Diameter = 20 mil Inductnace (ph) mil 250 mil 750 mil 1000 mil Distance Between Capacitors (mils) November 2016 Dr. Bruce Archambeault 23

24 Understanding Inductance Effects and Proximity 1 via 2 via with degree 30 10cm 10mm 20cm 10cm 2 via with degree 90 2 via with degree cm November 2016 Dr. Bruce Archambeault 24

25 Current Density [m] [m] A/m 2 A/m 2 [m] [m] A/m 2 [m] [m] A/m 2 [m] [m] November 2016 Dr. Bruce Archambeault 25

26 DUT for Experimental Validation (Single Plane pair) 10cm Shorting via 1 shorting 10cm 2mm G-S probing port 0.8mm Short Vias Short Vias θ = 0,30, 180 G-S probing port 2 shorting with 30 2 shorting with 180 November 2016 Dr. Bruce Archambeault 26

27 Experimental Validation (Single Plane Pair) 10 Measured Input Impedance Impedance [Ω] 1 Total inductance [ph] Frequency [MHz] with only 1 via (852pH) with 2 vias with 30 (687pH) with 2 via with 180 (586H = 68.8% 852pH) Even in the case with two shorting vias at opposite sides (θ =180 ), the inductance value is 68.8% of that with one shorting via As two shorting vias get closer together, mutual inductance between two shorting vias increases. 4 ( R + r) ( ) 3 2R sin( θ / 2) + r µ d ln 4π r 500 November Dr. Bruce 250 Archambeault Equation 27 theta (degree)

28 Multiple Capacitors GND_cap PWR_cap Decaps Cavity1 GND PWR GND PWR Cavity2 Cavity3 GND PWR GND Cavity4 PWR November 2016 Dr. Bruce Archambeault 28

29 Via Spacing 9 mils 9 mils 20 mils 10 mils* 10 mils* Via Barrel 10 mils 60 mils 108 mils minimum 128 mils typical Distance to Planes (mils) 40 mil Spacing (nh) 0402 SMT (nh) 0603 SMT (nh) November 2016 Dr. Bruce Archambeault 29

30 0603 Size Cap Typical Mounting 9 mils 9 mils 20 mils 10 mils* 10 mils* Via Barrel 10 mils 60 mils 108 mils minimum 128 mils typical *Note: Minimum distance is 10 mils but more typical distance is 20 mils November 2016 Dr. Bruce Archambeault 30

31 Connection Inductance for Typical Capacitor Configurations Distance into board to planes (mils) 0805 typical/minimum (148 mils between via barrels) 0603 typical/minimu m (128 mils between via barrels) 0402 typical/minimum (106 mils between via barrels) nh 1.1 nh 0.9 nh nh 1.6 nh 1.3 nh nh 1.9 nh 1.6 nh nh 2.2 nh 1.9 nh nh 2.5 nh 2.1 nh nh 2.7 nh 2.3 nh nh 3.0 nh 2.6 nh nh 3.2 nh 2.8 nh nh 3.5 nh 3.0 nh nh 3.7 nh 3.2 nh November 2016 Dr. Bruce Archambeault 31

32 Connection Inductance for Typical Capacitor Configurations with 50 mils from Capacitor Pad to Via Pad Distance into board to planes (mils) 0805 (208 mils between via barrels) 0603 (188 mils between via barrels) 0402 (166 mils between via barrels) nh 1.6 nh 1.4 nh nh 2.3 nh 2.0 nh nh 2.8 nh 2.5 nh nh 3.2 nh 2.8 nh nh 3.5 nh 3.1 nh nh 3.9 nh 3.5 nh nh 4.2 nh 3.7 nh nh 4.5 nh 4.0 nh nh 4.7 nh 4.3 nh nh 5.0 nh 4.6 nh November 2016 Dr. Bruce Archambeault 32

33 Possible Configurations Dense, alternating Dense, nonalternating Spread, nonalternating Spread, alternating November 2016 Dr. Bruce Archambeault 33

34 120 Effective Inductance for 16 Decoupling Capacitors for Dense and Spread Configurations and Plane Pair Depth 100 Effective Inductance (ph) Dense Non-Alternating Dense Alternating Spread Non- Alternating Spread Alternating Distance into PCB (mils) 40 mil via spacing November 2016 Dr. Bruce Archambeault 34

35 L Decap Convergence Line G P Port Decaps modeled as a Short h Alternating 50 mils Regular 100 mils Ldecap Comparison h=5mils Line Alternating Line Regular 1/n 10-1 Ldecap Comparison h=5mils Line Alternating Line Regular 1/n [nh] [nh] Number of Capacitors Number of Capacitors November 2016 Dr. Bruce Archambeault 35

36 L Decap comparison (h=10mils, 0201) Alternating Regular Doublet GND GND Short Port 10mil LDecap vs # of Decaps, 0201 Regular Alternating Doublet 1/n LDecap vs # of Decaps, 0201 Regular Alternating Doublet 1/n L [n H ] L [n H ] # of Decaps November 2016 Dr. Bruce Archambeault 36 0 # of Decaps

37 L Decap comparison (h=10mils, 0402) Alternating Regular Doublet Short GND GND 10mil Port LDecap vs # of Decaps, 0402 Regular Alternating Doublet 1/n LDecap vs # of Decaps, 0402 Regular Alternating Doublet 1/n L [n H ] L [n H ] # of Decaps # of Decaps November 2016 Dr. Bruce Archambeault 37 0

38 L Decap comparison (h=10mils, 0603) Alternating Regular Doublet Short GND GND Port 10mil LDecap vs # of Decaps, 0603 Regular Alternating Doublet 1/n LDecap vs # of Decaps, 0603 Regular Alternating Doublet 1/n L [n H ] L [n H ] # of Decaps # of Decaps November 2016 Dr. Bruce Archambeault 38

39 L Decap comparison (h=10mils, 0805) Alternating Regular Doublet GND GND Short Port 10mil LDecap vs # of Decaps, 0805 Regular Alternating Doublet 1/n LDecap vs # of Decaps, 0805 Regular Alternating Doublet 1/n L [n H ] L [n H ] # of Decaps # of Decaps November 2016 Dr. Bruce Archambeault 39

40 Observations Added via (capacitor) does not lower effective inductance to 70-75% of original single via case Thicker dielectric results in higher inductance Alternating PWR/GND can significantly reduce overall inductance November 2016 Dr. Bruce Archambeault 40

41 Effect of Plane width on Inductance Case1 : 10 inches Case2 : 5 inches Case3 : 2 inches 1 inch Port1 Port2 November 2016 Dr. Bruce Archambeault 41

42 Geometry Solid Plane Capacitor Port IC Port (shorting via) width 10 inches Top View 12 inches IC Port (shorting via) 10 mils Capacitor Port Side View November 2016 Dr. Bruce Archambeault 42

43 Inductance as a Function of Plane Width Plane Width (inches) Inductance (ph) November 2016 Dr. Bruce Archambeault 43

44 Inductance as a Function of Plane Width Plane Width (inches) Inductance (ph) (Distance=10 ) Inductance (ph) (Distance=2 ) Inductance (ph) (Distance=1 ) November 2016 Dr. Bruce Archambeault 44

45 Plane Width & Current Density November 2016 Dr. Bruce Archambeault 45

46 Typical PCB Power Design November 2016 Dr. Bruce Archambeault 46

47 Another Example November 2016 Dr. Dr. Bruce Archambeault 47

48 Sharp Angles Cause Current Bunching (Increased Inductance) November 2016 Dr. Bruce Archambeault 48

49 Geometry for Case Studies Via Map 16 Capacitors are placed, to maintain the symmetry IC region 1.2 mil 1oz Cu Copper thickness 44 Layer 3 mil Dielectric thickness ~300 mils 0.6 mil 0.5oz 3.5 mil mil 1oz Cu 3 mil mil 0.5oz Cu 3.5 mil 100 mils Signal Net Location Reference Net Possible Power net Location 1.2 mil 1oz Cu November 2016 Dr. Bruce Archambeault 49 3 mil

50 Q1 & Q2. Location of Power Layer/Caps Top decaps only Power plane at mid Power plane at top IC 16 Decaps IC 16 Decaps Power plane at bottom IC 16 Decaps Bottom decaps only Away from the IC Bottom decaps only Under the IC IC IC IC 16 Decap 16 Decap IC IC IC 16 Decap 16 Decap 16 Decap Power Net under test Reference Net Floating Net 16 Decap 50

51 Ω PWR Layer Location Results Z 11 - Top Cap Power plane at Top Top Mid Bottom Power plane Middle Power plane Bottom Ω Z 11 - Bottom Caps - Under the IC Power plane at Top Top Mid Bottom Power plane Middle Power plane Bottom 10-4 Geometry and Currents [GHz] IC Top Cap Power layer [GHz] IC Geometry and Currents Power layer should be closest to the IC, to minimize IC to power plane inductance. November 2016 Dr. Bruce Archambeault Bottom Cap 51 Under the IC

52 Cap Location Effect - Results Z 11 - Top Pwr Top Cap Bottom Cap-Away Bottom Cap- Under the IC Z 11 - Middle PWR Top Cap Bottom Cap-Away Bottom Cap- Under the IC Ω Ω IC [GHz] Top Cap Power layer [GHz] The capacitors should to be placed on the side closest to the power plane to reduce the inductance from the capacitor to power plane. Capacitor location does not affect the high frequency inductance. November 2016 Bottom Cap Bottom Cap Dr. Bruce Archambeault 52 Under the IC Away from IC

53 Q3. Effect of Ground Planes Geometries IC IC Intermediate GND planes removed Intermediate GND planes removed All ground planes With top nearby ground plane IC IC With bottom nearby ground plane Intermediate GND planes removed Intermediate GND planes removed Intermediate GND planes removed Only topmost and bottommost ground planes November 2016 Dr. Bruce Archambeault 53

54 Effect of Ground Planes Results Z 11 - Top Cap All GND Planes Top Closest Bottom Closest Only Topmost & Bottommost IC Top Cap Ω 10-2 Geometry Power layer [GHz] Geometry and current path for no GND plane case Geometry and current path for all GND planes case The closest ground plane from the power plane, is most important. Other Ground planes in the stack up will not affect the L low or L high significantly. November 2016 Dr. Bruce Archambeault 54

55 Power Integrity Analysis Summary Physical cause of inductance (current path) identified for each portion of overall path Value of capacitance not as important as number of capacitors Via connection configuration can dramatically influence inductance If power/ground-reference planes deep in PCB stackup, capacitor placement has less impact than might be expected November 2016 Dr. Bruce Archambeault 55

56 Design Conclusions PWR/GND plane pair close to IC minimizes L IC Capacitors close to the power layer minimize the inductance L decap from the capacitor to the power plane. PWR/GND plane separation small Placing Caps under the IC can benefit the design, if board is thin, or the plane inductance is large. Ground plane closest to the power layer affects the response most, all other ground layer have very little influence. November 2016 Dr. Bruce Archambeault 56