PCB Effects for Power Integrity

Transcription

1 PCB Effects for Power Integrity Bruce Archambeault, PhD IEEE Fellow, MST Adjunct Professor IBM Distinguished Engineer Emeritus

2 PCB Issues for Optimum Power Integrity Inductance dominates performance Which inductance? Under what circumstances? Effect of capacitance value Effect of number of capacitors Effect of capacitor density Effect of capacitor via configuration Case Study 2

3 Design Geometry, Current Path, and Z PDN Input Impedance at IC port [Ω] C = C + C eq 10 0 planes decoupling Step1-1 Capacitor Step2-19 Capacitors Step3-43 Capactors LIC + Lplanes + LDecaps + Mij L high Frequency[GHz] 3 3

4 Model for Plane Recharge Investigations ε r = 4.5 b = 10 Port2 (4,5) Port3 (4,4.95) Cdec (4.05,5) Port1 (8,7) d = 35 mil a = 12 Vdc I input Decoupling Capacitor : C = 1uF ESR = 30mOhm ESL = 0.5nH DC voltage used to charge the power plane Port 2 represents IC current draw 4

5 Charge Between Planes vs.. Charge Drawn by IC Board total charge : C*V = 3.5nF*3.3V = 11nC Pulse charge 5A peak : I*dt/2 = (1ns*5A)/2=2.5nC 5

6 Triangular pulses (5 Amps Peak) 6

7 Charge Depletion vs. Capacitor Distance 7

8 Charge Depletion for 400 mils for Various connection Inductance 8

9 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=1uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =

10 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=0.5uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =

11 Effect of Multiple Capacitors While Keeping Total Capacitance Constant The decap locations are 800mils from the power pin (power-ground pins at IC center) C=0.25uF ESL=0.5nH ESR=1Ω Decap Port1 (8,7) (Ls 50nH) 10 1 inch Ground pin Port2 (4,5) (power pin) εr =

12 Constant Capacitance 800 mil Distance 12

13 Constant Capacitance 800 mil Distance 13

14 Effect of Capacitor Value?? Need enough charge to supply need Depends on connection inductance 14

15 Noise Voltage is INDEPENDENT of Amount of Capacitance! Dist=400 mils ESR=30mOhms ESL=0.5nH As long as there is enough charge 15

16 What Happens if a 2 nd Decoupling Capacitor is placed near the First Via #1 Observation Point Capacitor? distance 500 mils Via #2 Moved in arc around Observation point while maintaining 500 mil distance to observation point 16

17 Second Via Around a circle d d Port = R ( x, y ) θ = 2 R sin 2 d 2 d 1 θ Port 2 Port 1 R R: distance between Port 1 and Port 2 in mil r: radius for all ports in mil d: thickness of dielectric layer in mil d1: distance between Port 3 and Port 1 in mil d2: distance between Port 2 and Port 3 in mil theta: angle as shown in the figure in degree 2 d1 + r 2 2 ln µ d ( R + r) ( d ) 1 + r µ d R + r ln 3 4π ( ) r d + r d + r 2 4π 2 ln r 4 ( R + r ) ( ) 2R sin( θ / 2) + r µ d ln 4 π r = 3 Courtesy of Jingook Kim, Jun Fan, Jim Drewniak Missouri University of Science and Technology 17

18 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Equal Distance Around Circle Plane Seperation = 35 mil -- Via Diameter = 20 mil Inductnace (ph) mil 500mil 750 mil 1000 mil Angle (degrees) 18

19 500 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Equal Distance Around Circle Plane Seperation = 10 mil -- Via Diameter = 20 mil Inductnace (ph) mil 250 mil 750 mil 1000 mil Angle (degrees) 19

20 Second Via Along Side R: distance between Port 1 and Port 2 in mil Port 3 ( x, y ) d 1 d 2 Port 1 R Port 2 r: radius for all ports in mil d: thickness of dielectric layer in mil d1: distance between Port 3 and Port 1 in mil d2: distance between Port 2 and Port 3 in mil = R d 2 d + 20

21 Effective Inductance for Various Distances to Decoupling Capacitor With Second Capacitor (Via) Positioned Adjacent to First Capacitor Plane Seperation = 35 mil -- Via Diameter = 20 mil Inductnace (ph) mil 250 mil 750 mil 1000 mil Distance Between Capacitors (mils) 21

22 Understanding Inductance Effects and Proximity 1 via 2 via with degree 30 10cm 10mm 20cm 10cm 2 via with degree 90 2 via with degree cm 22

23 Current Density [m] [m] A/m 2 A/m 2 [m] [m] A/m 2 [m] [m] A/m 2 [m] [m] 23

24 DUT for Experimental Validation (Single Plane pair) 10cm Shorting via 1 shorting 10cm 2mm G-S probing port 0.8mm Short Vias Short Vias θ = 0,30, 180 G-S probing port 2 shorting with 30 2 shorting with

25 Experimental Validation (Single Plane Pair) 10 Measured Input Impedance Impedance [Ω] 1 Total inductance [ph] Frequency [MHz] with only 1 via (852pH) with 2 vias with 30 (687pH) with 2 via with 180 (586H = 68.8% 852pH) theta (degree) Even in the case with two shorting vias at opposite sides (θ =180 ), the inductance value is 68.8% of that with one shorting via As two shorting vias get closer together, mutual inductance between two shorting vias increases. ( ) ( ) 3 4 µ d R + r ln 4π 2R sin( θ / 2) + r r Equation 25

26 Multiple Capacitors GND_cap PWR_cap Decaps Cavity1 GND PWR GND PWR Cavity2 Cavity3 GND PWR GND Cavity4 PWR 26

27 Via Spacing 9 mils 9 mils 20 mils 10 mils* 10 mils* Via Barrel 10 mils 60 mils 108 mils minimum 128 mils typical Distance to Planes (mils) 40 mil Spacing (nh) 0402 SMT (nh) 0603 SMT (nh)

28 Possible Configurations Dense, alternating Dense, nonalternating Spread, nonalternating Spread, alternating 28

29 120 Effective Inductance for 16 Decoupling Capacitors for Dense and Spread Configurations and Plane Pair Depth 100 Effective Inductance (ph) Dense Non-Alternating Dense Alternating Spread Non- Alternating Spread Alternating Distance into PCB (mils) 40 mil via spacing 29

30 [nh] Line L Decap Convergence G P Ldecap Comparison h=5mils Port Line Alternating Line Regular 1/n Decaps modeled as a Short [nh] h Alternating 50 mils Regular 100 mils Ldecap Comparison h=5mils Line Alternating Line Regular 1/n Number of Capacitors Number of Capacitors 30

31 G P L Decap Convergence 0402 Size Line Port Alternating h=5mils Decaps modeled as a Short [nh] 50 mils Regular 100 mils Line Horizontal Ldecap Comparison h=5mils Line Vertical a 10-3 Convention Alternating Convention Regular Line Horizontal Line Vertical 10 1 Number of Capacitors 31

32 G P L Decap Convergence 0402 Size Line Port h=5mils Decaps modeled as a Short Alternating [nh] 50 mils Regular 100 mils Line Horizontal Ldecap Comparison h=5mils Line Vertical Convention Alternating Convention Regular Line Horizontal Line Vertical a Number of Capacitors 32

33 Observations Added via (capacitor) does not lower effective inductance to 70-75% of original single via case Thicker dielectric results in higher inductance Alternating PWR/GND can significantly reduce overall inductance 33

34 Effect of Plane width on Inductance Case1 : 10 inches Case2 : 5 inches Case3 : 2 inches 1 inch Port1 Port2 34

35 Geometry Solid Plane Capacitor Port IC Port (shorting via) width 10 inches Top View 12 inches IC Port (shorting via) Capacitor Port Side View 10 mils 35

36 Inductance as a Function of Plane Width Plane Width (inches) Inductance (ph)

37 Inductance as a Function of Plane Width Plane Width (inches) Inductance (ph) (Distance=10 ) Inductance (ph) (Distance=2 ) Inductance (ph) (Distance=1 )

38 Plane Width & Current Density 38

39 Geometry for Case Studies Via Map 16 Capacitors are placed, to maintain the symmetry IC region 1.2 mil 1oz Cu Copper thickness 44 Layer 3 mil Dielectric thickness ~300 mils 0.6 mil 0.5oz 3.5 mil mil 1oz Cu 3 mil mil 0.5oz Cu 3.5 mil 100 mils Signal Net Location Reference Net Possible Power net Location 1.2 mil 1oz Cu 3 mil 39

40 Q1 & Q2. Location of Power Layer/Caps Top decaps only Power plane at mid Power plane at top IC 16 Decaps IC 16 Decaps Power plane at bottom IC 16 Decaps Bottom decaps only Away from the IC Bottom decaps only Under the IC IC IC IC 16 Decap 16 Decap IC IC IC 16 Decap 16 Decap 16 Decap Power Net under test Reference Net Floating Net 16 Decap 40 40

41 Ω PWR Layer Location Results Z 11 - Top Cap Power plane at Top Top Mid Bottom Power plane Middle Power plane Bottom Ω Z 11 - Bottom Caps - Under the IC Power plane at Top Top Mid Bottom Power plane Middle Power plane Bottom 10-4 Geometry and Currents [GHz] IC Top Cap Power layer [GHz] IC Geometry and Currents Power layer should be closest to the IC, to minimize IC to power plane inductance. Bottom Cap Under the IC 41

42 Cap Location Effect - Results Z 11 - Top Pwr Top Cap Bottom Cap-Away Bottom Cap- Under the IC Z 11 - Middle PWR Top Cap Bottom Cap-Away Bottom Cap- Under the IC Ω Ω IC [GHz] Top Cap Power layer [GHz] The capacitors should to be placed on the side closest to the power plane to reduce the inductance from the capacitor to power plane. Capacitor location does not affect the high frequency inductance. Bottom Cap Under the IC Bottom Cap Away from IC 42

43 Q3. Effect of Ground Planes Geometries IC IC Intermediate GND planes removed Intermediate GND planes removed All ground planes With top nearby ground plane IC IC With bottom nearby ground plane Intermediate GND planes removed Intermediate GND planes removed Intermediate GND planes removed Only topmost and bottommost ground planes 43 43

44 Effect of Ground Planes Results Z 11 - Top Cap All GND Planes Top Closest Bottom Closest Only Topmost & Bottommost IC Top Cap Ω 10-2 Geometry Power layer [GHz] Geometry and current path for no GND plane case Geometry and current path for all GND planes case The closest ground plane from the power plane, is most important. Other Ground planes in the stack up will not affect the L low or L high significantly. 44

45 Power Integrity Analysis Summary Physical cause of inductance (current path) identified for each portion of overall path Value of capacitance not as important as number of capacitors Via connection configuration can dramatically influence inductance If power/ground-reference planes deep in PCB stackup, capacitor placement has less impact than might be expected 45

46 Design Conclusions PWR/GND plane pair close to IC minimizes L IC Capacitors close to the power layer minimize the inductance L decap from the capacitor to the power plane. PWR/GND plane separation small Placing Caps under the IC can benefit the design, if board is thin, or the plane inductance is large. Ground plane closest to the power layer affects the response most, all other ground layer have very little influence. Ground vias for power return currents placed adjacent to the ground terminal of the capacitors reduces the inductance in the current return path 46