ENGR-4300 Electronic Instrumentation Fall 2000

Transcription

1 ENGR-400 Electronic Instrumentation Fall 000 Questions about Logic Gates Fall 004 Question : NAND Gate Circuit (6 points) Below is a picture of a series of NAND gates hooked together to form one of the basic gates we have studied and the PSpice output for the circuit OFFTIME = 0.5u DSTM ONTIME =.5uS CLK DELAY = 0 STARTAL = 0 OPPAL = A U0A C UA E U4A G OFFTIME = us DSTM ONTIME = us CLK DELAY = 0 STARTAL = 0 OPPAL = B UA D F U5A U6A a) Fill in the truth table for the circuit (0 points) A B C D E F G b) This circuit is a model for one of the gates we have seen in class. What single gate does it represent ( points)? c) Write a boolean expression for this circuit. Do not simplify. (4 points) K. A. Connor Revised: /0/005

2 ENGR-400 Electronic Instrumentation Fall 000 Fall 004 Solution (not available) K. A. Connor Revised: /0/005

3 ENGR-400 Electronic Instrumentation Fall 000 Spring 004 Question Logic Gates (0 points) a) Fill in the truth table for the circuit above: ( points) A B C D E F G H Q b) Write the Boolean expression for the circuit in a). Do not simplify. (6 points) c) What type of gate could the above circuit be replaced with to give the same results for Q based on A, B and C? ( points) ) Three input AND gate ) Three input OR gate ) Three input NOR gate 4) Three input NAND gate 5) none of the above K. A. Connor Revised: /0/005

4 ENGR-400 Electronic Instrumentation Fall 000 Extra credit ( point): Simplify the Boolean expression in b) using the rules of Boolean algebra on your crib sheet. K. A. Connor 4 Revised: /0/005

5 ENGR-400 Electronic Instrumentation Fall 000 Spring 004 solution Question Logic Gates (0 points) b) Fill in the truth table for the circuit above: ( points) A B C D E F G H Q b) Write the Boolean expression for the circuit in a). Do not simplify. (6 points) Q = ~{G + H} = ~{~F + (F&E)} = ~{~~(D+E) + (~(D+E)&E)} G = ~F H=F&E F=~(D+E) E= ~(B&C) D=~(A&B) Q = ~{ [ ~~(~(A&B) + ~(B&C))] + [~(~(A&B)+~(B&C)) & ~(B&C)] } c) What type of gate could the above circuit be replaced with to give the same results for Q based on A, B and C? ( points) ) Three input AND gate ) Three input OR gate ) Three input NOR gate K. A. Connor 5 Revised: /0/005

6 ENGR-400 Electronic Instrumentation Fall 000 4) Three input NAND gate 5) none of the above Extra credit ( point): Simplify the Boolean expression in b) using the rules of Boolean algebra on your crib sheet. expression rule Q=~{[ ~~(~(A&B) + ~(B&C))] + [~(~(A&B)+~(B&C)) & ~(B&C)]} given Q=~{[(~A&B) + ~(B&C)] + [~(~(A&B)+~(B&C)) & ~(B&C)]} ~~X = X Q=~{~[(A&B) & (B&C)] + [~~(A&B & B&C)) & ~(B&C)]} ~X&~Y=~(X&Y) Q=~{~[A&B&B&C] + [(A&B&B&C) & ~(B&C)]} ~~X = X Q=~{~[A&B&C] + [(A & (B&C) & ~(B&C)]} X&X=X Q=~{~[A&B&C] +[A&0]} X&~X=0 Q=~{~{A&B&C] + 0 } X&0=0 Q=~~{A&B&C} X+0=X Q= A&B&C ~~X=X QED K. A. Connor 6 Revised: /0/005

7 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Question Logic Gates (0 points) a) Match the gate on the left with an equivalent circuit on the right. (0 points) K. A. Connor 7 Revised: /0/005

8 ENGR-400 Electronic Instrumentation Fall 000 b) Fill in the truth table for the circuit below. (6 points) A B UA:Y UA:Y UA:Y Q c) Write the Boolean expression for the circuit in b. Do not simplify. (4 points) Extra credit ( point): Simplify the Boolean expression in c) using the rules of Boolean algebra on your crib sheet. K. A. Connor 8 Revised: /0/005

9 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Solution Question Logic Gates (0 points) a) Match the gate on the left with an equivalent circuit on the right. (0 points) A= B= C=5 D=4 E= and 5 are DeMorgan s Laws is ~(A and A) = ~A ~(A or A) = ~A too is ~(~A or ~B) = ~~(A and B) by DeMorgan s Law = (A and B) 4 is ~(~A and ~B) = ~~(A or B) by Demorgan s Law = (A or B) K. A. Connor 9 Revised: /0/005

10 ENGR-400 Electronic Instrumentation Fall 000 b) Fill in the truth table for the circuit below. (6 points) A B UA:Y UA:Y UA:Y Q c) Write the Boolean expression for the circuit in b. Do not simplify. (4 points) {( ) [ ( )] } A A + B A A Q = ( Extra credit ( point): Simplify the Boolean expression in c) using the rules of Boolean algebra on your crib sheet. Q = Q Q Q Q = = = = Q = {( ) [ ( )] } A A + ( B A A {( ) [ ( )] A + A + ( B A + A } {( A + A) + [( B ( A + A) ]} { + [( B ) ]} { + B} From DeMorgan' s Law X = part c) X X + X = X = X X + = K. A. Connor 0 Revised: /0/005

11 ENGR-400 Electronic Instrumentation Fall 000 Spring 00 Question ) Logic Gates (0 pts) a) In the circuit above, form the truth table for all marked points. ( pts each) A B C D E F G H I J b) Based on the truth table you formed, write a Boolean expression for D as a function of A. ( pt) c) Based on the truth table you formed, write a Boolean expression for H as a function of D and E. Your answer should involve only one gate operation. ( pts) d) Based on the truth table you formed, write a Boolean expression for J as a function of A, B and C. Your answer should involve only one gate operation. ( pts) K. A. Connor Revised: /0/005

12 ENGR-400 Electronic Instrumentation Fall 000 Spring 00 solution (not available) K. A. Connor Revised: /0/005

13 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Question ) NAND Gate Circuit (5 points) Below is a picture of a series of NAND gates hooked together to form one of the basic gates we have studied and the PSpice output for the circuit. OFFTIME = us DSTM ONTIME = us CLK DELAY = 0 STARTAL = 0 OPPAL = OFFTIME =.5us DSTM ONTIME =.5us CLK DELAY = 0 STARTAL = 0 OPPAL = A B UA C UA UA E D U4A F UA:A DSTM: UA:A UA:Y UA:Y U4A:Y 0s.0us 4.0us 6.0us 8.0us Time a) Fill in the truth table for the circuit (9 pts). A B C D E F b) What gate does this represent ( pts)? c) Write a boolean expression for this circuit. Do not simplify. (4 pts). K. A. Connor Revised: /0/005

14 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Solution Question ) NAND Gate Circuit (5 points) Below is a picture of a series of NAND gates hooked together to form one of the basic gates we have studied and the PSpice output for the circuit. OFFTIME = us DSTM ONTIME = us CLK DELAY = 0 STARTAL = 0 OPPAL = OFFTIME =.5us DSTM ONTIME =.5us CLK DELAY = 0 STARTAL = 0 OPPAL = A B UA C UA UA E D U4A F UA:A DSTM: UA:A UA:Y UA:Y U4A:Y 0s.0us 4.0us 6.0us 8.0us Time a) Fill in the truth table for the circuit (9 pts). A B C D E F b) What gate does this represent ( pts)? XOR a) Write a boolean expression for this circuit. Do not simplify. (4 pts). [( A B) A] [( A B) B] K. A. Connor 4 Revised: /0/005

15 ENGR-400 Electronic Instrumentation Fall 000 Spring 00 ) Logic Gates (0 points) You should recognize the digital gates in the following circuit as the ones introduced in the lab and/or in class. a) What kind of gate is UA? ( points) b) What is the truth table for gate UA? (6 points) c) Indicate which of the three plots on the following page represents the output of the circuit. Show any work below for partial credit. ( points) K. A. Connor 5 Revised: /0/005

16 ENGR-400 Electronic Instrumentation Fall 000 Circuits for question part c). A. DSTM: UA:Y UA:Y UA:B B. 0s us 4us 6us 8us 0us Time DSTM: UA:Y UA:Y UA:B 0s us 4us 6us 8us 0us Time C. DSTM: UA:A UA:B UA:Y 0s us 4us 6us 8us 0us Time K. A. Connor 6 Revised: /0/005

17 ENGR-400 Electronic Instrumentation Fall 000 ) Logic Gates (0 points) You should recognize the digital gates in the following circuit as the ones introduced in the lab and/or in class. a) What kind of gate is UA? ( points) Answer: UA is a three input NOR gate b) What is the truth table for gate UA? (6 points) Answer: A B C Y c) Indicate which of the three plots on the following page represents the output of the circuit. Show any work below for partial credit. ( points) work: DSTM UA:Y U5A:Y UA:Y UA:Y Note: UA:B is the same as UA:Y K. A. Connor 7 Revised: /0/005

18 ENGR-400 Electronic Instrumentation Fall 000 Circuits for question part c). A. DSTM: UA:Y UA:Y UA:B 0s us 4us 6us 8us 0us Time B. Answer: This one is CORRECT. DSTM: UA:Y UA:Y UA:B C. DSTM: UA:A UA:B UA:Y 0s us 4us 6us 8us 0us Time 0s us 4us 6us 8us 0us Time K. A. Connor 8 Revised: /0/005

19 ENGR-400 Electronic Instrumentation Fall 000 ) NAND Gate Circuits (0 points) It is possible to configure all standard gates using just NAND gates. The figure below show one such combination of NANDS. Clock OFFTIME =.5u DSTM ONTIME =.5u CLK DELAY = 0 STARTAL = 0 OPPAL = Clock OFFTIME =.5uS DSTM ONTIME =.5uS CLK DELAY = 0 STARTAL = 0 OPPAL = A B UA UA C D a. On the following plot, identify which signal goes with which location (6 points). UA E U4A F b. Draw a truth table for the circuit, showing the inputs, the output and as many steps in between as you need to determine how it works (0 points). c. Which single type of gate is this circuit equivalent to (4 points)? K. A. Connor 9 Revised: /0/005

20 ENGR-400 Electronic Instrumentation Fall 000 ) NAND Gate Circuits (0 points) It is possible to configure all standard gates using just NAND gates. The figure below show one such combination of NANDS. Clock OFFTIME =.5u DSTM ONTIME =.5u CLK DELAY = 0 STARTAL = 0 OPPAL = Clock OFFTIME =.5uS DSTM ONTIME =.5uS CLK DELAY = 0 STARTAL = 0 OPPAL = A B UA UA C D a. On the following plot, identify which signal goes with which location (6 points). UA E U4A F Answer: order from top to bottom: F,A,B,C,D,E b. Draw a truth table for the circuit, showing the inputs, the output and as many steps in between as you need to determine how it works (0 points). Answer: A B C D E F c. Which single type of gate is this circuit equivalent to (4 points)? Answer: two input NOR gate K. A. Connor 0 Revised: /0/005

21 ENGR-400 Electronic Instrumentation Fall 000 ) Combinational Logic (0 points) Draw the truth table for the circuit above: A B C D E F G H I Q K. A. Connor Revised: /0/005

22 ENGR-400 Electronic Instrumentation Fall 000 ) Combinational Logic (0 points) Draw the truth table for the circuit above: Answer: A B C D E F G H I Q K. A. Connor Revised: /0/005

23 ENGR-400 Electronic Instrumentation Fall 000 Spring 00 Sample Question: Boolean Algebra It is possible to configure all standard gates using just NAND gates. The figure below show one such combination of NANDS. Clock OFFTIME =.5u A DSTM UA ONTIME =.5u C CLK DELAY = 0 STARTAL = 0 OPPAL = UA E U4A F Clock OFFTIME =.5uS DSTM ONTIME =.5uS CLK DELAY = 0 STARTAL = 0 OPPAL = B UA D a. Identify which trace belongs to which point in the circuit. b. Write a boolean expression for this circuit (Do not simplify). K. A. Connor Revised: /0/005

24 ENGR-400 Electronic Instrumentation Fall 000 a. Properties of b. Rules of Combination c. DeMorgan s Laws Operations (a) A ٠ 0 = 0 (b) A ٠ B = B ٠ A (c) ~(A ٠ B) = ~A + ~B (a) A + 0 = A (b) A + B = B + A (c) ~(A + B) = ~A ٠ ~B (a) A ٠ = A (b) A ٠ (B+C) = (A٠B) + (A٠C) (a4) A + = (b4) A ٠ (B٠C) = (A٠B) ٠ C d. Other Rules (a5) A ٠ A = A (b5) A + (B+C) = (A+B) + C (d)a B = ~A٠B + A٠~B (a6) A + A = A (b6) A + (A٠B) = A (d)a XOR B = ~AandB + Aand~B (a7) A ٠ ~A = 0 (b7) A ٠ (A+B) = A (d) ~(A B) = ~A٠~B + A٠B (a8) A + ~A = (b8) A ٠ (~A + B) = A ٠ B (d) ~(A XOR B) = ~Aand~B + AandB (a9) ~(~A) = A (b9) A + (~A ٠ B) = A + B (b0) ~A + (A ٠ B) = ~A + B (b) ~A + (A ٠ ~B) = ~A + ~B Note that the NOT operation is indicated here by ~ instead of as a bar over the letter. You are free to use either notation. You can indicate the rule by the letter. [Note to students: Unfortunately, the PDF writer has trouble with the symbol font. In the above chart, the? in sections a, b and c are AND symbols and the meaning of the? in section d can be found in the restatement of the rule.] c. Using the Boolean Algebra rules shown above, prove that this combination of gates works as a NOR gate. K. A. Connor 4 Revised: /0/005

25 ENGR-400 Electronic Instrumentation Fall 000 Spring 00 solution Sample Question: Boolean Algebra ** ANSWER ** It is possible to configure all standard gates using just NAND gates. The figure below show one such combination of NANDS. Clock OFFTIME =.5u A DSTM UA ONTIME =.5u C CLK DELAY = 0 STARTAL = 0 OPPAL = UA E U4A F Clock OFFTIME =.5uS DSTM ONTIME =.5uS CLK DELAY = 0 STARTAL = 0 OPPAL = B UA D a. Identify which trace belongs to which point in the circuit. A = Clock; B=Clock; C = ~A = X; D = ~B = Y; E = ~(XandY) = Z; F=~E=W b) Write a boolean expression for this circuit (Do not simplify). F = ~[~( ~A and ~B )] K. A. Connor 5 Revised: /0/005

26 ENGR-400 Electronic Instrumentation Fall 000 a. Properties of b. Rules of Combination c. DeMorgan s Laws Operations (a) A ٠ 0 = 0 (b) A ٠ B = B ٠ A (c) ~(A ٠ B) = ~A + ~B (a) A + 0 = A (b) A + B = B + A (c) ~(A + B) = ~A ٠ ~B (a) A ٠ = A (b) A ٠ (B+C) = (A٠B) + (A٠C) (a4) A + = (b4) A ٠ (B٠C) = (A٠B) ٠ C d. Other Rules (a5) A ٠ A = A (b5) A + (B+C) = (A+B) + C (d)a B = ~A٠B + A٠~B (a6) A + A = A (b6) A + (A٠B) = A (d)a XOR B = ~AandB + Aand~B (a7) A ٠ ~A = 0 (b7) A ٠ (A+B) = A (d) ~(A B) = ~A٠~B + A٠B (a8) A + ~A = (b8) A ٠ (~A + B) = A ٠ B (d) ~(A XOR B) = ~Aand~B + AandB (a9) ~(~A) = A (b9) A + (~A ٠ B) = A + B (b0) ~A + (A ٠ B) = ~A + B (b) ~A + (A ٠ ~B) = ~A + ~B Note that the NOT operation is indicated here by ~ instead of as a bar over the letter. You are free to use either notation. You can indicate the rule by the letter. [Note to students: Unfortunately, the PDF writer has trouble with the symbol font. In the above chart, the? in sections a, b and c are AND symbols and the meaning of the? in section d can be found in the restatement of the rule.] c. Using the Boolean Algebra rules shown above, prove that this combination of gates works as a NOR gate. F = ~[~(~A and ~B)] F = ~A and ~B F = ~ (A or B) given rule a9 rule c This is a NOR gate. K. A. Connor 6 Revised: /0/005

27 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Solution K. A. Connor 7 Revised: /0/005

28 ENGR-400 Electronic Instrumentation Fall 000 K. A. Connor 8 Revised: /0/005

29 ENGR-400 Electronic Instrumentation Fall 000 K. A. Connor 9 Revised: /0/005

30 ENGR-400 Electronic Instrumentation Fall 000 K. A. Connor 0 Revised: /0/005

31 ENGR-400 Electronic Instrumentation Fall 000 Fall 000. Logic Gates You should recognize the logic gates in the figure below as those used in part of Experiment 0. If you performed the same kind of experiment as you did when you tested the gates on the protoboard, which of the following three figures is correct for the inputs shown? The digital clock represents the function generator and the other inputs are DC values obtained by connecting to the ground and CC rails on the protoboard. UA 740 DSTM CLK UA 740 5v R k 0 UA 7404 K. A. Connor Revised: /0/005

32 ENGR-400 Electronic Instrumentation Fall 000 DSTM: UA:Y UA:Y UA:Y 0s.0us.0us.0us 4.0us 5.0us Time UA:Y UA:Y UA:Y DSTM: 0s.0us.0us.0us 4.0us 5.0us Time DSTM: UA:Y UA:Y UA:Y 0s.0us.0us.0us 4.0us 5.0us Time K. A. Connor Revised: /0/005

33 ENGR-400 Electronic Instrumentation Fall 000 Fall 00 Solution:. Logic Gates You should recognize the logic gates in the figure below as those used in part of Experiment 0. If you performed the same kind of experiment as you did when you tested the gates on the protoboard, which of the following three figures is correct for the inputs shown? The digital clock represents the function generator and the other inputs are DC values obtained by connecting to the ground and CC rails on the protoboard. UA 740 DSTM CLK UA 740 5v R k 0 UA 7404 work: DSTM UA:Y UA:Y UA:Y K. A. Connor Revised: /0/005

34 ENGR-400 Electronic Instrumentation Fall 000 DSTM: UA:Y UA:Y UA:Y UA:Y UA:Y UA:Y DSTM: 0s.0us.0us.0us 4.0us 5.0us Time Answer: The one below is correct. 0s.0us.0us.0us 4.0us 5.0us Time DSTM: UA:Y UA:Y UA:Y 0s.0us.0us.0us 4.0us 5.0us Time K. A. Connor 4 Revised: /0/005

35 ENGR-400 Electronic Instrumentation Fall 000 Fall 000. Combinational Logic A UA 7404 UA U5A UA U6A Q B U4A 74 Which of the following truth tables is correct for this circuit? A B Q A B Q A B Q A B Q A B Q A B Q A B Q A B Q K. A. Connor 5 Revised: /0/005

36 ENGR-400 Electronic Instrumentation Fall 000 Fall 000 solution. Combinational Logic A UA 7404 UA U5A UA U6A Q B U4A 74 Which of the following truth tables is correct for this circuit? A B UA:Y UA:Y UA:Y U5A:Y U4A:Y U6A:Y Answer: the one below is correct A B Q A B Q A B Q A B Q A B Q A B Q A B Q A B Q K. A. Connor 6 Revised: /0/005

37 ENGR-400 Electronic Instrumentation Fall 000 Fall NAND Gate Circuits It is possible to configure all standard gates using just NAND gates. The figure below shows one such combination of NANDs. There are six voltages displayed on the transient voltage plot below. Identify which signal goes with which location. See if you can identify what the overall circuit is equivalent to. (You might want to construct the truth table for this purpose.) Remember that each standard gate comes in two forms, one that performs a particular logical function and one that performs the complement of (or NOT the) function. DSTM CLK DSTM CLK A B UA UA C D UA E U4A Q DSTM: DSTM: UA:Y UA:Y UA:Y U4A:Y 0s.0us.0us.0us 4.0us Time K. A. Connor 7 Revised: /0/005

38 ENGR-400 Electronic Instrumentation Fall 000 Fall 000 Solution 4. NAND Gate Circuits It is possible to configure all standard gates using just NAND gates. The figure below shows one such combination of NANDs. There are six voltages displayed on the transient voltage plot below. Identify which signal goes with which location. See if you can identify what the overall circuit is equivalent to. (You might want to construct the truth table for this purpose.) Remember that each standard gate comes in two forms, one that performs a particular logical function and one that performs the complement of (or NOT the) function. DSTM CLK DSTM CLK A B UA UA C D UA E U4A Q DSTM: DSTM: UA:Y UA:Y UA:Y U4A:Y 0s.0us.0us.0us 4.0us Time Answer : Method - Truth Table DSTM(A) DSTM(B) UA:Y(C) UA:Y(D) UA:Y(E) U4A:Y(Q) This is a NOR GATE Answer: Method Boolean Algebra A B = A B = A + B NOR GATE ~ ~ (~A ~B) = (~A ~B) = ~(A+B) NOR GATE K. A. Connor 8 Revised: /0/005