Digitalteknik EIT020. Lecture 10: Kanaugh Maps
|
|
|
- Chloe Edwards
- 6 years ago
- Views:
Transcription
1 Digitalteknik EIT020 Lecture 10: Kanaugh Maps October 2, 2015
2 Note regarding notation Some notation in the Compendium has changed from older versions. Normal forms for Boolean functions DNF (Disjunctive normal form) CNF (Conjunctive normal form) Reed-Muller Canonical Form (RMF) = Ring-Sum Expansion (RSE) = Algebraic Normal Form (ANF), Digitalteknik L10:2, Ch 5.1.2
3 Idea of minimisation Theorem There exists a prime cover that is a minimal cover. Minimal prime cover Find all prime implicants. Find the essential prime implicants. These must be part of a minimal prime cover a part of on-set. Cover the rest of on-set with a minmal number of prime implicants., Digitalteknik L10:3, Ch 5.1.2
4 Gray code In a Gray code only one variable is changed for each (cyclic) step. Example Example of NBCD and Gray code for N = 4 and N = 8. N = 4 N = 8 n NBCD Gray (NBCD = Natural Binary Coded Decimal.) n NBCD Gray , Digitalteknik L10:4, Ch 5.1.2
5 Karnaugh maps A Karnaugh map is a function table in matrix form with at most two variables per dimension. the input combinations are listed as Gray code. Then, between two consecutive positions (horisontal or vertical) there is only a change in one variable. The Karnaugh map can be seen as a graphicaly interpretation of B n. The maps useful on paper (2-dimensions) are for functions with 2, 3, or 4 variables., Digitalteknik L10:5, Ch 5.1.2
6 Karnaugh maps (cont'd) f (x 1 x 2 ): f (x 1 x 2 x 3 ): f (x 1 x 2 x 3 x 4 ): f x f x 2 x f x 3 x f (0) f (1) 0 f (0) f (1) f (3) f (2) 00 f (0) f (1) f (3) f (2) x 1 1 f (2) f (3) x 1 1 f (4) f (5) f (7) f (6) 01 f (4) f (5) f (7) f (6) f 00 x f (0) f (1) x 1 x f (12) f (13) f (15) f (14) f (8) f (9) f (11) f (10) 01 x 1 x f (2) f (3) f (6) f (7) f (4) f (5), Digitalteknik L10:6, Ch 5.1.2
7 Minimisation Cubes In a Karnaugh map a cube is a (cyclic) rectangular block covering 2 k positions. Minimisation by Karnaugh maps Find as big rectangular blocks as possible with 2 k 1s and. These represent the prime implicants. Find the essential implicants. These must be part of the function. Chose a minimal number of the rest of the implicants such that the function is covered., Digitalteknik L10:7, Ch 5.1.2
8 Karnaugh minimisation (Ex) Example Consider the function f with f 1 (1) = {0, 2, 3, 7}, f 1 ( ) = {5, 6} The Karnaugh map is f x 1 x x A B C Prime implicants: A = c (0B0) (x) = x 1x 3 B = c (B1B) (x) = x 2 C = c (1B1) (x) = x 1 x 3 A and B are essential, and covers the function, i.e., f min = A B = x 1x 3 x 2 is a minimal function (disjunctive form)., Digitalteknik L10:8, Ch 5.1.2
9 Karnaugh minimisation (Conjunctive form) Example Consider the function f with f 1 (1) = {0, 2, 3, 7}, f 1 ( ) = {5, 6} The Karnaugh map is f x 1 x 2 11 C 10 x A B 0 - (Anti) prime implicants: ( A = c (x)) (B01) ( ) = x 2 x 3 = x2 x 3 ( B = c (x)) (10B) ( = x1 x 2) = x 1 x 2 ( C = c (x)) (1B0) ( = x1 x 3) = x 1 x 3 A is essential. Minimal conjunctive form: f min = A B = (x 2 x 3)(x 1 x 2 ) f min = A C = (x 2 x 3)(x 1 x 3 ), Digitalteknik L10:9, Ch 5.1.2
10 Minimal disjunctive form Example 5.7 (disjunctive form) The function f (x 1 x 2 x 3 x 4 ) has f 1 (1) = {0, 4, 5, 8, 9, 10, 11, 13, 15} Prime implicants: f A 00 B 01 x 1 x 2 11 C 10 x 3 x D E F A = x 2x 3x 4 B = x 1x 3x 4 C = x 1x 2 x 3 D = x 2 x 3x 4 E = x 1 x 4 F = x 1 x 2, Digitalteknik L10:11, Ch 5.1.2
11 Prime table A prime table (P-table) shows which minterms the prime implicants cover. Rows correspond to prime implicants. Columns correspond to minterms. A cross shows when a minterm is covered by the implicant. Then an essential row contains a that is not represented in any other rows. Essential rows must be in the cover. row r dominates row s, r s, if all in s also exist in r. The dominated row, s, can be deleted. column c dominates column d, c d, if all in d also exist in c. The dominating column, c, can be deleted., Digitalteknik L10:12, Ch 5.1.2
12 Prime table (Ex 5.7) A x x B x x C x x D x x E x x x x F x x x x Essential: E from 15 F from 10 All columns that have in row E and F are deleted from the table, they are covered by E and F., Digitalteknik L10:13, Ch 5.1.2
13 Prime table (Ex 5.7) B A x B x x C x x C D x Here, B dominates A and C dominates D B x x C x x Now we see that 4 dominates both 0 and 5. Henc, the column 4 is deleted. Then, both B and C are (secondary) essential. f = E F B C Remark: From the Karnaugh map we can nd two other minimal covers: f = E F B D and f = E F A C, Digitalteknik L10:14, Ch 5.1.2
14 Cyclic prime table Example The function f i specied by f 1 (1) = {5, 6, 15} f 1 (0) = {0, 2, 8, 10, 12} A f x 1 x x 3 x B C, Digitalteknik L10:16, Ch 5.1.2
15 Cyclic prime table Example (cont'd) A x x B x x C x x The table is cyclic (No essentioal rows, dominating rows or dominating columns). M = (A B)(A C)(B C) = AB AC ABC AC AB ABC BC BC f = A B = x 1 x 2 x 4 f = A C = x 1 x 2 x 2 x 3 f = B C = x 4 x 2 x 3, Digitalteknik L10:17, Ch 5.1.2
16 Minimal conjunctive form Example 5.7 (conjunctive form) The function f has f 1 (0) = {1, 2, 3, 6, 7, 12, 14} Karnaugh map: f x 1 x 2 11 x 3 x 4 A B C 10 D, Digitalteknik L10:19, Ch 5.1.2
17 Minimal conjunctive form Example (cont'd) (Dual of) implicants: A = (x 1x 2x 4 ) = x 1 x 2 x 4 B = (x 1x 3 ) = x 1 x 3 C = (x 2 x 3 x 4) = x 2 x 3 x 4 D = (x 1 x 2 x 4) = x 1 x 2 x 4 Essential: A, B, and D The essentials cover f. f = A B D = (x 1 x 2 x 4)(x 1 x 3)(x 1 x 2 x 4 ), Digitalteknik L10:20, Ch 5.1.2
18 5 variables Example 5.9 Minimise f (x 1 x 2 x 3 x 4 x 5 ) where f 1 (1) = {4, 5, 6, 7, 13, 15, 20, 21, 23, 26, 27, 29, 30, 31} To solve this we need three dimensions. Use two separate maps and view them as the third dimension (on top of each other)., Digitalteknik L10:21, Ch 5.1.2
19 Ex 5.9 (solution) Split the function in two Karnaugh maps, one for x 1 = 0 and one for x 1 = 1: x 4 x 5 x 4 x 5 f x f x A x 2 x B C D x 2 x x 1 = 0 x 1 = 1 Prime implicants: A = x 2 x 3x 4 C = x 3 x 5 B = x 1 x 2 x 3 D = x 1 x 2 x 4 All prime implicants are essential, f = A B C D, Digitalteknik L10:22, Ch 5.1.2
20 More than one function Example 5.10 Minimise a minimal circuit that realises the functions f 1 1 (1) = {1, 3, 5, 7, 8, 9, 12, 14} f 1 2 (1) = {1, 3, 5, 7, 8, 9, 10, 14, 15}, Digitalteknik L10:23, Ch 5.1.2
21 Ex 5.10 (solution) Karnaugh maps for f 1 and f 2 to get implicants for the separeted functions: f x 2 x D x 4 x 5 A B C f x 2 x x 4 x 5 A B F H G E E I, Digitalteknik L10:24, Ch 5.1.2
22 Ex 5.10 (solution) Implicants that can be used in both f 1 and A f 2 : x 3 x 4 f 1 f B 01 x 1 x J E, Digitalteknik L10:25, Ch 5.1.2
23 P-table (Ex 5.10) f 1 f A x x x x B x x x x x x x x C x x D x x E x x x x F x x G x x H x x I x x J x x, Digitalteknik L10:26, Ch 5.1.2
24 1st reduction f 1 f A x x C x x D x x E x x x x F x G x x H x x I x x J x x, Digitalteknik L10:27, Ch 5.1.2
25 2nd reduction A E delete A. Then E is (sec.) essential in both f 1 and f 2. D C delete D I G delete I F H delete F f 1 f C x x G x x H x x J x x Then C is (sec.) essential in f 1 and G and H are (sec.) essential in f 2. f 1 = B E C f 2 = B E G H, Digitalteknik L10:28, Ch 5.1.2
Digitalteknik EIT020. Lecture 10: Karnaugh Maps
Digitalteknik EIT020 Lecture 10: Karnaugh Maps September 30, 2014 Idea of minimisation Theorem There exists a prime cover that is a minimal cover. Minimal prime cover Find all prime implicants. Find the
Digitalteknik EIT020. Lecture 18: Linear Sequential Circuits (Time Domain)
Digitalteknik EIT020 Lecture 18: Linear Sequential Circuits (Time Domain) November 16, 2014 Linear Boolean functions Denition (Linearity) A function f is said to be linear if f (x y) = f (x) f (y) (L 1
Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011
Problem 2-1 Recall that a minterm is a cube in which every variable appears. A Boolean expression in SOP form is canonical if every cube in the expression has a unique representation in which all of the
This form sometimes used in logic circuit, example:
Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from
If f = ABC + ABC + A B C then f = AB C + A BC + AB C + A BC + A B C
Examples: If f 5 = AB + AB then f 5 = A B + A B = f 10 If f = ABC + ABC + A B C then f = AB C + A BC + AB C + A BC + A B C In terms of a truth table, if f is the sum (OR) of all the minterms with a 1 in
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational
Logical Design of Digital Systems
Lecture 4 Table of Content 1. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memory structures 4. Programmable logic devices 5. Algorithmic minimization approaches
Unit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
CPE100: Digital Logic Design I
Chapter 2 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Combinational Logic Design Chapter
Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms
Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley
CSE20: Discrete Mathematics for Computer Science. Lecture Unit 2: Boolan Functions, Logic Circuits, and Implication
CSE20: Discrete Mathematics for Computer Science Lecture Unit 2: Boolan Functions, Logic Circuits, and Implication Disjunctive normal form Example: Let f (x, y, z) =xy z. Write this function in DNF. Minterm
CHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all Lecture #: Combinational Circuit Synthesis I Combinational Circuit Synthesis Recall: Combinational circuit
Combinational Logic Fundamentals
Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
CHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
Combinational Logic. Review of Combinational Logic 1
Combinational Logic! Switches -> Boolean algebra! Representation of Boolean functions! Logic circuit elements - logic gates! Regular logic structures! Timing behavior of combinational logic! HDLs and combinational
Binary logic consists of binary variables and logical operations. The variables are
1) Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two
MC9211 Computer Organization
MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra
Unit 6. Quine-McClusky Method. Unit 6 1
Unit 6 Quine-McClusky Method Unit 6 1 Outline Determination of prime implicants The prime implicant chart Petrick s method Simplification of incompletely specified functions Unit 6 2 Overview (1/2) A systematic
Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata
Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,
Boolean Algebra. Philipp Koehn. 9 September 2016
Boolean Algebra Philipp Koehn 9 September 2016 Core Boolean Operators 1 AND OR NOT A B A and B 0 0 0 0 1 0 1 0 0 1 1 1 A B A or B 0 0 0 0 1 1 1 0 1 1 1 1 A not A 0 1 1 0 AND OR NOT 2 Boolean algebra Boolean
Midterm1 Review. Jan 24 Armita
Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon
Chapter 2. Digital Logic Basics
Chapter 2 Digital Logic Basics 1 2 Chapter 2 2 1 Implementation using NND gates: We can write the XOR logical expression B + B using double negation as B+ B = B+B = B B From this logical expression, we
Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.
Boolean Expression Forms: Sum-of-products (SOP) Write an AND term for each input combination that produces a 1 output. Write the input variable if its value is 1; write its complement otherwise. OR the
Logic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 06 October 24, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative Admin for tonight Syllabus
CSE 140: Components and Design Techniques for Digital Systems
Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean Algebra
for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
Lecture 4: Four Input K-Maps
Lecture 4: Four Input K-Maps CSE 4: Components and Design Techniques for Digital Systems Fall 24 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Outlines Boolean
CSE 140, Lecture 2 Combinational Logic CK Cheng CSE Dept. UC San Diego
CSE 140, Lecture 2 Combinational Logic CK Cheng CSE Dept. UC San Diego 1 Combinational Logic Outlines 1. Introduction 1. Scope 2. Review of Boolean lgebra 3. Review: Laws/Theorems and Digital Logic 2.
Simplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
Boolean Algebra CHAPTER 15
CHAPTER 15 Boolean Algebra 15.1 INTRODUCTION Both sets and propositions satisfy similar laws, which are listed in Tables 1-1 and 4-1 (in Chapters 1 and 4, respectively). These laws are used to define an
Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
Anand Raghunathan MSEE 348
ECE 595Z: Digital VLSI Design Automation, Spring 2012 2012 Anand Raghunathan 1 ECE 595Z Digital Systems Design Automation Module 2 (Lectures 3-5) : Advanced Boolean Algebra Lecture 5 Anand Raghunathan
Introduction to Karnaugh Maps
Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for
Chapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 1 Gate Circuits and Boolean Equations Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. Overview Part 1 Gate
Section 1.2 Propositional Equivalences. A tautology is a proposition which is always true. A contradiction is a proposition which is always false.
Section 1.2 Propositional Equivalences A tautology is a proposition which is always true. Classic Example: P P A contradiction is a proposition which is always false. Classic Example: P P A contingency
Combinational Logic Circuits Part II -Theoretical Foundations
Combinational Logic Circuits Part II -Theoretical Foundations Overview Boolean Algebra Basic Logic Operations Basic Identities Basic Principles, Properties, and Theorems Boolean Function and Representations
Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1
Ch 2. Combinational Logic II - Combinational Logic Contemporary Logic Design 1 Combinational logic Define The kind of digital system whose output behavior depends only on the current inputs memoryless:
KP/Worksheets: Propositional Logic, Boolean Algebra and Computer Hardware Page 1 of 8
KP/Worksheets: Propositional Logic, Boolean Algebra and Computer Hardware Page 1 of 8 Q1. What is a Proposition? Q2. What are Simple and Compound Propositions? Q3. What is a Connective? Q4. What are Sentential
Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173
Propositional Logic CSC 17 Propositional logic mathematical model (or algebra) for reasoning about the truth of logical expressions (propositions) Logical expressions propositional variables or logical
Boolean Algebra, Gates and Circuits
Boolean Algebra, Gates and Circuits Kasper Brink November 21, 2017 (Images taken from Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.) Outline Last week: Von
Karnaugh Maps Objectives
Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between
Logic Gate Level. Part 2
Logic Gate Level Part 2 Constructing Boolean expression from First method: write nonparenthesized OR of ANDs Each AND is a 1 in the result column of the truth table Works best for table with relatively
Review for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18
University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering Boolean Algebra Boolean Algebra A Boolean algebra is defined with: A set of
COM111 Introduction to Computer Engineering (Fall ) NOTES 6 -- page 1 of 12
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 6 -- page 1 of 12 Karnaugh Maps In this lecture, we will discuss Karnaugh maps (K-maps) more formally than last time and discuss a more
Combinatorial Logic Design Principles
Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1 Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages
Spiral 1 / Unit 5. Karnaugh Maps
-. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
Digital Logic Design. Malik Najmus Siraj
Digital Logic Design Malik Najmus Siraj siraj@case.edu.pkedu LECTURE 4 Today s Agenda Recap 2 s complement Binary Logic Boolean algebra Recap Computer Arithmetic Signed numbers Radix and diminished radix
Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
Chapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1
Digital Logic COMP370 Introduction to Computer Architecture Logic Simplification It is frequently possible to simplify a logical expression. This makes it easier to understand and requires fewer gates
L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES
L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore
Optimizations and Tradeoffs. Combinational Logic Optimization
Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming
UNIT 5 KARNAUGH MAPS Spring 2011
UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable
UNIT 4 MINTERM AND MAXTERM EXPANSIONS
UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and
Week-I. Combinational Logic & Circuits
Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and
Minimierung. Wintersemester 2018/19. Folien basierend auf Material von F. Vahid und S. Werner Vorlesender: Dr. Ing.
Minimierung Grundlagen der technischen Informatik Wintersemester 28/9 Folien basierend auf Material von F. Vahid und S. Werner Wintersemester 28/9 Review - Boolean Algebra Properties Commutative (Kommutativgesetz)
L9: Galois Fields. Reading material
L9: Galois Fields Reading material Muzio & Wesselkamper Multiple-valued switching theory, p. 3-5, - 4 Sasao, Switching theory for logic synthesis, pp. 43-44 p. 2 - Advanced Logic Design L9 - Elena Dubrova
Propositional Logic:
CS2209A 2017 Applied Logic for Computer Science Lecture 8, 9 Propositional Logic: Conjunctive Normal Form & Disjunctive Normal Form Instructor: Yu Zhen Xie 1 Conjunctive Normal Form (CNF) Resolution works
Administrative Notes. Chapter 2 <9>
Administrative Notes Note: New homework instructions starting with HW03 Homework is due at the beginning of class Homework must be organized, legible (messy is not), and stapled to be graded Chapter 2
Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
Philadelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
Chapter 2 Combinational logic
Chapter 2 Combinational logic Chapter 2 is very easy. I presume you already took discrete mathemtics. The major part of chapter 2 is boolean algebra. II - Combinational Logic Copyright 24, Gaetano Borriello
Logic and Boolean algebra
Computer Mathematics Week 7 Logic and Boolean algebra College of Information Science and Engineering Ritsumeikan University last week coding theory channel coding information theory concept Hamming distance
ECE473 Lecture 15: Propositional Logic
ECE473 Lecture 15: Propositional Logic Jeffrey Mark Siskind School of Electrical and Computer Engineering Spring 2018 Siskind (Purdue ECE) ECE473 Lecture 15: Propositional Logic Spring 2018 1 / 23 What
9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories
. Unit Implementing Combinational Functions with Karnaugh Maps or Memories . Outcomes I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate
Minimization of Boolean Expressions Using Matrix Algebra
Minimization of Boolean Expressions Using Matrix Algebra Holger Schwender Collaborative Research Center SFB 475 University of Dortmund holger.schwender@udo.edu Abstract The more variables a logic expression
REPRESENTATION AND MINIMIZATION OF BOOLEAN FUNCTIONS. Part II Minimization of Boolean Functions.
Bulletin of the Marathwada Mathematical Society Vol.5, No.1, June 2004, Pages 35-44 REPRESENTATION AND MINIMIZATION OF BOOLEAN FUNCTIONS. Part II Minimization of Boolean Functions. S.R. Joshi 3, Accharya
Logic Synthesis and Verification
Logic Synthesis and Verification Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 24 Two-Level Logic Minimization (/2) Reading: Logic Synthesis in a Nutshell
Hardware Design I Chap. 2 Basis of logical circuit, logical expression, and logical function
Hardware Design I Chap. 2 Basis of logical circuit, logical expression, and logical function E-mail: shimada@is.naist.jp Outline Combinational logical circuit Logic gate (logic element) Definition of combinational
Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions
EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The
Boolean Algebra and Logic Gates
Boolean Algebra and Logic Gates ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Basic
Boolean Algebra and Logic Simplification
S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions
Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 3 for ENEL 353 Fall 2016 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2016 SN s ENEL 353 Fall 2016 Slide Set 3 slide
Chapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev
E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean
CHAPTER 5 KARNAUGH MAPS
CHAPTER 5 1/36 KARNAUGH MAPS This chapter in the book includes: Objectives Study Guide 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three-Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps
Propositional Calculus: Formula Simplification, Essential Laws, Normal Forms
P Formula Simplification, Essential Laws, Normal Forms Lila Kari University of Waterloo P Formula Simplification, Essential Laws, Normal CS245, Forms Logic and Computation 1 / 26 Propositional calculus
Chapter 4 Optimized Implementation of Logic Functions
Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization
Karnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
ELEC Digital Logic Circuits Fall 2014 Switching Algebra (Chapter 2)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Switching Algebra (Chapter 2) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn,
ECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions
Last (Family) Name: KIME First (Given) Name: Student I: epartment of Electrical and omputer Engineering University of Wisconsin - Madison EE/omp Sci 352 igital System Fundamentals Quiz # Solutions October
Systems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
Chapter-2 BOOLEAN ALGEBRA
Chapter-2 BOOLEAN ALGEBRA Introduction: An algebra that deals with binary number system is called Boolean Algebra. It is very power in designing logic circuits used by the processor of computer system.
Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا
Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.
E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates
Digital Circuits & Systems Lecture Transparencies (Boolean lgebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean lgebra & Logic Gates Major topics Boolean algebra NND & NOR gates Boolean algebra
Minimization techniques
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation
Lecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
CS/COE0447: Computer Organization and Assembly Language
CS/COE0447: Computer Organization and Assembly Language Logic Design Introduction (Brief?) Appendix B: The Basics of Logic Design Dept. of Computer Science Logic design? Digital hardware is implemented
ELC224C. Karnaugh Maps
KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on
Slides for Lecture 10
Slides for Lecture 10 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 30 September, 2013 ENEL 353
The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,
Combinational Logic (mostly review!)
ombinational Logic (mostly review!)! Logic functions, truth tables, and switches " NOT, N, OR, NN, NOR, OR,... " Minimal set! xioms and theorems of oolean algebra " Proofs by re-writing " Proofs by perfect
CSE 140 Midterm I - Solution
CSE 140 Midterm I - Solution 1. Answer the following questions given the logic circuit below. (15 points) a. (5 points) How many CMOS transistors does the given (unsimplified) circuit have. b. (6 points)