ELEC Digital Logic Circuits Fall 2014 Switching Algebra (Chapter 2)

Transcription

1 ELEC Digital Logic Circuits Fall 2014 Switching Algebra (Chapter 2) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL Fall 2014, Sep ELEC Lecture 4 1

2 Switching Algebra A Boolean algebra, where Set K contains just two elements, {0, 1}, also called {false, true}, or {off, on}, etc. Two operations are defined as, + OR, AND Fall 2014, Sep ELEC Lecture 4 2

3 Claude E. Shannon ( ) Fall 2014, Sep ELEC Lecture 4 3

4 Shannon s Legacy A Symbolic Analysis of Relay and Switching Circuits, Master s Thesis, MIT, Perhaps the most influential master s thesis of the 20 th century. An Algebra for Theoretical Genetics, PhD Thesis, MIT, Founded the field of Information Theory. C. E. Shannon and W. Weaver, The Mathematical Theory of Communication, University of Illinois Press, A must read. Fall 2014, Sep ELEC Lecture 4 4

5 Switching Devices Electromechanical relays (1940s) Vacuum tubes (1950s) Bipolar transistors ( ) Field effect transistors ( ) Integrated circuits ( ) Nanotechnology devices (future) Fall 2014, Sep ELEC Lecture 4 5

6 Example: Automobile Ignition Engine turns on when Ignition key is applied AND AND Car is in parking gear OR Brake pedal is on Seat belt is fastened OR Car is in parking gear Fall 2014, Sep ELEC Lecture 4 6

7 Switching logic Parking gear Seat belt Key Brake pedal Parking gear Battery Motor Fall 2014, Sep ELEC Lecture 4 7

8 Define Boolean Variables Parking gear Seat belt Key P = {0, 1} S = {0, 1} Battery K = {0, 1} Brake pedal Parking gear B = {0,1} P = {0, 1} 0 means switch off or open 1 means switch on or closed Motor M = {0, 1} Fall 2014, Sep ELEC Lecture 4 8

9 Write Boolean Function Parking gear Seat belt Key P = {0, 1} S = {0, 1} Battery K = {0, 1} Brake pedal Parking gear B = {0,1} P = {0, 1} Motor M = {0, 1} Ignition function: M = K AND (P OR B) AND (S OR P) = K(P + B)(S + P) Fall 2014, Sep ELEC Lecture 4 9

10 Simplify Boolean Function M = K AND (P OR B) AND (S OR P) = K(P + B)(S + P) = K(P + B)(P + S) Commutativity = K (P + B S) Distributivity Fall 2014, Sep ELEC Lecture 4 10

11 Construct an Optimum Circuit M = K (P + B S) Parking gear Key P = {0, 1} Battery K = {0, 1} Brake pedal Seat belt B = {0,1} S = {0, 1} This is a relay circuit. Earlier logic circuits, even computers, were built with relays. Motor M = {0,1} Fall 2014, Sep ELEC Lecture 4 11

12 Implementing with Relays An electromechanical relay contains: Electromagnet Current source A switch, spring-loaded, normally open or closed Switch has two states, open (0) or closed (1). The state of switch is controlled by not applying or applying current to electromagnet. Fall 2014, Sep ELEC Lecture 4 12

13 One Switch Controlling Other Switches X and Y are normally open. Y cannot close unless a current is applied to X. X Y Y = X Fall 2014, Sep ELEC Lecture 4 13

14 Inverting Switch Switch X is normally closed and Y is normally open. Y cannot open unless a current is applied to X. X Y Y = X Fall 2014, Sep ELEC Lecture 4 14

15 Boolean Operations AND Series connected relays. OR Parallel relays. A A B F B F F = A B F = A + B Fall 2014, Sep ELEC Lecture 4 15

16 Complement (Inversion) A A F B F F = A F = A + B = A B Fall 2014, Sep ELEC Lecture 4 16

17 Relay Computers Conrad Zuse ( ) Z1 (1938) Z3 (1941) Fall 2014, Sep ELEC Lecture 4 17

18 Electronic Switching Devices Electron Tube Fleming, 1904 de Forest, 1906 Point Contact Transistor Bardeen, Brattain, Shockley, 1948 Fall 2014, Sep ELEC Lecture 4 18

19 Transistor, 1948 The thinker, the tinkerer, the visionary and the transistor John Bardeen, Walter Brattain, William Shockley Nobel Prize, 1956 Fall 2014, Sep ELEC Lecture 4 19

20 Bell Laboratories, Murray Hill, New Jersey Fall 2014, Sep ELEC Lecture 4 20

21 Fall 2014, Sep ELEC Lecture 4 21

22 Bipolar Junction Transistor (BJT) Fall 2014, Sep ELEC Lecture 4 22

23 Field Effect Transistor (FET) a.k.a. metal oxide semiconductor (MOS) FET. (metal oxide) Fall 2014, Sep ELEC Lecture 4 23

24 Integrated Circuit (1958) Jack Kilby ( ), Nobel Prize, 2000 Fall 2014, Sep ELEC Lecture 4 24

25 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Drain Drain Gate VGS Short or Open Gate VGS Short or Open Source Source NMOSFET VGS = 0, open VGS = high, short PMOSFET VGS = 0, short VGS = high, open Reference: R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw Hill. Fall 2014, Sep ELEC Lecture 4 25

26 NMOSFET NOT Gate (Early Design) A: Boolean variable A = VDD volts; 1, true, on A = 0 volt; 0, false, off A Power supply VDD volts w.r.t. ground Ground = 0 volt A Problem: When A = 1, current leakage causes power dissipation. Solution: Complementary MOS design proposed by F. M. Wanlass and C.-T. Sah, Nanowatt Logic Using Field- Effect Metal-Oxide Semiconductor Triodes, International Solid State Circuits Conference Digest of Technical Papers, Feb 20, 1963, pp Fall 2014, Sep ELEC Lecture 4 26

27 CMOS Circuit Wanlass, F. M. "Low Stand-By Power Complementary Field Effect Circuitry. U. S. Patent 3,356,858 (Filed June 18, Issued December 5, 1967). Fall 2014, Sep ELEC Lecture 4 27

28 CMOS NOT Gate (Modern Design) Power supply VDD = 1 volt; voltage depends on technology. A = VDD = 1 volt is state 1 A = GND = 0 volt is state 0 Truth Table A A A A A A 0 1 Electrical Circuit GND Ground 1 0 Boolean Function Symbol Fall 2014, Sep ELEC Lecture 4 28

29 CMOS Logic Gate: NAND Electrical Circuit VDD Boolean Function Truth Table A B F A Symbol A F B F B GND Fall 2014, Sep ELEC Lecture 4 29

30 CMOS Logic Gate: NOR Electrical Circuit A VDD Boolean Function Truth Table A B F A Symbol F B F B GND Fall 2014, Sep ELEC Lecture 4 30

31 CMOS Logic Gate: AND Boolean Function Symbol Truth Table A B F F A B F A B F Fall 2014, Sep ELEC Lecture 4 31

32 CMOS Logic Gate: OR Boolean Function Symbol Truth Table A B F F A B F A B F Fall 2014, Sep ELEC Lecture 4 32

33 CMOS Gates Logic function Number of transistors 1 or 2 inputs N inputs NOT 2 - AND 6 2N + 2 OR 6 2N + 2 NAND 4 2N NOR 4 2N Fall 2014, Sep ELEC Lecture 4 33

34 Optimized Ignition Logic M = K (P + B S) = KP + KBS K KP P M B S KBS 3 gates, 20 transistors. Can we reduce transistors? Fall 2014, Sep ELEC Lecture 4 34

35 Further Optimization M = K (P + B S) = KP + KBS (Distr. law) = KP + KBS (Theorem 3, involution) NAND gates 4+6 transistors K P B S = KP KBS (De Morgan s theorem) KP M KBS 3 gates, 14 transistors. Fall 2014, Sep ELEC Lecture 4 35

36 Digital Systems DIGITAL CIRCUITS Fall 2014, Sep ELEC Lecture 4 36

37 Digital Logic Design Representation of switching function: Truth table Canonical forms Karnaugh map Logic minimization: Minimize number of literals. Technology mapping: Implement logic function using predesigned gates or building blocks from a technology library. Fall 2014, Sep ELEC Lecture 4 37

38 Truth Table Truth table is an exhaustive description of a switching function. Contains 2 n input combinations for n variables. Example: f(a,b,c) = A B + A C + A C n Input variables, n = 3 Output A B C f(a,b,c) n = 8 rows Fall 2014, Sep ELEC Lecture 4 38

39 How Many Switching Functions? Output column of truth table has length 2 n for n input variables. It can be arranged in variables. ways for n Example: n = 1, single variable. Input n 2 2 Output functions A F1(A) F2(A) F3(A) F4(A) Fall 2014, Sep ELEC Lecture 4 39

40 Definitions Boolean variable: A variable denoted by a symbol; can assume a value 0 or 1. Literal: Symbol for a variable or its complement. Product or product term: A set of literals, ANDed together. Example, a b c. Cube: Same as a product term. Sum: A set of literals, Ored together. Example, a + b + c. Fall 2014, Sep ELEC Lecture 4 40

41 More Definitions SOP (sum of products): A Boolean function expressed as a sum of products. Example: f(a,b,c) = A B + A C + A C POS (product of sums): A Boolean function expressed as a product of sums. Example: f(a,b,c) = ( A + B + C) ( A + B + C) ( A + B + C) Fall 2014, Sep ELEC Lecture 4 41

42 Minterm A product term in which each variable is present either in true or in complement form. For n variables, there are 2 n unique minterms. Minterm m 0 m 1 m 2 m 3 m 4 m 5 m 6 m 7 Product A B C A B C A B C A B C A B C A B C A B C A B C Fall 2014, Sep ELEC Lecture 4 42

43 Minterms are Canonical Functions Value of minterm 1 0 m 0 m 1 m 2 m 3 m 4 m 5 m 6 m Input Fall 2014, Sep ELEC Lecture 4 43

44 Canonical SOP Form a.k.a. Disjunctive Normal Form (DNF) A Boolean function expressed as a sum of minterms. Example: f(a,b,c) = A B + A C + A C = A BC + ABC + A B C + AB C + ABC = m 1 +m 3 +m 4 +m 6 +m 7 = m(1, 3, 4, 6, 7) Truth table with row numbers Row No. A B C f(a,b,c) Fall 2014, Sep ELEC Lecture 4 44

45 Maxterm A summation term in which each variable is present either in true or in complement form. For n variables, there are 2 n unique maxterms. Maxterm M 0 M 1 M 2 M 3 M 4 M 5 M 6 M 7 Sum A + B + C A + B + C A + B + C A + B + C A + B + C A + B + C A + B + C A + B + C Fall 2014, Sep ELEC Lecture 4 45

46 Canonical POS Form a.k.a. Conjunctive Normal Form (CNF) A Boolean function expressed as a product of maxterms. Example: f(a,b,c) = A B + A C + A C = (A + B + C)(A + B + C)( A + B + C) = M 0 M 2 M 5 = Π M(0, 2, 5) Truth table with row numbers Row No. A B C f(a,b,c) Fall 2014, Sep ELEC Lecture 4 46

47 Canonical Forms are Unique A canonical form completely defines a Boolean function. That is, for every input the canonical form specifies the value of the function. To determine canonical form: Construct truth table and sum minterms corresponding to 1 outputs, or multiply maxterms corresponding to 0 outputs. Alternatively, use Shannon s expansion theorem (see Section 2.2.3, page 101). Two Boolean functions are identical if and only if their canonical forms are identical. Fall 2014, Sep ELEC Lecture 4 47

48 Why Generate Canonical Form? Example: Are the following Boolean Functions Identical? F1= A B D + F2 F3 = = A C D A B D A B C D + B D A C D + A B D + B C D Generate canonical forms, e.g., minterms, and compare. + Fall 2014, Sep ELEC Lecture 4 48

49 Algebraic Procedure Expand each term to contain all variables Remember Postulate 6: Complement a + a = 1 a a = 0 Postulate 2: Identity elements a + 0 = a, 0 is identity element for + a 1 = a, 1 is identity element for dot ( ) Fall 2014, Sep ELEC Lecture 4 49

50 F1= ABD + ABD + ACD = ABD(C + C) + ABD(C + C) + ACD(B + B) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD = m 7 + m 5 + m 15 + m 13 + m 11 = m(5, 7,11,13,15) Similarly, F2 F3 = = m(5, 7,11,13,15) m(5, 7,11,13,15) Hence, three functions are identical. Fall 2014, Sep ELEC Lecture 4 50

51 Karnaugh Map 1952: Edward M. Veitch invented a graphical procedure for digital circuit optimization. 1953: Maurice Karnaugh perfected the map procedure: The Map Method for Synthesis of Combinational Logic Circuits, Trans. AIEE, pt I, 72(9): , November Fall 2014, Sep ELEC Lecture 4 51

52 Karnaugh Map: 2 Variables, A, B A = 0 A = 1 Unit Hamming distance between adjacent cells B = 0 B = 1 m 0 m m 2 m Each cell is a minterm m 3 = AB = 11 (numerical interpretation) Fall 2014, Sep ELEC Lecture 4 52

53 Representing a Function B = 0 B = 1 A = 0 A = m 0 m m 1 m Place 1 in cells corresponding to minterms in canonical form. For example, see F = A B + A B represented on the left. Truth Table A B F Fall 2014, Sep ELEC Lecture 4 53

54 Grouping Adjacent Minterms A = 0 A = 1 B = Adjacent cells differ in one variable, which is eliminated. B = 1 m 0 1 m For example, F = A B + A B = A(B + B) = A m 1 m 3 Product term A Fall 2014, Sep ELEC Lecture 4 54

55 Karnaugh Map Minimization Canonical SOP form represented on map Example: F = A B + A B + A B Find minimal cover (fewest groups of largest sizes), F = A + B A = 0 A = 1 product A B = 0 1 A F m 0 m 2 B B = product B m 1 m 3 Fall 2014, Sep ELEC Lecture 4 55

56 Karnaugh Map: 3 Variables, A, B, C A C B Check unit Hamming distance between adjacent cells. Fall 2014, Sep ELEC Lecture 4 56

57 Synthesizing a Digital Function Start with specification. Create a truth table from specification. Minimize (SOP with fewest literals): Either write canonical SOP Reduce using postulates and theorems Or find largest cubes from Karnaugh map Minimized SOP gives a two-level AND-OR circuit. NAND or NOR circuit for CMOS technology can be found using de Morgan s theorem. Fall 2014, Sep ELEC Lecture 4 57

58 Example: Multiplexer Inputs: A, B, C Output: F Function: F = A, when C = 1 F = B, when C = 0 Fall 2014, Sep ELEC Lecture 4 58

59 3-Input Function: Multiplexer B C A Truth Table row A B C F C B A C F = A C + B C A C F B Fall 2014, Sep ELEC Lecture 4 59

60 Technology Optimization A C B F = A C + B C F = 20 transistors A C F B Fall 2014, Sep ELEC Lecture 4 60

61 Optimized Multiplexer A C B X Y F F = X + Y = X Y from de Morgan' s theorem A X C B F Y = 14 transistors Fall 2014, Sep ELEC Lecture 4 61

62 Karnaugh Map: 4 Variables, A, B, C, D A D C B Check unit Hamming distance between adjacent cells. Fall 2014, Sep ELEC Lecture 4 62

63 Adjacency of Edge Cells Fall 2014, Sep ELEC Lecture 4 63

64 Reexamine Three Functions from Slide 48 Example: Are the following Boolean Functions Identical? F1= A B D + A B D + A C D F2 = A C D + A B D + B C D F3 = A B C D + B D This time generate Karnaugh maps, and compare. Fall 2014, Sep ELEC Lecture 4 64

65 F1 = A Karnaugh Map of F1 B D + A B D + A C D A C D F1 = Σm(5,. 7, 11, 13, 15) B Fall 2014, Sep ELEC Lecture 4 65

66 Karnaugh Map of F2 F2 = A C D + A B D + B C D A C D. F2 = Σm(5, 7, 11, 13, 15) F1 and F2 cover same area on map. Fall 2014, Sep ELEC Lecture 4 66 B

67 F3 = A B C D + Karnaugh Map of F3 B D A C D F3 = Σm(5, 7, 11, 13, 15) F1, F2 and F3 cover exactly the. same area on map, hence, they are identical. Fall 2014, Sep ELEC Lecture 4 67 B

68 Ignition Function Minterm K P B S M M = K AND (P OR B) AND (S OR P) = K(P + B)(S + P) Fall 2014, Sep ELEC Lecture 4 68

69 Karnaugh Map: M(K, P, B, S) K B S. P Fall 2014, Sep ELEC Lecture 4 69

70 Karnaugh Map: Minimum Cover K KP B S KBS. P Fall 2014, Sep ELEC Lecture 4 70

71 Minimized Function M = KP + KBS K P M B S Fall 2014, Sep ELEC Lecture 4 71

72 Using Inverting Gates Because They Need Fewer Transistors M = KP + KBS = KP KBS Using de Morgan s Theorem K P M B S Fall 2014, Sep ELEC Lecture 4 72

73 Karnaugh Map on the Web Fall 2014, Sep ELEC Lecture 4 73

74 Minterm Clusters, Cubes or Products A ABCD ABD BCD D C AC Larger clusters are products with fewer variables. B Fall 2014, Sep ELEC Lecture 4 74

75 Product P 1 = ABCD = A + B + C + D A B C D P1 Signals are voltages B w.r.t. GROUND A = 0 or 1 volt C B = 0 or 1 volt C = 0 or 1 volt D D = 0 or 1 volt NMOS transistors A GROUND VDD = 1 volt PMOS transistors P1 = 0 or 1 volt More variables in a product mean more transistors (hardware). Fall 2014, Sep ELEC Lecture 4 75

76 A C Product P 2 = AC = P2 AC VDD = 1 volt Signals are voltages w.r.t. GROUND A A = 0 or 1 volt B = 0 or 1 volt C = 0 or 1 volt C D = 0 or 1 volt P1 = 0 or 1 volt GROUND Fewer variables in a product mean fewer transistors (hardware). Fall 2014, Sep ELEC Lecture 4 76

77 Observations A larger minterm cluster is a product with fewer variables; requires fewer transistors. Each gate input needs two transistors. Smaller number of clusters is more efficient: Fewer gates to generate products. Fewer inputs for the OR gate to produce the function. Direct minterm implementation is most inefficient. Fall 2014, Sep ELEC Lecture 4 77