Pipeline Datapath. With some slides from: John Lazzaro and Dan Garcia

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1 Pipeline path With some slides from: John Lazzaro and Dan Garcia

2 Gotta Do Landry Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and pt away Washer takes 3 mintes A B C D Dryer takes 3 mintes Folder takes 3 mintes Stasher takes 3 mintes to pt clothes into drawers 2

3 Seqential Landry 6 P A T a s k O r d e r A B C D Time Seqential landry takes 8 hors for loads 3

4 Pipelined Landry 2 2 A 6 P T a s k O r d e r A B C D Pipelined landry takes 3.5 hors for loads! Time

5 instrction registers מבנה ה - path rd rs rt + imm. Instrction Fetch 2. Decode/ ister 3. Eecte. emory 5. Back 5

6 I n s t r. O r d e r Graphical Pipeline Representation (In, right half highlight read, left half write) Time (clock cycles) Load Store Sb Or I$ I$ I$ D$ I$ D$ I$ D$ D$ D$ 7

7 חלוקה לשלבים IF: Instrction fetch ID: Instrction decode/ register file read EX: Eecte/ address calclation E: emory access : back Shift left 2 reslt ress Instrction Instrction register register 2 isters 2 register Zero reslt ress 6 Sign etend 32 8

8 Instrction הוספת הרגיסטרים IF/ID ID/EX EX/E E/ Shift left 2 reslt ress Instrction register register 2 isters 2 register Zero reslt ress 6 Sign etend 32 9

9 I n s t r c t i o n l w I n s t r c t i o n f e t c h IF/ID I F / I D I D / E X E X / E E / W B A d d A d d A d d r e s l t S h i f t l e f t 2 P C A d d r e s s I n s t r c t i o n m e m o r y R e a d r e g i s t e r R e a d r e g i s t e r 2 R e g i s t e r s W r i t e r e g i s t e r W r i t e d a t a R e a d d a t a R e a d d a t a 2 A L U Z e r o A L U r e s l t A W r i t e d a t a R e a d d a t a 6 S i g n e t e n d 3 2

10 I n s t r c t i o n l w I F / I D I n s t r c t i o n d e c o d e ID/EX I D / E X E X / E E / W B A d d A d d A d d r e s l t S h i f t l e f t 2 P C A d d r e s s I n s t r c t i o n m e m o r y R e a d r e g i s t e r R e a d r e g i s t e r 2 R e g i s t e r s W r i t e r e g i s t e r W r i t e d a t a R e a d d a t a R e a d d a t a 2 A L U Z e r o A L U r e s l t A d d r e s s W r i t e d a t a D a t a m e m o r y R e a d d a t a 6 S i g n e t e n d 3 2

11 2 Instrction ress 32 reslt Shift left 2 Instrction IF/ID EX/E isters 2 register register 2 6 Sign etend register reslt Zero ID/EX E/ Eection lw ress EX/E

12 l w e m o r y E/ I F / I D I D / E X E X / E E / W B A d d A d d A d d r e s l t S h i f t l e f t 2 P C A d d r e s s I n s t r c t i o n m e m o r y I n s t r c t i o n R e a d r e g i s t e r R e a d r e g i s t e r 2 R e g i s t e r s W r i t e r e g i s t e r W r i t e d a t a R e a d d a t a R e a d d a t a 2 A L U Z e r o A L U r e s l t A d d r e s s W r i t e d a t a D a t a m e m o r y R e a d d a t a 6 S i g n e t e n d 3 2 3

13 I n s t r c t i o n l w W r i t e b a c k I F / I D I D / E X E X / E E / W B A d d A d d A d d r e s l t S h i f t l e f t 2 P C A d d r e s s I n s t r c t i o n m e m o r y R e a d r e g i s t e r R e a d r e g i s t e r 2 R e g i s t e r s W r i t e r e g i s t e r W r i t e d a t a R e a d d a t a R e a d d a t a 2 A L U Z e r o A L U r e s l t A d d r e s s D a t a W r i t e d a t a m e m o r y R e a d d a t a 6 S i g n e t e n d 3 2

14 Instrction תיקון!!! correction A IF/ID ID/EX EX/E E/ Shift left 2 reslt ress Instrction register register 2 isters 2 register Zero reslt ress 6 Sign etend 32 5 Keep the right Rd all the way!

15 Instrction So here is the pdated CPU; IF/ID ID/EX EX/E E/ Shift left 2 reslt ress Instrction register register 2 isters 2 register Zero reslt ress 6 Sign etend 32 6

16 Instrction Control Src IF/ID ID/EX EX/E E/ Shift left 2 reslt Branch ress Instrction register register 2 isters 2 register Instrction [5 ] 6 Sign 32 etend Src 6 control Zero reslt ress em em emto Instrction [2 6] Instrction [5 ] Dst Op 8

17 Instrction emto em path with Control Src Control ID/EX EX/E E/ IF/ID EX ress Instrction register register 2 isters register 2 Shift left 2 reslt Src Zero reslt Branch ress Instrction 6 32 [5 ] Sign etend 6 control em Instrction [2 6] Instrction [5 ] Dst Op 9

18 דוגמא A demonstration of a seqence of instrctions: Lw $,2($) Sb $,$2,$3 And $2,$,$5 Or $3,$6,$7 $,$8,$9 2

19 Instrction emto em Instrction emto em IF: lw $, 2($) ID: before<> EX: before<2> E: before<3> : before<> IF/ID Control ID/EX EX EX/E E/ ress Instrction register register 2 isters 2 register Shift left 2 reslt Src Zero reslt Branch ress Instrction [5 ] Sign etend control em Clock Instrction [2 6] Instrction [5 ] Dst Op IF: sb $, $2, $3 ID: lw $, 2($) EX: before<> E: before<2> : before<3> IF/ID lw Control ID/EX EX EX/E E/ ress Instrction X 2 register register 2 isters $X 2 register Instrction [5 ] Sign etend $ 2 Shift left 2 reslt control Src Zero reslt Branch ress em 2 Clock 2 X Instrction [2 6] Instrction [5 ] X Dst Op

20 Instrction emto em Instrction emto em IF: and $2, $, $5 ID: sb $, $2, $3 EX: lw $,... E: before<> : before<2> IF/ID sb Control ID/EX EX EX/E E/ ress Instrction 2 3 register $2 register 2 isters $3 2 register Shift left 2 $ reslt Src Zero reslt Branch ress X Instrction [5 ] Sign etend X 2 control em Clock 3 X Instrction [2 6] Instrction [5 ] X Dst Op IF: or $3, $6, $7 ID: ID: and and $2, $2, $2, $, $3 $5 EX: sb $,... E: lw $,... : before<> IF/ID and Control ID/EX EX EX/E E/ ress Instrction 5 X Shift left 2 register $ $2 register 2 isters $5 $3 2 register Instrction [5 ] Sign etend X reslt control Src Zero reslt Branch ress em 22 Clock X 2 Instrction [2 6] Instrction [5 ] X 2 Dst Op

21 Instrction emto em Instrction emto em IF: add $, $8, $9 ID: or $3, $6, $7 EX: and $2,... E: sb $,... : lw $,... IF/ID or Control ID/EX EX EX/E E/ ress Instrction 6 7 register $6 register 2 isters $7 2 register Shift left 2 $ $5 reslt Src Zero reslt Branch ress X Instrction [5 ] Sign etend X control em Clock 5 X 3 Instrction [2 6] Instrction [5 ] X 3 2 Dst Op IF: after<> ID: add $, $8, $9 EX: or $3,... E: and $2,... : sb $,... IF/ID add Control ID/EX EX EX/E E/ ress Instrction 8 9 X register register 2 isters $9 2 register Instrction [5 ] Sign etend $8 X Shift left 2 $6 $7 reslt control Src Zero reslt Branch ress em 23 Clock 6 X Instrction [2 6] Instrction [5 ] X 3 Dst Op 2

22 Instrction emto em Instrction emto em IF: after<2> ID: after<> EX: add $,... E: or $3,... : and $2,... IF/ID Control ID/EX EX EX/E E/ ress Instrction 2 register register 2 isters 2 register Shift left 2 $8 $9 reslt Src Zero reslt Branch ress Instrction [5 ] Sign etend control em Clock 7 Instrction [2 6] Instrction [5 ] Dst Op 3 2 IF: after<3> ID: after<2> EX: after<> E: add $,... : or $3,... IF/ID Control ID/EX EX EX/E E/ ress Instrction 3 register register 2 isters 2 register Instrction [5 ] Sign etend Shift left 2 reslt control Src Zero reslt Branch ress em 2 Clock 8 Instrction [2 6] Instrction [5 ] Dst Op 3

23 e m t o R e g e m W r i t e R e g W r i t e I F : a f t e r < > I D : a f t e r < 3 > E X : a f t e r < 2 > E : a f t e r < > W B : a d d $,... I F / I D C o n t r o l I D / E X W B E X E X / E W B E / W B W B A d d P C A d d r e s s I n s t r c t i o n m e m o r y I n s t r c t i o n R e a d r e g i s t e r R e a d R e a d d a t a r e g i s t e r 2 R e g i s t e r s R e a d d a t a 2 W r i t e r e g i s t e r W r i t e d a t a S h i f t l e f t 2 A d d A d d r e s l t A L U S r c Z e r o A L U A L U r e s l t B r a n c h A d d r e s s D a t a m e m o r y W r i t e d a t a R e a d d a t a I n s t r c t i o n [ 5 ] S i g n e t e n d A L U c o n t r o l e m R e a d C l o c k 9 I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] R e g D s t A L U O p 25

24 Problems for Compters Limits to pipelining: Hazards prevent net instrction from eecting dring its designated clock cycle Strctral hazards: HW cannot spport this combination of instrctions (single person to fold and pt clothes away) Control hazards: Pipelining of branches & other instrctions stall the pipeline ntil the hazard bbbles in the pipeline hazards: Instrction depends on reslt of prior instrction still in the pipeline 26

25 An eample for hazards: sb $2, $, $3 and $2, $2, $5 or $3, $6, $2 add $, $2, $2 sw $5, ($2) 27

26 An eample for hazards: sb $2, $, $3 and $2, $2, $5 or $3, $6, $2 add $, $2, $2 sw $5, ($2) An eample for hazards: ister $2 is pdated only at the phase, i.e., the 5th clock cycle (actally at the end of the 5th clock cycle). However, we try to se it at the 3rd clock cycle when we read $2 at the decode phase of the and instrction 28

27 Graphic representation of hazards: Time (in clock cycles) Vale of register $2: Program eection order (in instrctions) sb $2, $, $3 CC CC 2 CC 3 CC CC 5 CC 6 I CC 7 CC 8 CC 9 / D and $2, $2, $5 I D or $3, $6, $2 I D add $, $2, $2 I D sw $5, ($2) I D 29

28 Solving hazards by adding nops sb $2, $, $3 nop nop nop and $2, $2, $5 or $3, $6, $2 add $, $2, $2 sw $5, ($2) 3

29 Solving hazards by adding nops P r o g r a m e e c t i o n o r d e r ( i n i n s t r c t i o n s ) s b $ 2, $, $ 3 T i m e ( i n c l o c k c y c l e s ) V a l e o f r e g i s t e r $ 2 : C C C C 2 C C 3 C C C C 5 C C 6 I R e g D R e g C C 7 C C 8 C C 9 / C C C C C C nop I R e g D R e g nop I R e g D R e g nop I R e g D R e g a n d $ 2, $ 2, $ 5 I R e g D R e g o r $ 3, $ 6, $ 2 I R e g D R e g a d d $, $ 2, $ 2 I R e g D R e g 3 s w $ 5, ( $ 2 ) I R e g D R e g

30 We cold earn ck cycle if GPR is transparent P r o g r a m e e c t i o n o r d e r ( i n i n s t r c t i o n s ) s b $ 2, $, $ 3 T i m e ( i n c l o c k c y c l e s ) V a l e o f r e g i s t e r $ 2 : C C C C 2 C C 3 C C C C 5 C C 6 I R e g D R e g C C 7 C C 8 C C 9 / C C C C C C nop I R e g D R e g nop I R e g D R e g a n d $ 2, $ 2, $ 5 I R e g D R e g o r $ 3, $ 6, $ 2 I R e g D R e g a d d $, $ 2, $ 2 We cold earn ck cycle if GPR is transparent, i.e, we cold see the write to the GPR at the GPR otpts (if the write address eqals the read address), i.e., dring Ck #5. I R e g D R e g s w $ 5, ( $ 2 ) I R e g D R g e 32

31 After doing that change we only need 2 nops sb $2, $, $3 nop nop and $2, $2, $5 or $3, $6, $2 add $, $2, $2 sw $5, ($2) After the change the of an early instrction can happen at the same time with the read reg (decode) phase of a newer instrction (3 with two other instrctions in between). In case we have a hazard, we need to add only two nop instrctions. Unfortnately, this happens too often. We need a better soltion! 33

32 Graphic representation of hazards: Time (in clock cycles) Vale of register $2: Program eection order (in instrctions) sb $2, $, $3 CC CC 2 CC 3 CC CC 5 CC 6 I CC 7 CC 8 CC 9 / D and $2, $2, $5 I D or $3, $6, $2 I D add $, $2, $2 I D sw $5, ($2) I D 3

33 Vale of register $2: Program eection order (in instrctions) sb $2, $, $3 CC CC 2 CC 3 CC CC 5 CC 6 CC 7 CC 8 / I D and $2, $2, $5 I D or $3, $6, $2 I D add $, $2, $2 35 I D

34 גניבת הערכים Forwarding Time (in clock cycles) CC CC 2 CC 3 CC CC 5 CC 6 CC 7 CC 8 CC 9 Vale of register $2 : / Vale of EX/E : X X X 2 X X X X X Vale of E/ : X X X X 2 X X X X Program eection order (in instrctions) sb $2, $, $3 I D and $2, $2, $5 I D or $3, $6, $2 I D add $, $2, $2 I D sw $5, ($2) I D 36

35 Time (in clock cycles) CC CC 2 CC 3 CC CC 5 CC 6 CC 7 CC 8 C Vale of register $2 : / Vale of EX/E : X X X 2 X X X X Vale of E/ : X X X X 2 X X X Program eection order (in instrctions) sb $2, $, $3 I D and $2, $2, $5 I D or $3, $6, $2 I D add $, $2, $2 I D 37 sw $5, ($2) I D R

36 Forwarding (done at the eecte phase) Instrction ID/EX EX/E Control E/ IF/ID EX Instrction isters IF/ID.isterRs Rs IF/ID.isterRt Rt IF/ID.isterRt IF/ID.isterRd Rt Rd EX/E.isterRd Forwarding nit E/.isterRd If ID/EX.Rs=EX/E.Rd, i.e., the Rd of the previos instrction eqals the Rs of the crrent instrction (which is in the decode phase), then we se the ot of the previos instrction instead of the otpt of the GPR. If ID/EX.Rs=E/.Rd, i.e., the Rd of the previos instrction eqals the Rs of the crrent instrction (which is in the decode phase), then we se the ot of the previos instrction instead of the otpt of the GPR. [ similarly, compare also ID/EX.Rt to E/.Rd ] 38 Similarly, compare also ID/EX.Rt to EX/E.Rd and to E/.Rd

37 לא תמיד הפתרון עובד - lw The soltion does not work for (in lw we do not have the in the pipe!, it comes from the!) Program eection order (in instrctions) lw $2, 2($) Time (in clock cycles) CC CC 2 CC 3 CC CC 5 CC 6 I D CC 7 CC 8 CC 9 and $, $2, $5 I D or $8, $2, $6 I D add $9, $, $2 I D slt $, $6, $7 I D If the previos instrction was lw to a register and we try to se the register in the crrent instrction, we have a problem, since we cannot go back in time! One soltion is to avoid sch cases by adding a nop (by the Assembler) whenever Rt of the lw is eqal to Rs or Rt of the following instrction. 39

38 Another h/w soltion is to add Bbbles, i.e., add nop by hardware Program eection order (in instrctions) Time (in clock cycles) CC CC 2 CC 3 CC CC 5 CC 6 CC 7 CC 8 CC 9 CC lw $2, 2($) I D and $, $2, $5 I D or $8, $2, $6 add $9, $, $2 slt $, $6, $7 I nop I D bbble I D I D We need to hold IF/ID for one ck cycle and insert a nop: into ID/EX. This is eqal to adding a nop instrction by the Assembler.

39 Instrction IF/ID Rs, Rt of crrent inst. IF/ID Hazard detection nit Hazard detection nit Control ID/EX.em ID/EX EX identifies lw EX/E E/ Instrction isters IF/ID.isterRs Rt from prev. inst. IF/ID.isterRt IF/ID.isterRt IF/ID.isterRd ID/EX.isterRt Rt Rd Rs Rt Forwarding nit EX/E.isterRd E/.isterRd We need to hold the IF/ID and for one ck cycle and insert a nop: into ID/EX. This is eqal to adding a nop instrction by the Assembler. If (ID/EX.emRd)&& ( (ID/EX.Rt= =IF/ID.Rs) (ID/EX.Rt= =IF/ID.Rt) ) we mst stall the pipeline! This means that prev. inst was lw and it was to the crrent Rs or Rt. (of corse if one of them is not sed, don t stall) Holding means freeze the IF/ID and the for clock cycle Hold the IF/ID by not giving a IF/IDWrire signal and do not increment the (which already points at the ne instrction) by not giving the signal. Inserting a nop is by clearing all control signals.

40 דוגמא An eample for lw hazard detection lw $2, 2($) And $, $2, $5 Or $, $, $2 $9, $, $2 2

41 Instrction IF/ID Instrction IF/ID and $, $2, $5 lw $2, 2($) before<> before<2> IF/ID X Hazard detection nit Control ID/EX.em ID/EX EX EX/E E/ before<3> Instrction X isters $ $X ID/EX.isterRt X 2 Forwarding nit Clock 2 or $, $, $2 and $, $2, $5 2 5 Hazard detection nit ID/EX.em ID/EX lw $2, 2($) EX/E before<> before<2> IF/ID Control EX E/ Instrction 2 5 isters $2 $5 $ $X ID/EX.isterRt X Forwarding nit 3 Clock 3

42 Instrction IF/ID Instrction IF/ID or $, $, $2 IF/ID and $, $2, $5 2 5 Hazard detection nit Control ID/EX.em ID/EX EX bbble EX/E lw $2,... E/ before<> Instrction 2 5 isters $2 $5 $2 $ ID/EX.isterRt Forwarding nit 2 Clock add $9, $, $2 IF/ID or $, $, $2 2 Hazard detection nit Control ID/EX.em ID/EX EX and $, $2, $5 bbble lw $2,... EX/E E/ Instrction 2 2 isters $ $2 $2 $ ID/EX.isterRt Forwarding nit 2 Clock 5 The lw instrction is in the phase. $2 is being written. We can se $2 in the Eecte phase of the and instrction, with the help of forwarding.

43 Instrction IF/ID Instrction IF/ID after<> add $9, $, $2 or $, $, $2 and $,... bbble 2 Hazard detection nit ID/EX.em ID/EX EX/E IF/ID Control EX E/ Instrction 2 isters $ $2 $ $2 2 2 ID/EX.isterRt 9 Forwarding nit Clock 6 after<2> IF/ID after<> Hazard detection nit Control ID/EX.em ID/EX EX add $9, $, $2 or $,... and $,... EX/E E/ $ Instrction isters $2 2 ID/EX.isterRt 9 Forwarding nit 5 Clock 7

44 Control Hazard: Branching (/7) Optimization #: move asynchronos comparator p to Stage 2 as soon as instrction is decoded (Opcode identifies is as a branch), immediately make a decision and set the vale of the (if necessary) Benefit: since branch is complete in Stage 2, only one nnecessary instrction is fetched, so only one no-op is needed Side Note: This means that branches are idle in Stages 3, and 5. 6

45 7 Instrction isters EX ID/EX EX/E E/ Hazard detection nit Forwarding nit IF.Flsh IF/ID Sign etend Control = Shift left 2

46 Control Hazard: Branching (5/7) I n s t r. O r d e r Insert a single no-op (bbble) add beq lw Time (clock cycles) I$ D$ I$ D$ bb ble I$ D$ Impact: 2 clock cycles per branch 8 instrction slow

47 שאלה ממבחן: add $2, $3, $ lw $2, 2($3) lw $3, ($2) add $2, $3, $ add $, $3, $2 lw $, 2($) sw $, 2($3).pipeline במחשב IPS לפניך קוד המבוצע בארכיטקטורת קוד זה גורם ל. hazard להתבצע. פרט אותם וציין את מספר מחזורי השעון שלוקח לקוד 9

48 שאלה ממבחן: בניסיון לייעל את ארכיטקטורת ה pipeline הוחלט לשנות את פקודות ה lw ו sw כך שבמקום לקבל את הכתובת כחלק מהפקודה )בין אם מדובר על כתובת של קריאה או כתיבה( הכתובת תמיד תלקח מתוך הרגיסטר s$. כלומר, לפני השינוי הפקודות עבדו כך: lw $, imm($y) <====> $ := E[$y + imm] sw $, imm($y) <====> E [$y + imm] := $ ואחרי השינוי: lw $ <====> $ := E[$s] sw $ <====> E[$s] :=$ סעיף א': תארו כיצד ניתן לנצל עובדה זו על מנת לייעל את ארכיטקטורת ה pipeline מבחינת קווי בקרה, קווי מידע, רכיבים, מספר מחזורי שעון הנדרשים לביצוע פעולה וטיפול ב.hazrads סעיף ב': פרטו את ה hazards ותארו כיצד ניתן לפתור כל אחד מהם ביעילות באמצעות החומרה.. add $s, $t, $t2 2. lw $s 3. sw $s. lw $s 5. add $t3, $s, $s 5

Pipeline Datapath. With some slides from: John Lazzaro and Dan Garcia

Pipeline Datapath. With some slides from: John Lazzaro and Dan Garcia Pipeline Datapath With some slides from: John Lazzaro and Dan Garcia The single cycle CPU Instrction [25 ] Shift Jmp address [3 ] left 2 26 28 PC+ [3 28] Instrction [3 26] Control RegDst Jmp Branch em