RISC Processors. Hierarchical VLSI Design. Multiple Layered Architecture. 6. Case Study: Formal Verification of RISC Processors using HOL

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6. Case Study: Formal Verfcaton of RISC Processors usng HOL RISC Processors Motvaton RISC Verfcaton Model Dervng Formal Specfcatons Verfcaton Tasks Ppelne Correctness Processor Specfc Defntons

29 Advantages: Popular and used n a wde range of applcatons Smaller and smpler nstructon set than CISCs Herarchcal and well structured Problems: Reasonng about the ppelne verfcaton Complexty of

1 6. Case Study: Formal Verfcaton of RISC Processors usng HOL RISC Processors Motvaton RISC Verfcaton Model Dervng Formal Specfcatons Verfcaton Tasks Ppelne Correctness Processor Specfc Defntons Expermental Results Conclusons References Page Advantages: Popular and used n a wde range of applcatons Smaller and smpler nstructon set than CISCs Herarchcal and well structured Problems: Reasonng about the ppelne verfcaton Complexty of contemporary RISC-Processors Restrcton to the core archtecture 6. (of 29) 6.2 (of 29) Multple Layered Archtecture Herarchcal VLSI Desgn Archtecture Core Archtecture: RISC processor base Basc ppelne Basc nstructon set (nteger, logc, load/ store, control) Protected Archtecture Numerc Archtecture Core Archtecture RTL Desgn Logc Gates Net. Transstor Net. Layout 6.3 (of 29) 6.4 (of 29)

2 Formal Verfcaton of Mcroprocessors RISC Instructon Executon ADD R Rj SUB R Rj JMP ### MOV R Rj Instr. Set MEM PC RF Prog. Model HW-Desgn RISC Instructon: Ppelne Stages: Clock Phases: Instructon Cycle u u+ IF ID WB t t+ t t+n s Clock n p 2 Specfcaton Proof Implementaton 3 4 Behavoral Descrpton Structural Descrpton Bus pr. Ppelne Stage RF read 6.5 (of 29) 6.6 (of 29) Instructon Classes MIPS Ppelne Structure Ppelne stages IF ID EX MEM WB ALU IF_X ID_X ALUOUT A op B MEM_A WB_A LOAD IF_X A RF [rs] 2 B RF [rs2] STORE IR M[PC] PC PC+4 2 IR IR EX_L MEM_L RF [rd] LMDR ID_X EX_S M[DMAR SMDR CONTROL IF_X ID_C Instructon Classes Class nstructon: corresponds to the set of nstructons wth smlar semantcs, e.g. ALU, FLP, LOAD, CONTROL abstracts the behavor of a group of nstructons, e.g. ALU:= (ADD,SUB,SHIFT,OR, ) Class Level: set of all nstructon classes Class abstracton orented proofs: -reducng the verfcaton overhead -reasonng about few class nstructons -nstantatng the obtaned theorems for nstructons at the archtectural level 6.7 (of 29) 6.8 (of 29) 2

3 RISC Verfcaton Model Dervng Formal Specfcatons Archtecture and class levels: Archtecture Level Class Level Stage Level Phase Level Abstracton Specfed usng the nstructon cycle tme granularty Derved automatcally from the nstructon set Example: - Manual: ADD:= RF[rd] RF[rs] + RF[rs2] - Archtecture Level: ADD_Instr (...):= u:inst_cycle. RF(u+)[rd(u)] = RF(u)[rs(u)] + RF(u)[rs2(u)] Hardware (RTL) - Class Level: ALU_Instr (...):= u:inst_cycle. RF(u+)[rd(u)] = RF(u)[rs(u)] op RF(u)[rs2(u)] 6.9 (of 29) 6.0 (of 29) Dervng Formal Specfcatons Stage and phase levels: Specfed usng the clock cycle or the clock phase tme granulartes Derved automatcally from the ppelne structure Example: - Common ID-stage: ID_Instr (...):= t: Clk_cycle. A(t+) = RF(t) [rs(t)] B(t+) = RF(t) [rs2(t)] IR(t+) = IR(t) RTL of MIPS (smplfed) ext_trap ackn Trap Control Bypass Logc IR3 IR2 IR IR Man Decode ControlUnt Datapath rd mem_data PC and Branch Logc Instr Memory mem_addr lmdr_mux rw smdr_mux alu_op a_mux,b_mux Imm rs rs2 WB MEM EX ID IF Reg.Fle ALUout A ALUout alu_op ALU B Reg.Fle LMDR DMAR rw dmem_addr dmem_data SMDR Data Memory 6. (of 29) 6.2 (of 29) 3

4 Hardware Formal Descrpton RTL: Specfed as a hardware structure (net lst) Derved automatcally from a schematc n CADENCE Formally descrbed as a herarchy of predcates: RTL (PC, I-MEM, RF,, A, B,, IR, IR, ) = rs,rs2,rd,alu_op,rw, mem_adr,. DataPath (RF, A, B, Aluout, alu_op, ) Control_Unt (PC, IR, rw, mem_adr, ) Instr_Memory (I-MEM, mem_adr, ) Data_Memory (D-MEM, dmem_adr, rw, ) Verfcaton Tasks Goal: Any nstructon sequence of the RISC archtecture s correctly executed by the mplementaton (RTL) Step: nstructons RTL Instructon Level Step 2: SW_Contrants, RTL I IF ID EX MEM WB IF ID EX MEM WB I IF ID EX MEM WB IF ID EX MEM WB I ns IF ID EX MEM WB tme Correct_Instr_Ppelnng 6.3 (of 29) 6.4 (of 29) Step : Correctness of Sngle Instructons Step 2: Ppelne Correctness Goal: The RTL mplements the semantcs of the nstructon set correctly Herarchcal proof of the Class Level: RTL Phase Level Phase Level Stage Level Stage Level Class Level Instantatons for each archtectural nstructon: RTL Phase Level Stage Level Instructon Level Automatc goal settngs usng parameterzed functons Automatc proofs usng parameterzed proof scrpts nstructons I IF ID EX MEM WB IF ID EX MEM WB I IF ID EX MEM WB IF ID EX MEM WB I ns IF ID EX MEM WB Clock n s tme Goal: all combnatons of n s nstructons n the ppelne are executed wthout conflcts 6.5 (of 29) 6.6 (of 29) 4

5 Ppelne Conflcts Facltatng the Ppelne Conflct Verfcaton Resource conflcts (structural hazards) arse from the smultaneous use of resources Data conflcts (data hazards) occur due to data dependences between the nstructons n the ppelne Control conflcts (control hazards) arse due to the lnear ppelne flow caused by control nstructons Correct_Instr_Ppelnng:= I I ns : class_nstructon. ( Resource_Conflct (I I ns )) ( Data_Conflct (I I ns )) ( Control_Conflct (I I ns )) All possble conflct combnatons between n s potental nstructons n the ppelne: multple conflcts Conflcts between pars of nstructons: dual conflcts - multple conflcts are specfed n terms of dual conflcts - verfcaton of multple conflcts s deduced from that of dual conflcts Conflct specfcatons based on the herarchy levels of the RISC model - multple and dual conflcts are consdered for each specfc level - ndependent herarchcal proof at each level possble 6.7 (of 29) 6.8 (of 29) Example: Data Conflcts RAW Data Conflct Specfcaton - Read-After-Wrte (RAW) - Wrte-After-Read (WAR) - Wrte-After-Wrte (WAW) Data_Conflct (I I ns ):= Multple_RAW_Conflct (I I ns ) Multple_WAR_Conflct (I I ns ) Multple_WAW_Conflct (I I ns ) Verfcaton goal: SW_Contrants, RTL Multple_RAW_Conflct (I I ns ) Multple_WAR_Conflct (I I ns ) Multple_WAW_Conflct (I I ns ) Multple Conflct: nstructons I I I ns Multple_RAW_Conflct (I I ns ):= Dual_RAW_Conflct ((I, t ), (I j, t +j-)), j (, j =... n s ) ( < j) Dual Conflct: Dual_RAW_Conflct ((I, t ), (I j, t j)):= Stage_RAW_Conflct ( ) Phase_RAW_Conflct ( ) n s tme 6.9 (of 29) 6.20 (of 29) 5

6 RAW Data Conflct Specfcaton RAW Data Conflct Verfcaton Stage Level Conflct: Stage_RAW_Conflct ( ):= (t j - t ) (s - s j) Stage_Range (I, s, r) Stage_Doman (I j, s j,r) I I j j t R j s j s t W Ultmate goal: I I ns. Multple_RAW_Conflct (I I ns ) Step : I I j. j. Dual_RAW_Conflct ((I, t ), (I, t j)) j Phase Level Conflct: Phase_RAW_Conflct ( ):= ( j - ) (s - s j) (p j p ) Phase_Range (I,s,p,r) Phase_Doman (I, s, p, j j j S S j 0 /j p p np P P j R j W Step 2: ( Dual_RAW_Conflct) ( Multple_RAW_Conflct) Step 2 s straghtforward Step s equvalent to: Stage_RAW_Conflct) [( Phase_RAW_Conflct) ] 6.2 (of 29) 6.22 (of 29) Goal: Stage RAW Data Conflct Verfcaton II j. t t j. s s j. r. Stage_RAW_Conflct ( ) Processor Specfc Defntons Enumeraton types for ppelne characterstcs: ppelne_stage = IF ID EX MEM WB clock_phase = Tactc: DATA_CONFLICT_TAC Stage_RAW_Conflct Subgoals: (I = LOAD), (I j= ALU), [(s = WB), (s j = ID), (r = RF) ] ( j - ) 3 Resoluton n software ( delayed load ): SW_Constrant:= [(I = LOAD) (Ij = ALU) (r = RF) ] (( t j - t ) 3) Enumeraton types for class, stage and phase nstructons: class_nstructon = ALU ALU_I LOAD STORE CONTROL stage_nstructon = phase_nstructon = Enumeraton types for level correspondng resources: CL_resource = PC RF of RF_addr I_MEM D_MEM IAR SL_resource = PL_resource = 6.23 (of 29) 6.24 (of 29) 6

7 RISC Verfcaton Methodology Expermental Results ADD R Rj SUB R Rj JMP ### MOV R Rj Arch. Level Class Level SemantcalCorrectness Class Abstracton Model Constructon Archtecture Level Stage Level Class Level Stage Level Phase Level RTL Phase Level RTL SW- Constr. Ppelne Correctness Verfcaton Goal Tme n sec Comments Predcates Extractons Resource Conflcts Conflcts RAW Conflcts Conflct cases WAR Conflcts Conflcts WAW Conflcts Conflcts Control Conflcts Conflct case Ppelne Correctness Semantcal Correctness MIPS Verfcaton (h 33mn) 6.25 (of 29) 6.26 (of 29) Expermental Results (MIPS Processor) Conclusons RISC core CPU 32 bt archtecture 5 nstructons 5 stage ppelne mplemented n CADENCE Complexty: 50,000 transstors verfed down to RTL n HOL Theorem-prover based verfcaton could be automated by restrctng to classes of crcuts: RISC processors Novel herarchcal Specfcaton and Verfcatonmodel Overhead reducton usng the noton of nstructon classes Two ndependent verfcaton tasks: - semantcal and - ppelne correctness Automatc verfcaton usng few generalzed tactcs Processor ndependent verfcaton methodology Overall methodology mplemented n the HOL system Applcaton on a typcal RISC processor (MIPS) 6.27 (of 29) 6.28 (of 29) 7

8 References. S. Tahar and R. Kumar: A Practcal Methodology for the Formal Verfcaton of RISC Processors; Formal Methods n Systems Desgn, Vol. 3, No. 2, September 998, Kluwer Academc Publshers, pp S. Tahar and R. Kumar: Formal Specfcaton and Verfcaton Technques for RISC-Ppelne Conflcts; The Computer Journal, Vol. 38, No. 2, July 995, Oxford Unversty Press, pp (of 29) 8

CMP N 301 Computer Architecture. Appendix C

CMP N 301 Computer Architecture Appendix C Outline Introduction Pipelining Hazards Pipelining Implementation Exception Handling Advanced Issues (Dynamic Scheduling, Out of order Issue, Superscalar, etc)