A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2 n )

Transcription

1 Reconfgurable System on Chp Implementaton for Ellptc Curve Cryptography over GF( n ) Mchael Jung, M. Ernst, F. Madlener, S. Huss, R. lümel Integrated Crcuts and Systems Lab Computer Scence Department Darmstadt Unversty of Technology Germany cv cryptovson GmbH Gelsenkrchen Germany

2 ECC over GF( n ) GF( n ) operatons mplemented n HW Square, Multply, dd Inverson wth Fermat s lttle Theorem Polynomal ase Multpler based on a novel, generalzed verson of the Karatsuba Ofman lgorthm EC level algorthms mplemented n SW P lgorthm for EC pont multplcaton Projectve Pont Coordnates lgorthmc flexblty combned wth performance [] Karatsuba and Ofman, Multplcaton of multdgt numbers on automata, 96 [] Lopez/Dahab, Fast multplcaton on ellptc curves over GF(m) wthout precomputatons, 999

3 8-t RISC Mcrocontroller + MHz tmel FPSLIC Reconfgurable System on Chp

4 8-t RISC Mcrocontroller FPG k Gate Equvalents Dstrbuted FreeRM TM Cells tmel FPSLIC Reconfgurable System on Chp

5 8-t RISC Mcrocontroller FPG 6 kyte RM Dual Ported Smultaneously accessble by MCU and FPG tmel FPSLIC Reconfgurable System on Chp

6 8-t RISC Mcrocontroller FPG 6 kyte RM Perpherals URTs Tmers etc. tmel FPSLIC Reconfgurable System on Chp

7 8-t RISC Mcrocontroller FPG 6 kyte RM Perpherals tmel FPSLIC Reconfgurable System on Chp Low cost, low complexty devce

8 Polynomal Karatsuba Multplcaton Polynomal Karatsuba Multplcaton n x a n b x ( ) ( ) ( ) ˆ ˆ x x ( ) T ( ) ( ) T ( ) T ˆ ) ( ˆ T x T T T T x * ( ) ( ) ˆ ˆ x x ˆ n x x wth

9 Mult Mult-Segment Segment Karatsuba Karatsuba (MSK) (MSK) + k k k k k x S x S MSK,, ˆ ), ( ˆ ), ( ), ( ), ( ), ( ), ( ), (,,,, M S S S l m m l m l m l m + ), ( ), (,, M S l l + + m l l m l l l m M, ), ( wth, and Generalzaton of the Karatsuba Multplcaton lgorthm Polynomals are splt nto an arbtrary number of segments

10 MSK k for k MSK wth M M M M M M,,,,,, ( M, ) ( M, M, M,) ( M, M, M,) ( M, M, M,) ( M ), xˆ xˆ xˆ xˆ xˆ ( ) ( ) ( ) ( ) ( ) ( ) *

11 Reorderng of Partal Products ) Pattern Groupng ) Reorder pattern by decreasng x n ) Mnmze dfferences n the set of ndces of adjacent pattern *

12 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

13 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

14 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

15 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

16 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

17 Pattern Groupng.) Groupng the partal products to one of three possble pattern *

18 Reorderng of Partal Products ) Pattern Groupng ) Reorder pattern by decreasng x n ) Mnmze dfferences n the set of ndces of adjacent pattern *

19 Reorderng of Partal Products.) Orderng of the pattern n a top-left to bottom-rght fashon *

20 Reorderng of Partal Products.) Orderng of the pattern n a top-left to bottom-rght fashon *

21 Reorderng of Partal Products ) Pattern Groupng ) Reorder pattern by decreasng x n ) Mnmze dfferences n the set of ndces of adjacent pattern *

22 Reorderng of Partal Products.) Ensurng that the set of added up segments n the partal products dffers only by one element between two adjacent patterns *

23 Reorderng of Partal Products.) Ensurng that the set of added up segments n the partal products dffers only by one element between two adjacent patterns *

24 Multplcaton Sequence Mult

25 Multplcaton Sequence Mult Clock Cycle:

26 Multplcaton Sequence Mult Clock Cycle:

27 Multplcaton Sequence Mult Clock Cycle:

28 Multplcaton Sequence Mult Clock Cycle:

29 Multplcaton Sequence Mult Clock Cycle:

30 Multplcaton Sequence Mult Clock Cycle: 6

31 Multplcaton Sequence Mult Clock Cycle: 7

32 Multplcaton Sequence Mult Clock Cycle: 8

33 Coprocessor Interface VR EC level lgorthms FPG Fnte Feld rthmetc MULT DD RM Op. Op. SQURE FF-LU Controller...

34 Prototype Implementaton: -Segment Karatsuba (MSK ) -t combnatonal Multpler GF( ) Results FF-Level Operaton FF-Mult Clock Cycles best case worst case Operaton EC-Double Clock Cycles 9 FF-dd 6 6 EC-dd 6 FF-Square 9 k P, One EC pont multplcaton takes.9 MHz Speed-up factor of about compared to an assembler optmzed software mplementaton