Compact modeling of high-voltage LDMOS devices including quasi-saturation Aarts, A.C.T.; Kloosterman, W.J.

Transcription

1 Compact modelig of high-voltage LDMOS devices icludig quasi-saturatio Aarts, A.C.T.; Kloosterma, W.J. Published: //2006 Documet Versio Publisher s PDF, also kow as Versio of Record (icludes fial page, issue ad volume umbers) Please check the documet versio of this publicatio: A submitted mauscript is the author's versio of the article upo submissio ad before peer-review. There ca be importat differeces betwee the submitted versio ad the official published versio of record. People iterested i the research are advised to cotact the author for the fial versio of the publicatio, or visit the DOI to the publisher's website. The fial author versio ad the galley proof are versios of the publicatio after peer review. The fial published versio features the fial layout of the paper icludig the volume, issue ad page umbers. Lik to publicatio Citatio for published versio (APA): Aarts, A. C. T., & Kloosterma, W. J. (2006). Compact modelig of high-voltage LDMOS devices icludig quasi-saturatio. (CASA-report; Vol. 0621). Eidhove: Techische Uiversiteit Eidhove. Geeral rights Copyright ad moral rights for the publicatios made accessible i the public portal are retaied by the authors ad/or other copyright owers ad it is a coditio of accessig publicatios that users recogise ad abide by the legal requiremets associated with these rights. Users may dowload ad prit oe copy of ay publicatio from the public portal for the purpose of private study or research. You may ot further distribute the material or use it for ay profit-makig activity or commercial gai You may freely distribute the URL idetifyig the publicatio i the public portal? Take dow policy If you believe that this documet breaches copyright please cotact us providig details, ad we will remove access to the work immediately ad ivestigate your claim. Dowload date: 07. Ja. 29

2 Compact Modelig of High-Voltage LDMOS Devices icludig Quasi-Saturatio Aemarie C.T. Aarts ad Willy J. Kloosterma Abstract The surface-potetial-based compact trasistor model, MOS Model 20 (MM20), has bee exteded with quasisaturatio, a effect that is typical for LDMOS devices with a log drift regio. As a result, MM20 exteds its applicatio rage from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V. I this paper, the ew dc model of MM20 icludig quasi-saturatio is preseted. The additio of velocity saturatio i the drift regio esures the curret to be cotrolled by either the chael regio or the drift regio. A compariso with dc measuremets o a 60V LDMOS device shows that the ew model provides a accurate descriptio i all regimes of operatio, ragig from sub-threshold to super-threshold, i both the liear ad saturatio regime. Thus, owig to the iclusio of quasi-saturatio also the regime of high gate ad high drai bias coditios for high-voltage LDMOS devices is accurately described. Idex Terms LDMOS, Modelig, High-Voltage MOS, Quasi- Saturatio, Itegrated Circuit Desig. I. INTRODUCTION TODAY, high-voltage LDMOS devices are extesively used i all kids of itegrated power circuits for automotive ad cosumer applicatios. Optimal desig of these power circuits requires high-voltage LDMOS models for circuit simulatio, which describe the device characteristics accurately. Iclusio of specific LDMOS trasistor aspects, like the quasisaturatio effect, is therefore ecessary. Recetly, a ew compact LDMOS trasistor model called MOS Model 20 (MM20) has bee developed [1]. This model describes the currets of a LDMOS device i surfacepotetial formulatios, thereby icludig accumulatio i the drift regio. As a result, MM20 gives a accurate descriptio i all regimes of operatio, ragig from sub-threshold to superthreshold, i both the liear ad saturatio regime. The origial MM20 model is aimed at low-voltage LDMOS devices (which cosequetly have a relatively short drift regio). For such a LDMOS device, velocity saturatio always occurs i the chael regio of the device, the reaso why velocity saturatio occurrig i the drift regio has ot bee icluded i the origial MM20 model. For high-voltage LDMOS devices (which cosequetly have a log drift regio), however, velocity saturatio ca occur i the drift regio of the device [2], a operatig regime geerally referred to as quasi-saturatio. I that case, the saturatio characteristics of the device are A.C.T. Aarts was with Philips Research Laboratories, Eidhove, 5656 AA Eidhove, The Netherlads. She is ow with the Departmet of Mathematics ad Computer Sciece, Eidhove Uiversity of Techology, Eidhove 5600 MB, The Netherlads ( a.c.t.aarts@tue.l). W.J. Kloosterma is with Philips Semicoductors, Nijmege 6534 AE, The Netherlads. cotrolled by the drift regio istead of by the chael regio. The mai limitatio of the preset MM20 model thus is that it is ot applicable to these high-voltage devices. So far, various LDMOS models have bee developed which take quasi-saturatio ito accout [3]-[11]. I the sub-circuit models [3]-[8] the iteral potetials of the device are solved by the circuit-simulator, i which case o cotrol ca be executed o the covergece durig circuit simulatio. I the compact models [9]-[11], the iteral potetials are solved by a umerical iteratio procedure iside the model itself. The drawback of most models, however, is that accumulatio i the drift regio is eglected ([4], [9] ad [10]), ad that the sub-threshold regime is ot icluded ([3], [4], [9] ad [11]). The aim of this paper is to preset a ew model for MM20 which icludes the effect of quasi-saturatio. To that ed, velocity saturatio i the drift regio is icluded, which limits the dc-curret at high gate ad high drai bias coditios. Furthermore, i additio to accumulatio occurrig i the drift regio, also pich-off of the drift regio through depletio has bee icluded. The capacitaces are described accordig to the origial MM20 model [1]. Through the iclusio of quasi-saturatio, however, i the ew model the iteral drai potetial may obtai differet values, affectig the capacitace values accordigly. Thus, the ew model combies all the beefits of the origial model with the ability to accurately describe quasi-saturatio. As a result, a ew MM20 model is obtaied which ca be used for both low-voltage ad highvoltage LDMOS devices. II. HIGH-VOLTAGE LDMOS DEVICES I Fig. 1 a cross-sectio of a high-voltage LDMOS trasistor is give. The p-well bulk (B) is diffused from the source-side uder the gate (G), ad thus forms a graded chael regio (of legth L ch ). The iteral drai Di represets the poit where the graded chael turs ito the lightly doped -drift regio (of total legth L dr +L LOCOS ). To withstad the high voltages betwee source (S) ad drai (D), the drift regio is log ad it comprises two differet sectios: the first sectio is the thigate-oxide drift regio (of legth L dr ), ad the secod is the thick-field-oxide drift regio (of legth L LOCOS ). The legth of the gate o the thi gate oxide oly, is deoted by L PSOD. Above the threshold voltage of the chael regio, electros flow from the source through a iversio chael towards the drift regio. With the gate extedig over the drift regio, subsequetly a accumulatio layer forms at the surface udereath the thi gate oxide of the drift regio. At a certai

3 B + p S + p well L PSOD L LOCOS L ch Ldr LOCOS chael regio G Di D thi gate oxide drift regio drift regio D + thick field oxide drift regio Fig. 1. A cross-sectio of a high-voltage LDMOS trasistor, comprisig two differet drift regio sectios. poit i the thi-gate-oxide drift regio, depletio occurs ad the accumulatio layer vaishes. Cosequetly, the electros gradually flow ito the bulk of the drift regio (see [3]). Further towards the drai, i the thick-field-oxide drift regio, the electros are spread out across the whole body of the drift regio. Sice the LOCOS oxide is very thick compared to the thi gate oxide, the potetial applied to the gate termial has hardly ay ifluece o the electros i the drift regio udereath this LOCOS oxide. For simulatio of the high-voltage LDMOS devices, the subcircuit depicted i Fig. 2 is used. I this sub-circuit, MM20 describes the total regio udereath the thi gate oxide. Sice the gate voltage has hardly ay ifluece o the electros i the drift regio udereath the LOCOS oxide, the curret through the thick-field-oxide drift regio is represeted by a costat resistace R drift. The value of this resistace is give by over the whole gate-bias rage. We observe that for high gate voltages the icrease of saturatio curret with icreasig gate voltage dimiishes, which idicates the oset of quasisaturatio. The reaso for the occurrece of quasi-saturatio at high gate voltages is that the coductivity of the chael regio is high, whereas that of the thi-gate-oxide drift regio is low due to depletio i the drift regio. For further icreasig drai voltages the depletio layer wides, ad the curret through the drift regio becomes cofied to a limited effective crosssectio [3], which leads to velocity saturatio i the drift regio. Sice velocity saturatio occurrig i the drift regio has ot bee icluded i the preset dc model of MM20, it is impossible to adequately describe quasi-saturatio with this model. I Fig. 3 the simulated curret obtaied with MM20 without quasi-saturatio is plotted i compariso to the measuremets. We observe that for low gate voltages the model accurately describes the device characteristics. The reaso is that for these low gate voltages saturatio of the curret is cotrolled by the chael regio. For high gate voltages, however, the curret is strogly over-estimated by the model, sice i the preset model the curret ca ot be cotrolled by the drift regio. R drift = L LOCOS W R sheet, (1) where W is the width of the device, ad R sheet is the sheetresistace of the thick-field-oxide drift regio. The temperature rise due to self-heatig is take ito accout via a thermal etwork (ot show here) [7]. B S G MM20 D R drift Fig. 2. Equivalet circuit for the high-voltage LDMOS device of Fig. 1. MM20 describes the total regio udereath the thi gate oxide. The costat resistace R drift represets the drift regio udereath the thick LOCOS oxide. Low-voltage LDMOS devices lack a thick-field-oxide drift regio, ad thus have a relatively short drift regio; see [1]. I these devices the coductivity of the drift regio is always larger tha that of the chael regio, so that saturatio of the curret is cotrolled by the chael regio [8]. I high-voltage LDMOS devices, o the other had, the curret-voltage characteristics are affected at high gate-bias coditios; see Fig. 3. I this figure the measured drai-to-source curret of a highvoltage (60V) LDMOS device is plotted versus drai voltage, D Fig. 3. Measured (symbols) drai-to-source curret I DS i compariso to MOS Model 20 (MM20) without quasi-saturatio (solid lies), at V GS = 2.4, 3.4, 4.4, 6, 810ad 12 V ad V SB =0V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS =3.5 μm. III. MODEL DESCRIPTION INCLUDING QUASI-SATURATION I our compact modelig approach, firstly expressios for the curret I ch through the iversio chael as well as for the curret I dr through the drift regio are derived (see Sectios III-A ad III-B), both i terms of the kow termial drai-, gate-, source- ad bulk voltages V D, V G, V S ad V B, respectively, as well as of the ukow iteral drai voltage V Di. Subsequetly, the iteral drai voltage V Di is derived by equatig I ch to I dr. Sice iclusio of velocity saturatio i the drift regio makes the curret expressio for I dr more complex, a iteratio procedure is icluded iside the model for the calculatio of the iteral drai potetial. As the curret differece I ch I dr is a mootoically icreasig fuctio of V Di, with exactly oe zero betwee the sourcead the exteral drai potetial, the stadard Newto-Raphso

4 scheme is used combied with a bisectio procedure to speed up the iteratio process ad to esure that the iteral drai potetial remais withi its domai. I this way, a fast ad robust iteratio procedure is obtaied for the calculatio of the iteral drai potetial. Next, the iteral drai voltage is used to calculate the surface potetial ψ sl at the iteral drai accordig to [12]. Fially, the drift- ad diffusio compoet of the chael regio curret is calculated, both i terms of its surface potetials. Subsequetly, secod-order effects like chael legth modulatio, drai-iduced barrier lowerig ad static feedback are added. Notice that expressio of the fial curret i surface potetial formulatios yields a accurate curret descriptio, also i the sub-threshold regime. A. Chael curret For the calculatio of the iteral drai quasi-fermi potetial V Di, the chael curret I ch is expressed as (see [1] with the surface-potetial drop Δψ s replaced by V DiS ) I ch = Wμch eff C ( ox Viv0 1 2 ξv ) DiS VDiS. (2) L ch 1+θ 3 V DiS Here, μ ch eff is the effective electro mobility i the chael regio, C ox = ɛ ox /t ox is the thi-gate-oxide capacitace per uit area (with t ox the thickess of the thi gate oxide, ad ɛ ox its permittivity), V iv0 = Q iv0 /C ox represets the iversio charge Q iv per uit area at the source side, ad θ 3 = μ ch 0 /(L ch v sat ) represets velocity saturatio i the chael regio, with μ ch 0 the zero-field electro mobility i the chael regio ad v sat the saturated drift velocity of electros. The factor ξ =( Q iv / ψ s ) /C ox reflects the variatio of iversio charge with surface potetial, ad is take as ξ = γ 0/ V 1 + ψ s0, where γ 0 is the body factor at the source, V 1 =1V, ad ψ s0 is the surface potetial at the source. To accout for mobility reductio due to the vertical electrical field, the effective electro mobility is take as [1] μ ch eff = μ ch 0 1+θ 1 V iv0 + θ 2 ( ψs0 ψ s0 VSB=0 ), (3) where θ 1 ad θ 2 are model parameters. Velocity saturatio i the chael regio occurs if I ch =0. (4) VDiS=V sat,ch V DiS By use of (2) ad (3), elaboratio of (4) yields for the saturatio potetial of the chael regio V sat,ch = 2 V iv0 /ξ θ 3 V iv0 /ξ. (5) Subsequetly, we icorporate saturatio i the chael regio curret I ch by takig a effective potetial drop V DiS,eff accordig to [13], which takes the miimum of V DiS ad V sat,ch i a smooth maer. B. Drift regio curret To take velocity saturatio ito accout i the drift regio, its curret is give i a cotiuous way as [14] I dr = W eff ( ) Q dr dv C dx 1+ μdr eff dv C v sat dx, V Di <V C <V D, (6) where eff is the effective electro mobility i the drift regio, Q is the charge desity per uit area, ad V C is the quasi- Fermi potetial i the drift regio. For the drift regio we take both accumulatio ad depletio udereath the thi gate oxide ito accout, so that Q dr = qn D t Sieff Q dr acc Q dr dep, (7) where q is the electro charge, N D is the dopig cocetratio of the drift regio, t Sieff is the effective drift regio thickess (takig ito accout the reductio due to depletio from the p-juctio), Q dr acc is the accumulatio charge per uit area at the surface of the drift regio, ad Q dr dep is the depletio charge per uit area at the surface of the drift regio. Both the accumulatio- ad depletio charge deped o the potetial drop V GC betwee gate ad drift regio, accordig to (see [15]) Q dr ( acc = C ox VGC VFB) dr, (8) valid for V GC >VFB dr, ad (γ ) Q dr dep = γ dr C ox γdr 2 + dr 2 ( ) V GC VFB dr, 2 (9) valid for V GC < VFB dr, respectively. Here, γ dr = 2qɛSi N D /C ox is the body factor of the drift regio, ad VFB dr is the flatbad voltage of the drift regio. Itegratio of (6) from x = L ch to x = L ch + L dr yields I dr = W L dr eff 1+θ dr 3 V DDi VD V Di ( ) Q dr dvc, (10) where θ3 dr = eff /(L drv sat ). I the model, θ3 dr is take as parameter, thus idepedet of the bias coditio. I this way, a sufficietly large value for θ3 dr esures the occurrece of velocity saturatio i the drift regio. Substitutio of (7)-(9) ito (10) yields, uder the assumptio that t Sieff is idepedet of V C, I dr = Wμdr eff C ox L dr ( V dr VC=V Di 1 2 ξdr V D Di 1+θ dr 3 V D Di ) V D Di (11) i which a Taylor expasio / has bee made aroud V C = V Di. Here, V dr = Q dr Cox, so that qn D t Sieff Q dr acc VC=V Di, V GDi >VFB dr C, V dr ox VC=V Di = qn D t Sieff Q dr dep VC=V Di, V GDi <VFB dr C, ox (12)

5 while ξ dr = ( / ) V dr VC VC=V. For simplicity, ξ dr is Di take equal to 1, which is the value i accumulatio. Fially, to accout for mobility reductio due to the vertical electrical field i accumulatio, the effective electro mobility is take as [1] eff = 0 1+θ 1acc ( 1 2 (V GS + V GD ) V dr FB ) (13) where 0 is the zero-field electro mobility i the drift regio. Velocity saturatio i the drift regio occurs if I dr =0. (14) VD Di =V sat,dr V D Di By use of (11) ad (13), elaboratio of (13) yields for the saturatio potetial of the drift regio 2 V dr V sat,dr = VC=V Di. (15) θ3 dr V dr V C=V Di Notice that, i cotrast to the chael regio, the saturatio potetial i the drift regio depeds o the iteral drai potetial V Di. Subsequetly, we icorporate saturatio i the drift regio by takig a effective potetial drop V D Di,eff accordig to [13], which takes the miimum of V D Di ad V sat,dr i a smooth maer. Fig. 4. Measured (symbols) ad modeled (solid lies) drai-to-source curret I DS i the sub-threshold regime, for V SB =0, 1 ad 2 V, for W mask = 20 μm, L PSOD =2.6 μm ad L LOCOS =3.5 μm. IV. RESULTS We have characterized a 60V LDMOS device, with thigate-oxide thickess t ox = 38 m, ad a thick-field-oxide thickess of 0.7 μm. The device is processed i SOItechology [16], ad it has differet mask widths W mask, ad legths L PSOD ad L LOCOS. For the referece device of W mask = 20 μm, L PSOD = 2.6 μm ad L LOCOS = 3.5 μm, the resistace R drift is equal to 330 Ω. I the model, velocity saturatio i the drift regio is obtaied by takig θ3 dr =0.9 V 1. I Fig. 4 we observe that the model describes the subthreshold curret accurately, also at the trasitio from the weak- to strog iversio regime. The reaso for the accurate descriptio i the sub-threshold regime is the formulatio of the fial drai-to-source curret I DS i surface potetials. Furthermore, the iclusio of drai-iduced barrier lowerig yields i this regime a accurate descriptio of the icrease i curret for higher drai voltages. I Fig. 5, we observe that also i the liear regime the model is accurate, eve at high gate voltages where the effect of the gate extedig over the drift regio is sigificat. Thus, by iclusio of the potetial drop across the accumulatio layer i the thi-gate-oxide drift regio, a accurate descriptio is obtaied. I Fig. 6 the drai-to-source curret ad the output coductace are plotted versus drai voltage, for relatively low gate voltages. I this operatig regime the curret is cotrolled by the chael regio, ad saturatio of the curret occurs because the electros i the chael regio reach their saturated drift velocity (see Fig. 9). Notice that i Fig. 6aegative output coductace is obtaied, which clearly demostrates the effect of self-heatig. I the model, the effect of self-heatig is Fig. 5. Measured (symbols) ad modeled (solid lies) drai-to-source curret I DS i the liear operatig regime, for V DS =0.25 V ad V SB =0, 0.5, 1, 1.5 ad 2 V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS = 3.5 μm. icorporated by the temperature depedet model parameters. By subsequet use of a thermal etwork [7], which calculates the temperature rise due to self-heatig, the curret through the device is affected accordigly. I Fig. 7 the measured drai-to-source curret is plotted versus drai voltage, over the whole gate-bias rage; see also Fig. 3. For the high gate voltages, the curret is cotrolled by the drift regio, ad saturatio of the curret occurs because the electros i the drift regio reach their saturated drift velocity (see Fig. 10). As we have see i Fig. 3, MM20 without quasi-saturatio is ot capable of describig the curret correctly at these high gate voltages. By iclusio of quasi-saturatio i MM20, however, we observe i Fig. 7 that a accurate curret descriptio is obtaied, also for the high gate voltages. I Fig. 8 the drai-to-source curret versus gate voltage is plotted. I this figure we clearly see that for high gate voltages the icrease of curret with icreasig gate voltage dimiishes, idicatig agai the oset of quasi-saturatio. Thus, by iclusio of velocity saturatio i the drift regio of MM20, a accurate descriptio is obtaied for the whole rage of bias coditios. To demostrate the effect of velocity saturatio i the drift regio, i Figs 9 ad 10 the iteral potetials of MM20

6 Fig. 7. Measured (symbols) drai-to-source curret I DS i compariso to MOS Model 20 (MM20) icludig quasi-saturatio (solid lies), at V GS = 2.4, 3.4, 4.4, 6, 8, 10 ad 12 V ad V SB =0V, for W mask =20μm, L PSOD =2.6μmad L LOCOS =3.5μm; cf. Fig. 3. By iclusio of quasi-saturatio ito MM20, a accurate descriptio is obtaied, also for the high gate voltages applied. Fig. 6. Measured (symbols) ad modeled (solid lies) drai-to-source curret I DS ad output coductace g DS = I DS / V DS, for V GS =1.4, 2.4, 3.4 ad 4.4 V, ad V SB =0V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS =3.5 μm. icludig quasi-saturatio are plotted versus drai voltage. I Fig. 9 the iteral potetials are give for the relatively low gate voltage V GS = 3.4 V. I this figure we observe that whe the curret saturates, the potetial drop V Di V S over the chael regio exceeds its saturatio potetial V sat,ch. At the oset of saturatio the potetial drop V D V Di over the thi-gate-oxide drift regio, o the other had, is still below its saturatio potetial V sat,dr ; oly for higher drai voltages also the potetial drop over the thi-gate-oxide drift regio exceeds its saturatio potetial. Thus, for V GS =3.4 V firstly the potetial drop of the chael regio exceeds its saturatio potetial, ad the saturatio curret is cotrolled by the chael regio. I Fig. 10 the iteral potetials of MM20 are give for the high gate voltage V GS =12V. I cotrast to Fig. 9, we observe i Fig. 10 that whe the curret saturates, the potetial drop V D V Di over the thi gate-oxide drift regio exceeds its saturatio potetial V sat,dr. The potetial drop V Di V S over the chael regio, o the other had, is sigificatly decreased for V GS =12V compared to the oe for the low gate voltage V GS =3.4 V, ad it remais below its saturatio potetial V sat,ch. Thus, for V GS =12V the saturatio curret is dictated by the thi-gate-oxide drift regio, ad quasisaturatio occurs i the device. Fially, we otice i both Figs 9 ad 10 that i saturatio most of the potetial drop V DS falls across the thi-gate-oxide drift regio. IDS [ma] measuremet MM20 icl quasi sat. VDS = 12 V VDS = 6 V VDS = 3 V VGS [V] Fig. 8. Measured (symbols) drai-to-source curret I DS i compariso to MOS Model 20 (MM20) icludig quasi-saturatio (solid lies), at V DS =3, 6 ad 12 V, ad V SB =0V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS =3.5 μm. Fig. 9. Iteral potetials of MOS Model 20 icludig quasi-saturatio, for V GS =3.4 V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS = 3.5 μm (see also Fig. 7)

7 Fig. 10. Iteral potetials of MOS Model 20 icludig quasi-saturatio, for V GS =12V, for W mask =20μm, L PSOD =2.6 μm ad L LOCOS = 3.5 μm (see also Fig. 7). V. CONCLUSIONS A ew model descriptio of the surface-potetial-based compact LDMOS trasistor model, MOS Model 20, has bee preseted which icludes the effect of quasi-saturatio. By takig velocity saturatio i the drift regio ito accout, a adequate solutio of the iteral drai potetial is obtaied, which esures the curret to be cotrolled by either the chael regio or the drift regio. A compariso with dc measuremets o a 60V LDMOS device shows a very good agreemet, i all operatig regimes ragig from sub-threshold to strog iversio, i both the liear ad saturatio regime. Thus, owig to the iclusio of quasi-saturatio, the ew model ca be successfully used for high-voltage devices, also i the regime of high gate ad high drai bias coditios. I this way, MM20 exteds its applicatio rage from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V. Successful use of the model i circuit simulatios has prove that the iteratio procedure iside the model, used for the calculatio of the iteral drai potetial, is robust ad sufficietly fast. Fially, it is metioed that the source code ad documetatio of the model will become available i the public domai [17]. [8] N.V.T. D Hallewey, J. Beso, W. Redma-White, K. Mistry ad M. Swaeberg, MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Aalogue Circuit Simulatio, IEEE Tras. Computer-Aided Desig Itegrated Circuits ad Systems, pp , [9] Y. Kim, J.G. Fossum ad R.K. Williams, New Physical Isights ad Models for High-Voltage LDMOST IC CAD, IEEE Tras. Electro Devices, Vol. 38, No. 7, pp , [10] Y. Subramaia, P.O. Lauritze ad K.R. Gree, A Compact Model for a IC Lateral Diffused MOSFET Usig Lumped-Charge Methodology, i Proc. Modelig ad Simulatio of Microsystems, pp , [11] Y. Chug, Semi-umerical static model for oplaar-drift lateral DMOS trasistor, IEE Proc. Circuits Devices Syst., Vol. 146, No. 3, pp , [12] R. va Lagevelde ad F.M. Klaasse, A Explicit Surface-potetialbased MOSFET Model for Circuit Simulatio, Solid-State Electroics, Vol. 44, pp , [13] K. Joardar, K.K. Gullapulli, C.C. McAdrew, M.E. Burham ad A. Wild, A improved MOSFET Model for Circuit Simulatio, IEEE Tras. Electro Devices, Vol. 45, No. 1, pp , [14] Y. Tsividis, Operatio ad Modelig of The MOS Trasistor, 2d ed., Mc. Graw-Hill, [15] H.C. de Graaff ad F.M. Klaasse, Compact Trasistor Modellig for Circuit Desig, Spriger-Verlag, [16] J.A. va der Pol et al., A-BCD: A Ecoomic 100V RESURF Silico- O-Isulator BCD Techology for Cosumer ad Automotive Applicatios, i Proc. ISPSD, pp , [17] Iteret: Models. Aemarie C.T. Aarts received the M.Sc. degree i Techical Mathematics i 1992 ad the Ph.D. degree for her research i istabilities i the extrusio of polymers i 1997, both from the Eidhove Uiversity of Techology, Eidhove, The Netherlads. I 1997 she joied Shell Iteratioal Exploratio ad Productio, Rijswijk, The Netherlads. I 1999 she became a seior research scietist with Philips Research Laboratories, Eidhove, The Netherlads, where she worked o high-voltage LDMOS modelig ad characterizatio. Recetly, she has become a Assistat Professor at the Eidhove Uiversity of Techology, where she works o idustrial problems through mathematical modelig. REFERENCES [1] A.C.T. Aarts, N. D Hallewey ad R. va Lagevelde, A Surface- Potetial-Based High-Voltage Compact LDMOS Trasistor Model, IEEE Tras. Electro Devices, Vol. 52, No. 5, pp , [2] M.N. Darwish, Study of the quasi-saturatio effect i VDMOS trasistors, IEEE Tras. Electro Devices, Vol. ED-33, No. 11, pp , [3] H.R. Claesse ad P. va der Zee, A accurate DC Model for High- Voltage Lateral DMOS Trasistors Suited for CACD, Tras. Electro Devices, Vol. ED-33, pp , [4] C.M. Liu, F.C. Shoe ad J.B. Kuo, A Closed-form Physical Back- Gate-Bias Depedet Quasi-saturatio Model for SOI Lateral DMOS Devices with Self-Heatig for Circuit Simulatio, i Proc. ISPSD, pp , [5] J. Victory, C.C. Mc Adrew, R. Thoma, K. Joardar, M. Kiffi, S. Merchat ad D. Mocoqut, A Physically-Based Compact Model for LDMOS Trasistors, i Proc. SISPAD, pp , [6] J. Jag, T. Arborg, Z. Yu ad R.W. Dutto, Circuit Model for Power LDMOS icludig Quasi-Saturatio, i Proc. SISPAD, pp , [7] A.C.T. Aarts, M.J. Swaeberg ad W.J. Kloosterma, Modellig of High-Voltage SOI-LDMOS Trasistors icludig Self-Heatig, i Proc. SISPAD, pp , 20. Willy J. Kloosterma was bor i Olst, The Netherlads, i July He received the B.S. degree i mechaical egieerig from the Techical College i Zwolle, The Netherlads, i I 1974, he joied Philips Research Laboratories Eidhove, The Netherlads. He worked o the dyamical behavior of CRT tubes, powder compactio models, ad sice 1980, o Bipolar ad MOS compact trasistor modelig. A major achievemet is the developmet of the Mextram Bipolar trasistor model. He joied Philips Semicoductors i Nijmege, i 20, ad is ow ivolved i the desig, modelig ad characterizatio of advaced bipolar, CMOS, DMOS, JFET, high voltage ( Volt) ad passive devices. Mr. Kloosterma was a member of the modelig ad characterizatio program committee of the BiPolar /BiCMOS Circuit Techology Meetig (BCTM) i 1998 ad 1999.