Parallel MAC Based On Radix-4 & Radix-8 Booth Encodings

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1 Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST) Parallel MAC Base On Rax-4 & Rax-8 Booth Encongs SHAKE GOEL Stuent, Department of Electroncs & Communcaton Engneerng atonal Insttute of Technology, Kurukshetra er.shankey@gmal.com R.K. SHARMA Faculty, Department of Electroncs & Communcaton Engneerng atonal Insttute of Technology, Kurukshetra malrrks@gmal.com ABSTRACT- Parallel MAC s frequently use n gtal sgnal processng an veo/graphcs applcatons. The MAC proves hgh spee multplcaton an multplcaton wth accumulatve aton. Ths paper presents a combne process of multplcaton an accumulaton base on rax-4 & rax-8 booth encongs. In ths Paper, we nvestgate the metho of mplementng the Parallel MAC wth the smallest possble elay. Enhancng the spee of operaton of the parallel MAC s a major esgn ssue. Ths has been acheve by evelopng a new Rax-5 Kogge stone aer for parallel MAC. Keywors: Rax-4 an Rax-8 base Booth multpler; carry save aer (CSA) tree; computer arthmetc; gtal sgnal processng (DSP); multpler an- accumulator (MAC); Aers.. Introucton In ths paper, we stuy the varous parallel MAC archtectures an then mplement a esgn of parallel MAC base on some booth encongs such as rax-4 & rax-8 booth encoer an some fnal aers such as CLA, Kogge stone aer an then compare ther performance characterstcs. A Dgtal multpler s the funamental component n general purpose mcroprocessor an n DSP [], []. Compare wth many other arthmetc operatons multplcaton s tme consumng an power hungry. Thus enhancng the performance an reucng the power sspaton are the most mportant esgn challenges for all applcatons n whch multpler unt omnate the system performance an power sspaton. The one most effectve way to ncrease the spee of a multpler s to reuce the number of the partal proucts. Although the number of partal proucts can be reuce wth a hgher rax booth encoer, but the number of har multples that are expensve to generate also ncreases smultaneously. To ncrease the spee an performance, many parallel MAC archtectures have been propose. Parallelsm n obtanng partal proucts s the most common technque use n the above mplemente archtecture. There are two common approaches that make use of parallelsm to enhance the multplcaton performance. The frst one s reucng the number of partal prouct rows an secon one s the carry-save-tree technque to reuce multple partal prouct rows as two "carry-save" reunant forms. An archtecture was propose n [4] to prove the tact to merge the fnal aer block to the accumulator regster n the MAC operator to prove the possblty of usng two separate /-bt aers nstea of one -bt aer to accumulate the bt MAC results. The most avance types of MAC has been propose by Elgubaly [8] n whch accumulaton has been combne wth the carry save aer (CSA) tree that compresses partal proucts an thus reuces the crtcal path. Later on a new archtecture for a hgh-spee MAC s propose by Seo an Km [9]. The fference between the two s that the latest one carres out the accumulaton by feeng back the fnal CSA output rather than the fnal aer results. The rest of the paper s organe as follows. In secton secon, an ntroucton to the general MAC s gven along wth basc MAC algorthms. In secton thr, entre process of parallel MAC base on rax-4 an rax-8 booth encongs [7] s explane. Secton four shows mplementaton result an the characterstcs of parallel MAC base on both of the booth encongs. Fnally, the concluson wll be gven n secton fve n whch we prove summary of our propose approach an scuss scope of future extensons.. GEERAL MAC STRUCTURE In ths secton, we scuss basc MAC operaton. Bascally, multpler operaton can be ve nto three operatonal steps. The frst one s booth encong to generate the partal proucts. The secon one s aer array or partal prouct compresson an the last one s fnal aton n whch fnal multplcaton result s prouce. ISS : Vol. o. 8 August 669

2 Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST) If the multplcaton process s extene to accumulate the multple result, then MAC conssts of four steps. General harware archtecture for MAC s shown n Fgure. It executes the multplcaton operaton by multplyng nput multpler an nput multplcan. After that current multplcaton result s ae to the prevous multplcaton result Z as accumulaton step. * Regster (Z) P Fg.. Harware archtecture of general MAC The -bt s complement bnary number can be expresse as y y () If Eq. () s expresse n base-8 type reunant sgn gt form n orer to apply the rax-8 booth s algorthm, t woul be 8 () {±4, ±, ±, ±, } () If Eq. () s expresse n base-4 type reunant sgn gt form n orer to apply the rax-4 booth s algorthm, t woul be 4 (4) {±, ±, } (5) Here refers to the select sgnals for the partal prouct. If Eq. () s use, then multplcaton can be expresse as (6) If these equatons are use, then multplcaton accumulaton result can be expresse as P Z (7) j Here the MAC archtecture mplemente by Eq. (7) s calle stanar esgn.. MAC ARCHITECTURE ow n ths secton we wll erve the expresson for new MAC By usng the stanar esgn, an also wth the help of above mentone results, VLSI archtecture for the new MAC wll be propose.. DERIVATIO OF MAC ARITHMETIC If an operaton of multplcaton of two -bt numbers an accumulatng them nto a -bt number s consere, then the crtcal path s totally etermne by accumulaton operaton. If ppelne scheme s apple for each step, then the elay of last accumulator must be reuce by combnng the accumulaton operaton wth the CSA functon. The aforementone concept s apple to Eq. (7) to express the propose MAC arthmetc. Frst Eq. (6) s ecompose an rearrange, t becomes ISS : Vol. o. 8 August 669

3 ... 6 (8) Eq. (8) can be re-expresse nto equaton (9) by vng t nto frst partal prouct, sum of the mle partal proucts an the last partal prouct. Thus (9) ow Eq. (9) s apple Eq. (7) n whch Z s ve nto upper an lower bts an rearrange Eq. () an Eq. () wll be erve. Z () The secon term can be further separate nto sum an carry terms, thus we get s c () If equatons Eq. (9) an Eq. () are use, then the MAC arthmetc n Eq. (7) can be expresse as c s P () If each term of Eq. () s matche to ts bt poston an rearrange, t can be expresse as Eq. (), whch s the ultmate equaton for the propose MAC. Thus, we get s c P (). MAC ARCHITECTURE The harware archtecture of the propose MAC satsfyng the aforementone equatons s shown n Fgure. The n-bt MAC nputs, an, are converte nto group of partal proucts by passng through the booth encoers base on rax-4 an rax-8 booth algorthms. Fg.. Harware archtecture of propose MAC After that accumulaton s carre out along wth aton of partal proucts n CSA an Accumulator. As a result n-bt S, C an, Z are generate. These three values are fe back an use for accumulaton operaton. P [n-: n] s generate by ang S an C n the fnal aer whch woul be ether CLA (carry look ahea aer) or RCA (rpple carry aer) or Kogge stone aer. At last, by combnng P [n-: n] wth P [n-: ] we get the fnal result. Booth Encoer CSA & Accumulator Fnal Aer P [n-:] P [n-: n] Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST) ISS : Vol. o. 8 August 6694

4 Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST). BOOTH ECODERS The mofe Booth s algorthm base on a rax-4, generally calle Booth- [7] s the most popular approach for mplementng fast multplers usng parallel encong []. It uses a gt set {, ±, ±} to reuce the number of the partal proucts to n = [(n+)/ ]. Rax- 4 encong start by appenng a ero to the rght of multpler LSB. Trplets are taken begnnng at poston x an contnung to the MSB wth one bt overlappng between ajacent trplets. Table. Rax-4 booth encong n+ n n- Z n Partal Prouct Multplcan Multplcan Multplcan - - Multplcan - Multplcan - Multplcan Ths recong scheme apple to a parallel multpler halves the number of partal proucts so the multplcaton tme an the harware requrements ecrease. Rax-8 recong [5], [7] apples the same algorthm as rax-4, but now n ths we take quartets of bts nstea of trplets. The Booth- scheme s base on a rax-8 encong to reuce ths number to n = [(n+)/]. All gt sets {, ±, ±, ±, ±4} are obtane by smple shftng an complementary operatons, except generaton of the multple, whch s compute by an ang an shftng operaton, = + an - can be generate by complement. Rax-4 booth encong that generates partal proucts s shown n Table respectvely..4 PROPOSED CSA AD ACCUMULATOR ARCHITECTURE The archtecture of CSA an accumulator base on rax-4 mofe booth encoer s shown n Fgure whch performs 8 8 bt MAC operaton. In Fgure, s to compensate the s complement number nto s complement, S s to specfy the sgn expanson of the corresponng partal prouct an (~S ) s s complement of S. S[] an C[] correspons to the th bt of the feeback sum an carry whereas Z[] s the th bt of the sum of lower bts for each partal prouct. S [], C [] an Z [] are the prevous result for accumulaton. In aton, P j [] s the th bt of jth partal prouct. Fg.. CSA archtecture for 8-bt MAC base on rax-4 booth encoer Propose CSA conssts of full aers, half aers an carry look ahea aers as shown n Fgure. In ths, seres of CLA aers are use to generate the lower 8-bts of the fnal result. The whte square n Fgure represents an FA an the black square s a half aer (HA). The rectangular symbol wth fve nputs s a -bt CLA wth a carry nput. ISS : Vol. o. 8 August 6695

5 Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST).5 FIAL ADDER Fnal aers are gtal crcuts that compute the aton of varable bnary strngs of equvalent or fferent se. Two types of aer are use for the aton of upper sum an carry bts. These are CLA an rax-4 Kogge stone aer (KSA) []. In carry look-ahea aer, carry sgnal s calculate n avance base on nput sgnals. The result s a reuce carry propagaton tme. The secon aer.e. rax-5 Kogge stone aer s a parallel prefx form carry look ahea aer. In KSA, carres are compute fast by computng them n parallel at the cost of ncrease area but reuce elay. A Parallel Prefx Aer (PPA) s equvalent to the CLA aer. The two ffer n the way ther carry generaton block s mplemente. Rax-5 Kogge stone aer structure an ther symbol representaton are shown n fgure 4 an 5. When large numbers of groups are combne then that n valency 5 group logc the equatons for PG logc are: P : j P : k Pk : lpl l : m Pm : n Pn : j (4) G : j G Pl -: where : k m G or P m-:n : k or P G k-:l m-:n k l m or P k-:l an G n j G n-:j l-:m The sum can therefore be computes usng the followng equaton: or (5) S P G : (6) a 5 b5 a 4 b 4 a b a b a b Pre - processng Cell Fg. 4. Rax-5 Kogge stone aer structure Prefx Cell PP 5 Post - processng Cell PP PP PP 4 Fg. 5. Symbols use n Rax-5 Kogge stone aer Dummy cell 4. EPERIMETAL RESULT The 6 6 bt parallel MAC base on both the booth encongs (.e. Rax-4 booth encong an Rax-8 booth encong) an some fnal aers (such as CLA aer an Rax-5 Kogge stone aer) s esgne n Verlog an the functonaltes of the algorthms are verfe by ILI ISE 8. usng Vrtex p wth CVP7 famly wth FF896 package & -7 spee grae []. Fg. 6. Smulaton result of Ppelne 6-bt MAC base on rax-4 mofe booth encoer ISS : Vol. o. 8 August 6696

6 Shankey Goel. et al. / Internatonal Journal of Engneerng Scence an Technology (IJEST) Smulaton result for the 6-bt parallel MAC base on rax-4 booth encoer an usng Rax-5 Kogge stone as a fnal aer s shown n Fgure 6 respectvely an performance characterstcs n terms of spee an area are shown n table I. It coul be seen from table that the parallel MAC base on Rax-5 Kogge stone aer s havng more area as compare to others but havng less elay. Hgher woul be the no. of slces, hgher woul be area. Thus, MAC base on Rax-5 Kogge stone aer shows hgher performance than others but at the cost of area. Performance Parameters an ther comparson Table. Comparson result of 6-bt parallel MAC MAC usng Rax-4 Booth encong & aer CLA aer Rax-5 Kogge stone aer MAC usng Rax-8 Booth encong & aer CLA aer Rax-5 Kogge stone aer Max. Operatng Frequency(MH) Delay (ns) umber of occupe Slces (4,98) Total equvalent gate count 44 (8%) 4 (8%) 784 (5%) 84 (6%) 5,868 6,96,98, 5. COCLUSIO The prmary objectve of ths thess has been to present a new type of Parallel MAC usng Rax-5 Kogge stone aer, to reuce the mplementaton to practce, an to show through smulaton an esgn that ths algorthm s compettve wth other more commonly use algorthms when use for hgh performance mplementatons. Seconarly, ths thess has shown that algorthms base upon the Rax-4 Booth partal prouct metho are stnctly superor n performance when compare to Rax-8 Booth encoe metho. From above thess, we conclue that Parallel MAC base on Rax-4 booth encoer an usng Rax-5 Kogge stone aer has hgher spee of operaton an thus can be use n hgh performance systems. Ths work can be utle n any of the followng such as n DSP applcatons, umercal co-processor, Calculators (pocket, graphc etc), Flterng, Moulaton & Demoulaton etc. As the summaton networks an partal prouct generaton logc results n hgher elay an most of the area of a MAC. Thus n future, some more technques an avancement nees to be one whch further mproves the performance of MAC. Also some measures shoul be taken whch mnme the area consumpton. REFERECES [] J. J. F. Cavanagh, Dgtal Computer Arthmetc, ew ork: McGraw- Hll, 984. [] O. L. MacSorley, Hgh spee arthmetc n bnary computers, Proc. IRE, vol. 49, pp. 67 9, Jan. 96. [] C. S. Wallace, A suggeston for a fast multpler, IEEE Trans. Electron Comput., vol. EC-, no., pp. 4 7, Feb [4] Faye an M. Bayoum, A merge multpler-accumulator for hgh spee sgnal processng applcaton, Proc. ICASSP, vol., pp. 5,. [5] ajuan He an Chp-Hong Chang, A ew reunant bnary booth encong for fast n -bt multpler esgn, IEEE Transacton on crcut an systems, Vol. 56, o.6, June 9. [6] R. Cooper, Parallel archtecture mofe Booth multpler, Proc. Inst. Electr. Eng. G, vol. 5, pp. 5 8, 988. [7] Marc Hunger an Danel Marenfel, ew self checkng booth multpler, Int. J. Appl. Math, Comput. Sc., Vol.8, o., 9 8, 8. [8] F. Elgubaly, A fast parallel multpler accumulator usng the mofe Booth algorthm, IEEE Trans. Crcuts Syst., vol. 7, no. 9, pp. 9 98, Sep.. [9] oung-ho Seo an Dong-Wook Km, A ew VLSI Archtecture of Parallel Multpler Accumulator Base on Rax- Mofe Booth Algorthm, IEEE trans. on VLSI Systems, Vol.8 o., Feb.. R. [] E. Laner an M. J. Fscher, Parallel Prefx Computaton, Journal of the ACM, vol.7, o.4, October 98, [] Vrtex generaton confguraton user gue, Vrtex-II Pro FPGA famles, DS8- (v.) January,, avalable at ISS : Vol. o. 8 August 6697