CIRCUIT THEOREMS. Enhancing Your Career

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1 C H A P T E R CIRCUIT THEOREMS 4 Our schools hd etter get on with wht is their overwhelmingly most importnt tsk: teching their chrges to express themselves clerly nd with precision in oth speech nd writing; in other words, leding them towrd mstery of their own lnguge. Filing tht, ll their instruction in mthemtics nd science is wste of time. Joseph Weizenum, M.I.T. Enhncing Your Creer Enhncing Your Communiction Skill Tking course in circuit nlysis is one step in prepring yourself for creer in electricl engineering. Enhncing your communiction skill while in school should lso e prt of tht preprtion, s lrge prt of your time will e spent communicting. People in industry hve complined gin nd gin tht grduting engineers re ill-prepred in written nd orl communiction. An engineer who communictes effectively ecomes vlule sset. You cn proly spek or write esily nd quickly. But how effectively do you communicte? The rt of effective communiction is of the utmost importnce to your success s n engineer. For engineers in industry, communiction is key to promotility. Consider the result of survey of U.S. corportions tht sked wht fctors influence mngeril promotion. The survey includes listing of 22 personl qulities nd their importnce in dvncement. You my e surprised to note tht technicl skill sed on experience plced fourth from the ottom. Attriutes such s self-confidence, mition, flexiility, mturity, ility to mke sound decisions, getting things done with nd through people, nd cpcity for hrd work ll rnked higher. At the top of the list ws ility to communicte. The higher your professionl creer progresses, the more you will need to communicte. Therefore, you should regrd effective communiction s n importnt tool in your engineering tool chest. Lerning to communicte effectively is lifelong tsk you should lwys work towrd. The est time to egin is while still in school. Continully look for opportunities to develop nd strengthen your reding, writing, listening, Working nd getting long with people Aility to work hrd Prolem-solving skills Appernce Mturity Effective communiction Selfdetermintion College eduction Aility to communicte effectively is regrded y mny s the most importnt step to n executive promotion. (Adpted from J. Sherlock, A Guide to Technicl Communiction. Boston, MA: Allyn nd Bcon, 1985, p. 7.) nd speking skills. You cn do this through clssroom presenttions, tem projects, ctive prticiption in student orgniztions, nd enrollment in communiction courses. The risks re less now thn lter in the workplce. 119

2 120 PART 1 DC Circuits 4.1 INTRODUCTION A mjor dvntge of nlyzing circuits using Kirchhoff s lws s we did in Chpter 3 is tht we cn nlyze circuit without tmpering with its originl configurtion. A mjor disdvntge of this pproch is tht, for lrge, complex circuit, tedious computtion is involved. The growth in res of ppliction of electric circuits hs led to n evolution from simple to complex circuits. To hndle the complexity, engineers over the yers hve developed some theorems to simplify circuit nlysis. Such theorems include Thevenin s nd Norton s theorems. Since these theorems re pplicle to liner circuits, we first discuss the concept of circuit linerity. In ddition to circuit theorems, we discuss the concepts of superposition, source trnsformtion, nd mximum power trnsfer in this chpter. The concepts we develop re pplied in the lst section to source modeling nd resistnce mesurement. 4.2 LINEARITY PROPERTY Linerity is the property of n element descriing liner reltionship etween cuse nd effect. Although the property pplies to mny circuit elements, we shll limit its pplicility to resistors in this chpter. The property is comintion of oth the homogeneity (scling) property nd the dditivity property. The homogeneity property requires tht if the input (lso clled the excittion) is multiplied y constnt, then the output (lso clled the response) is multiplied y the sme constnt. For resistor, for exmple, Ohm s lw reltes the input i to the output v, v = ir (4.1) If the current is incresed y constnt k, then the voltge increses correspondingly y k, tht is, kir = kv (4.2) The dditivity property requires tht the response to sum of inputs is the sum of the responses to ech input pplied seprtely. Using the voltge-current reltionship of resistor, if nd then pplying (i 1 i 2 ) gives v 1 = i 1 R v 2 = i 2 R (4.3) (4.3) v = (i 1 i 2 )R = i 1 R i 2 R = v 1 v 2 (4.4) We sy tht resistor is liner element ecuse the voltge-current reltionship stisfies oth the homogeneity nd the dditivity properties. In generl, circuit is liner if it is oth dditive nd homogeneous. A liner circuit consists of only liner elements, liner dependent sources, nd independent sources.

3 CHAPTER 4 Circuit Theorems 121 A liner circuit is one whose output is linerly relted (or directly proportionl) to its input. Throughout this ook we consider only liner circuits. Note tht since p = i 2 R = v 2 /R (mking it qudrtic function rther thn liner one), the reltionship etween power nd voltge (or current) is nonliner. Therefore, the theorems covered in this chpter re not pplicle to power. To understnd the linerity principle, consider the liner circuit shown in Fig The liner circuit hs no independent sources inside it. It is excited y voltge source v s, which serves s the input. The circuit is terminted y lod R. We my tke the current i through R s the output. Suppose v s = 10 V gives i = 2 A. According to the linerity principle, v s = 1 V will give i = 0.2 A. By the sme token, i = 1mA must e due to v s = 5mV. v s Figure 4.1 Liner circuit A liner circuit with input v s nd output i. R i E X A M P L E 4. 1 For the circuit in Fig. 4.2, find i o when v s = 12 V nd v s = 24 V. Solution: Applying KVL to the two loops, we otin 12i 1 4i 2 v s = 0 (4.1.1) 4i 1 16i 2 3v x v s = 0 (4.1.2) But v x = 2i 1. Eqution (4.1.2) ecomes 10i 1 16i 2 v s = 0 (4.1.3) Adding Eqs. (4.1.1) nd (4.1.3) yields 2i 1 12i 2 = 0 i 1 =6i 2 Sustituting this in Eq. (4.1.1), we get 76i 2 v s = 0 i 2 = v s 76 When v s = 12 V, i o = i 2 = A When v s = 24 V, i o = i 2 = A showing tht when the source vlue is douled, i o doules. P R A C T I C E P R O B L E M Ω v x i 1 i 2 v s Figure 4.2 For Exmple 4.1. i o 3v x For the circuit in Fig. 4.3, find v o when i s = 15 nd i s = 30 A. Answer: 10 V, 20 V. i s v o Figure 4.3 For Prctice Pro. 4.1.

4 122 PART 1 DC Circuits E X A M P L E 4. 2 Assume I o = 1 A nd use linerity to find the ctul vlue of I o in the circuit in Fig I 2 4 V 2 I 2 1 V 1 3 Ω I 3 I 1 I o I s = 15 A 7 Ω 5 Ω Figure 4.4 For Exmple 4.2. P R A C T I C E P R O B L E M 4. 2 Solution: If I o = 1 A, then V 1 = (3 5)I o = 8 V nd I 1 = V 1 /4 = 2 A. Applying KCL t node 1 gives I 2 = I 1 I o = 3A V 2 = V 1 2I 2 = 8 6 = 14 V, I 3 = V 2 7 = 2A Applying KCL t node 2 gives I 4 = I 3 I 2 = 5A Therefore, I s = 5 A. This shows tht ssuming I o = 1givesI s = 5A; the ctul source current of 15 A will give I o = 3 A s the ctul vlue. 10 V 1 5 Ω 8 Ω V o Assume tht V o = 1 V nd use linerity to clculte the ctul vlue of V o in the circuit of Fig Answer: 4V. Figure 4.5 For Prctice Pro SUPERPOSITION If circuit hs two or more independent sources, one wy to determine the vlue of specific vrile (voltge or current) is to use nodl or mesh nlysis s in Chpter 3. Another wy is to determine the contriution of ech independent source to the vrile nd then dd them up. The ltter pproch is known s the superposition.

5 CHAPTER 4 Circuit Theorems 123 The ide of superposition rests on the linerity property. The superposition principle sttes tht the voltge cross (or current through) n element in liner circuit is the lgeric sum of the voltges cross (or currents through) tht element due to ech independent source cting lone. Superposition is not limited to circuit nlysis ut is pplicle in mny fields where cuse nd effect er liner reltionship to one nother. The principle of superposition helps us to nlyze liner circuit with more thn one independent source y clculting the contriution of ech independent source seprtely. However, to pply the superposition principle, we must keep two things in mind: 1. We consider one independent source t time while ll other independent sources re turned off. This implies tht we replce every voltge source y 0 V (or short circuit), nd every current source y 0 A (or n open circuit). This wy we otin simpler nd more mngele circuit. 2. Dependent sources re left intct ecuse they re controlled y circuit vriles. With these in mind, we pply the superposition principle in three steps: Steps to Apply Superposition Principle: 1. Turn off ll independent sources except one source. Find the output (voltge or current) due to tht ctive source using nodl or mesh nlysis. 2. Repet step 1 for ech of the other independent sources. 3. Find the totl contriution y dding lgericlly ll the contriutions due to the independent sources. Anlyzing circuit using superposition hs one mjor disdvntge: it my very likely involve more work. If the circuit hs three independent sources, we my hve to nlyze three simpler circuits ech providing the contriution due to the respective individul source. However, superposition does help reduce complex circuit to simpler circuits through replcement of voltge sources y short circuits nd of current sources y open circuits. Keep in mind tht superposition is sed on linerity. For this reson, it is not pplicle to the effect on power due to ech source, ecuse the power sored y resistor depends on the squre of the voltge or current. If the power vlue is needed, the current through (or voltge cross) the element must e clculted first using superposition. Other terms such s killed, mde inctive, dedened, orset equl to zero re often used to convey the sme ide. For exmple, when current i 1 flows through resistor R, the power is p 1 = Ri 2 1, nd when current i 2 flows through R, the power is p 2 = Ri 2 2.Ifcurrent i 1 i 2 flows through R, the power sored is p 3 = R(i 1 i 2 ) 2 = Ri 2 1 Ri2 2 2Ri 1i 2 p 1 p 2. Thus, the power reltion is nonliner. E X A M P L E 4. 3 Use the superposition theorem to find v in the circuit in Fig Solution: Since there re two sources, let v = v 1 v 2 where v 1 nd v 2 re the contriutions due to the 6-V voltge source nd 8 Ω 6 V v 3 A Figure 4.6 For Exmple 4.3.

6 124 PART 1 DC Circuits 8 Ω 6 V i 1 8 Ω () i 2 i 3 v 2 () v 1 Figure 4.7 For Exmple 4.3: () clculting v 1, () clculting v 2. 3 A the 3-A current source, respectively. To otin v 1, we set the current source to zero, s shown in Fig. 4.7(). Applying KVL to the loop in Fig. 4.7() gives Thus, 12i 1 6 = 0 i 1 = 0.5 A v 1 = 4i 1 = 2V We my lso use voltge division to get v 1 y writing v 1 = 4 (6) = 2V 4 8 To get v 2, we set the voltge source to zero, s in Fig. 4.7(). Using current division, i 3 = 8 (3) = 2A 4 8 Hence, And we find v 2 = 4i 3 = 8V v = v 1 v 2 = 2 8 = 10 V P R A C T I C E P R O B L E M Ω 5 Ω Using the superposition theorem, find v o in the circuit in Fig Answer: 12 V. v o 8 A 20 V Figure 4.8 For Prctice Pro E X A M P L E A 3 Ω 5 Ω 5i o 1 Ω i o 20 V Find i o in the circuit in Fig. 4.9 using superposition. Solution: The circuit in Fig. 4.9 involves dependent source, which must e left intct. We let i o = i o i o (4.4.1) where i o nd i o re due to the 4-A current source nd 20-V voltge source respectively. To otin i o, we turn off the 20-V source so tht we hve the circuit in Fig. 4.10(). We pply mesh nlysis in order to otin i o. For loop 1, Figure 4.9 For Exmple 4.4. i 1 = 4A (4.4.2)

7 CHAPTER 4 Circuit Theorems A 3 Ω i 2 i 1 1 Ω 5i o 3 Ω i o 1 Ω i 4 5i o 5 Ω i 1 i o i 3 0 () i 3 5 Ω i 5 20 V () Figure 4.10 For Exmple 4.4: Applying superposition to () otin i 0, () otin i 0. For loop 2, 3i 1 6i 2 1i 3 5i o = 0 (4.4.3) For loop 3, 5i 1 1i 2 10i 3 5i o = 0 (4.4.4) But t node 0, i 3 = i 1 i o = 4 i o (4.4.5) Sustituting Eqs. (4.4.2) nd (4.4.5) into Eqs. (4.4.3) nd (4.4.4) gives two simultneous equtions which cn e solved to get 3i 2 2i o = 8 (4.4.6) i 2 5i o = 20 (4.4.7) i o = A (4.4.8) To otin i o, we turn off the 4-A current source so tht the circuit ecomes tht shown in Fig. 4.10(). For loop 4, KVL gives nd for loop 5, 6i 4 i 5 5i o = 0 (4.4.9) i 4 10i i o = 0 (4.4.10) But i 5 =i o. Sustituting this in Eqs. (4.4.9) nd (4.4.10) gives which we solve to get 6i 4 4i o (4.4.11) i 4 5i o =20 (4.4.12)

8 126 PART 1 DC Circuits i o =60 17 A (4.4.13) Now sustituting Eqs. (4.4.8) nd (4.4.13) into Eq. (4.4.1) gives i o = 8 17 = A P R A C T I C E P R O B L E M Ω 10 V 2 A v x 0.1v x Use superposition to find v x in the circuit in Fig Answer: v x = 12.5 V. Figure 4.11 For Prctice Pro E X A M P L E V 8 Ω i For the circuit in Fig. 4.12, use the superposition theorem to find i. Solution: In this cse, we hve three sources. Let i = i 1 i 2 i 3 12 V 3 Ω 3 A Figure 4.12 For Exmple 4.5. where i 1,i 2, nd i 3 re due to the 12-V, 24-V, nd 3-A sources respectively. To get i 1, consider the circuit in Fig. 4.13(). Comining 4 (on the righthnd side) in series with 8 gives 12. The 12 in prllel with 4 gives 12 4/16 = 3. Thus, i 1 = 12 6 = 2A To get i 2, consider the circuit in Fig. 4.13(). Applying mesh nlysis, 16i 4i 24 = 0 4i i =6 (4.5.1) 7i 4i = 0 i = 7 4 i (4.5.2) Sustituting Eq. (4.5.2) into Eq. (4.5.1) gives i 2 = i =1 To get i 3, consider the circuit in Fig. 4.13(c). Using nodl nlysis, 3 = v 2 8 v 2 v 1 4 v 2 v 1 4 = v 1 4 v = 3v 2 2v 1 (4.5.3) v 2 = 10 3 v 1 (4.5.4) Sustituting Eq. (4.5.4) into Eq. (4.5.3) leds to v 1 = 3 nd

9 CHAPTER 4 Circuit Theorems Ω 3 Ω i 2 i 1 12 V 3 Ω 12 V 3 Ω () 24 V 8 Ω 8 Ω i v 1 v 2 i 2 i 2 i 3 Ω 3 Ω 3 A () (c) Figure 4.13 For Exmple 4.5. Thus, i 3 = v 1 3 = 1A i = i 1 i 2 i 3 = = 2A P R A C T I C E P R O B L E M 4. 5 Find i in the circuit in Fig using the superposition principle. i 8 Ω 16 V 4 A 12 V Answer: 0.75 A. Figure 4.14 For Prctice Pro SOURCE TRANSFORMATION We hve noticed tht series-prllel comintion nd wye-delt trnsformtion help simplify circuits. Source trnsformtion is nother tool for simplifying circuits. Bsic to these tools is the concept of equivlence.

10 128 PART 1 DC Circuits We recll tht n equivlent circuit is one whose v-i chrcteristics re identicl with the originl circuit. In Section 3.6, we sw tht node-voltge (or mesh-current) equtions cn e otined y mere inspection of circuit when the sources re ll independent current (or ll independent voltge) sources. It is therefore expedient in circuit nlysis to e le to sustitute voltge source in series with resistor for current source in prllel with resistor, or vice vers, s shown in Fig Either sustitution is known s source trnsformtion. R v s i s R Figure 4.15 Trnsformtion of independent sources. A source trnsformtion is the process of replcing voltge source v s in series with resistor R y current source i s in prllel with resistor R, or vice vers. The two circuits in Fig re equivlent provided they hve the sme voltge-current reltion t terminls -. It is esy to show tht they re indeed equivlent. If the sources re turned off, the equivlent resistnce t terminls - in oth circuits is R. Also, when terminls - re shortcircuited, the short-circuit current flowing from to is i sc = v s /R in the circuit on the left-hnd side nd i sc = i s for the circuit on the righthnd side. Thus, v s /R = i s in order for the two circuits to e equivlent. Hence, source trnsformtion requires tht v s = i s R or i s = v s (4.5) R Source trnsformtion lso pplies to dependent sources, provided we crefully hndle the dependent vrile. As shown in Fig. 4.16, dependent voltge source in series with resistor cn e trnsformed to dependent current source in prllel with the resistor or vice vers. R v s i s R Figure 4.16 Trnsformtion of dependent sources. Like the wye-delt trnsformtion we studied in Chpter 2, source trnsformtion does not ffect the remining prt of the circuit. When

11 CHAPTER 4 Circuit Theorems 129 pplicle, source trnsformtion is powerful tool tht llows circuit mnipultions to ese circuit nlysis. However, we should keep the following points in mind when deling with source trnsformtion. 1. Note from Fig (or Fig. 4.16) tht the rrow of the current source is directed towrd the positive terminl of the voltge source. 2. Note from Eq. (4.5) tht source trnsformtion is not possile when R = 0, which is the cse with n idel voltge source. However, for prcticl, nonidel voltge source, R 0. Similrly, n idel current source with R = cnnot e replced y finite voltge source. More will e sid on idel nd nonidel sources in Section E X A M P L E 4. 6 Use source trnsformtion to find v o in the circuit in Fig Ω Solution: We first trnsform the current nd voltge sources to otin the circuit in 3 A 8 Ω v o Fig. 4.18(). Comining the 4- nd 2- resistors in series nd trnsforming the 12-V voltge source gives us Fig. 4.18(). We now comine the 3- nd 6- resistors in prllel to get 2-. We lso comine the 2-A nd 4-A current sources to get 2-A source. Thus, y repetedly Figure 4.17 For Exmple 4.6. pplying source trnsformtions, we otin the circuit in Fig. 4.18(c). 12 V 12 V 8 Ω v o 3 Ω 4 A () 2 A i 8 Ω v o 3 Ω 4 A 8 Ω v o 2 A () (c) Figure 4.18 For Exmple 4.6. We use current division in Fig. 4.18(c) to get nd i = 2 (2) = v o = 8i = 8(0.4) = 3.2 V

12 130 PART 1 DC Circuits P R A C T I C E P R O B L E M 4. 6 Alterntively, since the 8- nd 2- resistors in Fig. 4.18(c) re in prllel, they hve the sme voltge v o cross them. Hence, v o = (8 2)(2 A) = 8 2 (2) = 3.2 V 10 Find i o in the circuit of Fig using source trnsformtion. 5 V i o 1 Ω 5 A 3 Ω 7 Ω 3 A Figure 4.19 For Prctice Pro Answer: 1.78 A. E X A M P L E v x 6 V v x 18 V Figure 4.20 For Exmple 4.7. Find v x in Fig using source trnsformtion. Solution: The circuit in Fig involves voltge-controlled dependent current source. We trnsform this dependent current source s well s the 6-V independent voltge source s shown in Fig. 4.21(). The 18-V voltge source is not trnsformed ecuse it is not connected in series with ny resistor. The two 2- resistors in prllel comine to give 1- resistor, which is in prllel with the 3-A current source. The current is trnsformed to voltge source s shown in Fig. 4.21(). Notice tht the terminls for v x re intct. Applying KVL round the loop in Fig. 4.21() gives 3 5i v x 18 = 0 (4.7.1) 3 A v x 18 V 3 V 1 Ω v x i v x 18 V () () Figure 4.21 For Exmple 4.7: Applying source trnsformtion to the circuit in Fig

13 CHAPTER 4 Circuit Theorems 131 Applying KVL to the loop contining only the 3-V voltge source, the 1- resistor, nd v x yields 3 1i v x = 0 v x = 3 i (4.7.2) Sustituting this into Eq. (4.7.1), we otin 15 5i 3 i = 0 i =4.5 A Alterntively, we my pply KVL to the loop contining v x, the 4- resistor, the voltge-controlled dependent voltge source, nd the 18-V voltge source in Fig. 4.21(). We otin v x 4i v x 18 = 0 i =4.5 A Thus, v x = 3 i = 7.5V. P R A C T I C E P R O B L E M 4. 7 Use source trnsformtion to find i x in the circuit shown in Fig Answer: A. i x 4 A 10 Ω 5 Ω 2i x Figure 4.22 For Prctice Pro THEVENIN S THEOREM It often occurs in prctice tht prticulr element in circuit is vrile (usully clled the lod) while other elements re fixed. As typicl exmple, household outlet terminl my e connected to different pplinces constituting vrile lod. Ech time the vrile element is chnged, the entire circuit hs to e nlyzed ll over gin. To void this prolem, Thevenin s theorem provides technique y which the fixed prt of the circuit is replced y n equivlent circuit. According to Thevenin s theorem, the liner circuit in Fig. 4.23() cn e replced y tht in Fig. 4.23(). (The lod in Fig my e single resistor or nother circuit.) The circuit to the left of the terminls - in Fig. 4.23() is known s the Thevenin equivlent circuit; it ws developed in 1883 y M. Leon Thevenin ( ), French telegrph engineer. Thevenin s theorem sttes tht liner two-terminl circuit cn e replced y n equivlent circuit consisting of voltge source V Th in series with resistor R Th, where V Th is the open-circuit voltge t the terminls nd R Th is the input or equivlent resistnce t the terminls when the independent sources re turned off. V Th Liner two-terminl circuit Figure 4.23 R Th () I I () V V Lod Lod Replcing liner two-terminl circuit y its Thevenin equivlent: () originl circuit, () the Thevenin equivlent circuit. The proof of the theorem will e given lter, in Section 4.7. Our mjor concern right now is how to find the Thevenin equivlent voltge

14 132 PART 1 DC Circuits V Th nd resistnce R Th. To do so, suppose the two circuits in Fig re equivlent. Two circuits re sid to e equivlent if they hve the sme voltge-current reltion t their terminls. Let us find out wht will mke the two circuits in Fig equivlent. If the terminls - re mde open-circuited (y removing the lod), no current flows, so tht the open-circuit voltge cross the terminls - in Fig. 4.23() must e equl to the voltge source V Th in Fig. 4.23(), since the two circuits re equivlent. Thus V Th is the open-circuit voltge cross the terminls s shown in Fig. 4.24(); tht is, V Th = v oc (4.6) Liner two-terminl circuit v oc Liner circuit with ll independent sources set equl to zero R in V Th = v oc R Th = R in () () Figure 4.24 Finding V Th nd R Th. Circuit with ll independent sources set equl to zero v o R Th = i o () Circuit with ll independent sources set equl to zero Figure 4.25 R Th = v o i o () v o i o v o i o Finding R Th when circuit hs dependent sources. Lter we will see tht n lterntive wy of finding R Th is R Th = v oc /i sc. Agin, with the lod disconnected nd terminls - open-circuited, we turn off ll independent sources. The input resistnce (or equivlent resistnce) of the ded circuit t the terminls - in Fig. 4.23() must e equl to R Th in Fig. 4.23() ecuse the two circuits re equivlent. Thus, R Th is the input resistnce t the terminls when the independent sources re turned off, s shown in Fig. 4.24(); tht is, R Th = R in (4.7) To pply this ide in finding the Thevenin resistnce R Th, we need to consider two cses. CASE 1 If the network hs no dependent sources, we turn off ll independent sources. R Th is the input resistnce of the network looking etween terminls nd, s shown in Fig. 4.24(). CASE 2 If the network hs dependent sources, we turn off ll independent sources. As with superposition, dependent sources re not to e turned off ecuse they re controlled y circuit vriles. We pply voltge source v o t terminls nd nd determine the resulting current i o. Then R Th = v o /i o, s shown in Fig. 4.25(). Alterntively, we my insert current source i o t terminls - s shown in Fig. 4.25() nd find the terminl voltge v o. Agin R Th = v o /i o. Either of the two pproches will give the sme result. In either pproch we my ssume ny vlue of v o nd i o. For exmple, we my use v o = 1Vori o = 1A, or even use unspecified vlues of v o or i o. It often occurs tht R Th tkes negtive vlue. In this cse, the negtive resistnce (v =ir) implies tht the circuit is supplying power.

15 CHAPTER 4 Circuit Theorems 133 This is possile in circuit with dependent sources; Exmple 4.10 will illustrte this. Thevenin s theorem is very importnt in circuit nlysis. It helps simplify circuit. A lrge circuit my e replced y single independent voltge source nd single resistor. This replcement technique is powerful tool in circuit design. As mentioned erlier, liner circuit with vrile lod cn e replced y the Thevenin equivlent, exclusive of the lod. The equivlent network ehves the sme wy externlly s the originl circuit. Consider liner circuit terminted y lod R L, s shown in Fig. 4.26(). The current I L through the lod nd the voltge V L cross the lod re esily determined once the Thevenin equivlent of the circuit t the lod s terminls is otined, s shown in Fig. 4.26(). From Fig. 4.26(), we otin V Th Liner circuit R Th () I L R L I L R L I L = (4.8) R Th R L R L V L = R L I L = V Th (4.8) R Th R L Note from Fig. 4.26() tht the Thevenin equivlent is simple voltge divider, yielding V L y mere inspection. V Th Figure 4.26 () A circuit with lod: () originl circuit, () Thevenin equivlent. E X A M P L E 4. 8 Find the Thevenin equivlent circuit of the circuit shown in Fig. 4.27, to the left of the terminls -. Then find the current through R L = 6, 16, nd 36. Solution: We find R Th y turning off the 32-V voltge source (replcing it with short circuit) nd the 2-A current source (replcing it with n open circuit). The circuit ecomes wht is shown in Fig. 4.28(). Thus, R Th = = = Ω 32 V 1 2 A Figure 4.27 For Exmple 4.8. R L 1 Ω V Th 1 Ω 1 R Th 32 V i 1 1 i 2 2 A V Th () () Figure 4.28 For Exmple 4.8: () finding R Th, () finding V Th. To find V Th, consider the circuit in Fig. 4.28(). Applying mesh nlysis to the two loops, we otin 32 4i 1 12(i 1 i 2 ) = 0, i 2 =2A

16 134 PART 1 DC Circuits Solving for i 1,wegeti 1 = 0.5 A. Thus, V Th = 12(i 1 i 2 ) = 12( ) = 30 V Alterntively, it is even esier to use nodl nlysis. We ignore the 1- resistor since no current flows through it. At the top node, KCL gives or 32 V Th 4 2 = V Th V Th 24 = V Th V Th = 30 V i L 30 V R L Figure 4.29 The Thevenin equivlent circuit for Exmple 4.8. s otined efore. We could lso use source trnsformtion to find V Th. The Thevenin equivlent circuit is shown in Fig The current through R L is When R L = 6, When R L = 16, When R L = 36, I L = V Th = 30 R Th R L 4 R L I L = = 3A I L = = 1.5 A I L = = 0.75 A P R A C T I C E P R O B L E M 4. 8 Using Thevenin s theorem, find the equivlent circuit to the left of the terminls in the circuit in Fig Then find i. 12 V 2 A i 1 Ω Figure 4.30 For Prctice Pro Answer: V Th = 6V,R Th = 3,i = 1.5 A. E X A M P L E 4. 9 Find the Thevenin equivlent of the circuit in Fig

17 CHAPTER 4 Circuit Theorems 135 Solution: This circuit contins dependent source, unlike the circuit in the previous exmple. To find R Th, we set the independent source equl to zero ut leve the dependent source lone. Becuse of the presence of the dependent source, however, we excite the network with voltge source v o connected to the terminls s indicted in Fig. 4.32(). We my set v o = 1 V to ese clcultion, since the circuit is liner. Our gol is to find the current i o through the terminls, nd then otin R Th = 1/i o. (Alterntively, we my insert 1-A current source, find the corresponding voltge v o, nd otin R Th = v o /1.) 2v x 5 A v x Figure 4.31 For Exmple v x 2v x i 1 i 3 i o v x i v o = 1 V 5 A 2 i i v x 3 1 i 2 () () v oc Figure 4.32 Finding R Th nd V Th for Exmple 4.9. in Applying mesh nlysis to loop 1 in the circuit in Fig. 4.32() results 2v x 2(i 1 i 2 ) = 0 or v x = i 1 i 2 But 4i 2 = v x = i 1 i 2 ; hence, For loops 2 nd 3, pplying KVL produces Solving these equtions gives But i o =i 3 = 1/6 A. Hence, i 1 =3i 2 (4.9.1) 4i 2 2(i 2 i 1 ) 6(i 2 i 3 ) = 0 (4.9.2) 6(i 3 i 2 ) 2i 3 1 = 0 (4.9.3) i 3 = 1 6 A R Th = 1V i o = 6 To get V Th,wefind v oc in the circuit of Fig. 4.32(). Applying mesh nlysis, we get

18 136 PART 1 DC Circuits i 1 = 5 (4.9.4) 2v x 2(i 3 i 2 ) = 0 v x = i 3 i 2 (4.9.5) 4(i 2 i 1 ) 2(i 2 i 3 ) 6i 2 = 0 or 20 V 12i 2 4i 1 2i 3 = 0 (4.9.6) But 4(i 1 i 2 ) = v x. Solving these equtions leds to i 2 = 10/3. Hence, Figure 4.33 The Thevenin equivlent of the circuit in Fig V Th = v oc = 6i 2 = 20 V The Thevenin equivlent is s shown in Fig P R A C T I C E P R O B L E M V 5 Ω I x 3 Ω 1.5I x Find the Thevenin equivlent circuit of the circuit in Fig to the left of the terminls. Answer: V Th = 5.33 V, R Th = Figure 4.34 For Prctice Pro E X A M P L E i x v o () i x Determine the Thevenin equivlent of the circuit in Fig. 4.35(). Solution: Since the circuit in Fig. 4.35() hs no independent sources, V Th = 0V. To find R Th, it is est to pply current source i o t the terminls s shown in Fig. 4.35(). Applying nodl nlysis gives i o i x = 2i x v o 4 (4.10.1) i x But 2i x i o i x = 0 v o 2 = v o 2 (4.10.2) () Figure 4.35 For Exmple Sustituting Eq. (4.10.2) into Eq. (4.10.1) yields Thus, i o = i x v o 4 =v o 2 v o 4 =v o 4 or v o =4i o R Th = v o i o =4 The negtive vlue of the resistnce tells us tht, ccording to the pssive sign convention, the circuit in Fig. 4.35() is supplying power. Of course, the resistors in Fig. 4.35() cnnot supply power (they sor power); it

19 CHAPTER 4 Circuit Theorems 137 is the dependent source tht supplies the power. This is n exmple of how dependent source nd resistors could e used to simulte negtive resistnce. P R A C T I C E P R O B L E M Otin the Thevenin equivlent of the circuit in Fig Answer: V Th = 0V,R Th =7.5. v x 4v x 10 Ω 5 Ω 15 Ω Figure 4.36 For Prctice Pro NORTON S THEOREM In 1926, out 43 yers fter Thevenin pulished his theorem, E. L. Norton, n Americn engineer t Bell Telephone Lortories, proposed similr theorem. Norton s theorem sttes tht liner two-terminl circuit cn e replced y n equivlent circuit consisting of current source I N in prllel with resistor R N, where I N is the short-circuit current through the terminls nd R N is the input or equivlent resistnce t the terminls when the independent sources re turned off. Thus, the circuit in Fig. 4.37() cn e replced y the one in Fig. 4.37(). The proof of Norton s theorem will e given in the next section. For now, we re minly concerned with how to get R N nd I N.Wefind R N in the sme wy we find R Th. In fct, from wht we know out source trnsformtion, the Thevenin nd Norton resistnces re equl; tht is, R N = R Th (4.9) To find the Norton current I N, we determine the short-circuit current flowing from terminl to in oth circuits in Fig It is evident tht the short-circuit current in Fig. 4.37() is I N. This must e the sme short-circuit current from terminl to in Fig. 4.37(), since the two circuits re equivlent. Thus, I N = i sc (4.10) shown in Fig Dependent nd independent sources re treted the sme wy s in Thevenin s theorem. Oserve the close reltionship etween Norton s nd Thevenin s theorems: R N = R Th s in Eq. (4.9), nd I N = V Th R Th (4.11) I N Figure 4.37 Liner two-terminl circuit () () R N () Originl circuit, () Norton equivlent circuit. Liner two-terminl circuit Figure 4.38 Finding Norton current I N. i sc = I N

20 138 PART 1 DC Circuits The Thevenin nd Norton equivlent circuits re relted y source trnsformtion. This is essentilly source trnsformtion. For this reson, source trnsformtion is often clled Thevenin-Norton trnsformtion. Since V Th, I N, nd R Th re relted ccording to Eq. (4.11), to determine the Thevenin or Norton equivlent circuit requires tht we find: The open-circuit voltge v oc cross terminls nd. The short-circuit current i sc t terminls nd. The equivlent or input resistnce R in t terminls nd when ll independent sources re turned off. We cn clculte ny two of the three using the method tht tkes the lest effort nd use them to get the third using Ohm s lw. Exmple 4.11 will illustrte this. Also, since V Th = v oc I N = i sc (4.12) (4.12) R Th = v oc = R N (4.12c) i sc the open-circuit nd short-circuit tests re sufficient to find ny Thevenin or Norton equivlent. E X A M P L E Ω 2 A 12 V 8 Ω Figure 4.39 For Exmple Ω Find the Norton equivlent circuit of the circuit in Fig Solution: We find R N in the sme wy we find R Th in the Thevenin equivlent circuit. Set the independent sources equl to zero. This leds to the circuit in Fig. 4.40(), from which we find R N. Thus, R N = 5 (8 4 8) = 5 20 = 20 5 = 4 25 To find I N, we short-circuit terminls nd, s shown in Fig. 4.40(). We ignore the 5- resistor ecuse it hs een short-circuited. Applying mesh nlysis, we otin i 1 = 2A, 20i 2 4i 1 12 = 0 From these equtions, we otin i 2 = 1A= i sc = I N Alterntively, we my determine I N from V Th /R Th. We otin V Th s the open-circuit voltge cross terminls nd in Fig. 4.40(c). Using mesh nlysis, we otin nd i 3 = 2A 25i 4 4i 3 12 = 0 i 4 = 0.8 A v oc = V Th = 5i 4 = 4V

21 CHAPTER 4 Circuit Theorems Ω 8 Ω i sc = I N i 1 R N 5 Ω 2 A 12 V 8 Ω 8 Ω () () i 2 5 Ω 8 Ω i 4 i 3 2 A 5 Ω 12 V 8 Ω V Th = v oc (c) Figure 4.40 For Exmple 4.11; finding: () R N, () I N = i sc, (c) V Th = v oc. Hence, I N = V Th R Th = 4 4 = 1A s otined previously. This lso serves to confirm Eq. (4.7) tht R Th = v oc /i sc = 4/1 = 4. Thus, the Norton equivlent circuit is s shown in Fig A Figure 4.41 Norton equivlent of the circuit in Fig P R A C T I C E P R O B L E M Find the Norton equivlent circuit for the circuit in Fig Answer: R N = 3,I N = 4.5A. 3 Ω 3 Ω 15 V 4 A Figure 4.42 For Prctice Pro E X A M P L E Using Norton s theorem, find R N nd I N of the circuit in Fig t terminls -. Solution: To find R N, we set the independent voltge source equl to zero nd connect voltge source of v o = 1 V (or ny unspecified voltge v o )tothe

22 140 PART 1 DC Circuits 2 I x i x 5 Ω 10 V Figure 4.43 For Exmple terminls. We otin the circuit in Fig. 4.44(). We ignore the 4- resistor ecuse it is short-circuited. Also due to the short circuit, the 5- resistor, the voltge source, nd the dependent current source re ll in prllel. Hence, i x = v o /5 = 1/5 = 0.2. At node, i o = i x 2i x = 3i x = 0.6, nd R N = v o = 1 =1.67 i o 0.6 To find I N, we short-circuit terminls nd nd find the current i sc, s indicted in Fig. 4.44(). Note from this figure tht the 4- resistor, the 10-V voltge source, the 5- resistor, nd the dependent current source re ll in prllel. Hence, At node, KCL gives Thus, i x = = 2A i sc = i x 2i x = 2 4 = 6A I N = 6A 2i x 2i x i x 5 Ω i x 5 Ω i o v o = 1 V 10 V i sc = I N () () Figure 4.44 For Exmple 4.12: () finding R N, () finding I N. P R A C T I C E P R O B L E M v x 10 A v x Find the Norton equivlent circuit of the circuit in Fig Answer: R N = 1,I N = 10 A. Figure 4.45 For Prctice Pro DERIVATIONS OF THEVENIN S AND NORTON S THEOREMS In this section, we will prove Thevenin s nd Norton s theorems using the superposition principle.

23 CHAPTER 4 Circuit Theorems 141 Consider the liner circuit in Fig. 4.46(). It is ssumed tht the circuit contins resistors, nd dependent nd independent sources. We hve ccess to the circuit vi terminls nd, through which current from n externl source is pplied. Our ojective is to ensure tht the voltgecurrent reltion t terminls nd is identicl to tht of the Thevenin equivlent in Fig. 4.46(). For the ske of simplicity, suppose the liner circuit in Fig. 4.46() contins two independent voltge sources v s1 nd v s2 nd two independent current sources i s1 nd i s2. We my otin ny circuit vrile, such s the terminl voltge v, y pplying superposition. Tht is, we consider the contriution due to ech independent source including the externl source i. By superposition, the terminl voltge v is v = A 0 i A 1 v s1 A 2 v s2 A 3 i s1 A 4 i s2 (4.13) where A 0,A 1,A 2,A 3, nd A 4 re constnts. Ech term on the right-hnd side of Eq. (4.13) is the contriution of the relted independent source; tht is, A 0 i is the contriution to v due to the externl current source i, A 1 v s1 is the contriution due to the voltge source v s1, nd so on. We my collect terms for the internl independent sources together s B 0,so tht Eq. (4.13) ecomes v = A 0 i B 0 (4.14) where B 0 = A 1 v s1 A 2 v s2 A 3 i s1 A 4 i s2. We now wnt to evlute the vlues of constnts A 0 nd B 0. When the terminls nd re opencircuited, i = 0 nd v = B 0. Thus B 0 is the open-circuit voltge v oc, which is the sme s V Th,so B 0 = V Th (4.15) When ll the internl sources re turned off, B 0 = 0. The circuit cn then e replced y n equivlent resistnce R eq, which is the sme s R Th, nd Eq. (4.14) ecomes i i Figure 4.46 v v () () Liner circuit R Th Derivtion of Thevenin equivlent: () current-driven circuit, () its Thevenin equivlent. V Th v = A 0 i = R Th i A 0 = R Th (4.16) Sustituting the vlues of A 0 nd B 0 in Eq. (4.14) gives v = R Th i V Th (4.17) which expresses the voltge-current reltion t terminls nd of the circuit in Fig. 4.46(). Thus, the two circuits in Fig. 4.46() nd 4.46() re equivlent. When the sme liner circuit is driven y voltge source v s shown in Fig. 4.47(), the current flowing into the circuit cn e otined y superposition s i = C 0 v D 0 (4.18) where C 0 v is the contriution to i due to the externl voltge source v nd D 0 contins the contriutions to i due to ll internl independent sources. When the terminls - re short-circuited, v = 0 so tht i = D 0 =i sc, where i sc is the short-circuit current flowing out of terminl, which is the sme s the Norton current I N, i.e., D 0 =I N (4.19) v v i i Figure 4.47 () () Liner circuit R N I N Derivtion of Norton equivlent: () voltge-driven circuit, () its Norton equivlent.

24 142 PART 1 DC Circuits When ll the internl independent sources re turned off, D 0 = 0 nd the circuit cn e replced y n equivlent resistnce R eq (or n equivlent conductnce G eq = 1/R eq ), which is the sme s R Th or R N. Thus Eq. (4.19) ecomes i = v I N (4.20) R Th This expresses the voltge-current reltion t terminls - of the circuit in Fig. 4.47(), confirming tht the two circuits in Fig. 4.47() nd 4.47() re equivlent. 4.8 MAXIMUM POWER TRANSFER R Th i V Th R L Figure 4.48 The circuit used for mximum power trnsfer. p p mx In mny prcticl situtions, circuit is designed to provide power to lod. While for electric utilities, minimizing power losses in the process of trnsmission nd distriution is criticl for efficiency nd economic resons, there re other pplictions in res such s communictions where it is desirle to mximize the power delivered to lod. We now ddress the prolem of delivering the mximum power to lod when given system with known internl losses. It should e noted tht this will result in significnt internl losses greter thn or equl to the power delivered to the lod. The Thevenin equivlent is useful in finding the mximum power liner circuit cn deliver to lod. We ssume tht we cn djust the lod resistnce R L. If the entire circuit is replced y its Thevenin equivlent except for the lod, s shown in Fig. 4.48, the power delivered to the lod is ( ) p = i 2 V 2 Th R L = R L (4.21) R Th R L For given circuit, V Th nd R Th re fixed. By vrying the lod resistnce R L, the power delivered to the lod vries s sketched in Fig We notice from Fig tht the power is smll for smll or lrge vlues of R L ut mximum for some vlue of R L etween 0 nd. We now wnt to show tht this mximum power occurs when R L is equl to R Th. This is known s the mximum power theorem. 0 R Th R L Mximum power is trnsferred to the lod when the lod resistnce equls the Thevenin resistnce s seen from the lod (R L = R Th ). Figure 4.49 Power delivered to the lod s function of R L. To prove the mximum power trnsfer theorem, we differentite p in Eq. (4.21) with respect to R L nd set the result equl to zero. We otin [ dp = V 2 (RTh R L ) 2 ] 2R L (R Th R L ) Th dr L (R Th R L ) 4 [ ] = VTh 2 (RTh R L 2R L ) = 0 (R Th R L ) 3

25 CHAPTER 4 Circuit Theorems 143 This implies tht 0 = (R Th R L 2R L ) = (R Th R L ) (4.22) which yields R L = R Th (4.23) showing tht the mximum power trnsfer tkes plce when the lod resistnce R L equls the Thevenin resistnce R Th. We cn redily confirm tht Eq. (4.23) gives the mximum power y showing tht d 2 p/drl 2 < 0. The mximum power trnsferred is otined y sustituting Eq. (4.23) into Eq. (4.21), for The source nd lod re sid to e mtched when R L = R Th. p mx = V 2 Th 4R Th (4.24) Eqution (4.24) pplies only when R L = R Th. When R L R Th,we compute the power delivered to the lod using Eq. (4.21). E X A M P L E Find the vlue of R L for mximum power trnsfer in the circuit of Fig Find the mximum power. 3 Ω 12 V 1 2 A R L Figure 4.50 For Exmple Solution: We need to find the Thevenin resistnce R Th nd the Thevenin voltge V Th cross the terminls -. To get R Th, we use the circuit in Fig. 4.51() nd otin R Th = = = Ω 1 3 Ω R Th 12 V i 1 1 i 2 2 A V Th () () Figure 4.51 For Exmple 4.13: () finding R Th, () finding V Th.

26 144 PART 1 DC Circuits To get V Th, we consider the circuit in Fig. 4.51(). Applying mesh nlysis, 12 18i 1 12i 2 = 0, i 2 =2A Solving for i 1, we get i 1 =2/3. Applying KVL round the outer loop to get V Th cross terminls -, we otin 12 6i 1 3i 2 2(0) V Th = 0 V Th = 22 V For mximum power trnsfer, nd the mximum power is R L = R Th = 9 p mx = V 2 Th 4R L = = W P R A C T I C E P R O B L E M v x 1 Ω Determine the vlue of R L tht will drw the mximum power from the rest of the circuit in Fig Clculte the mximum power. Answer: 4.22, W. 9 V 3v x R L Figure 4.52 For Prctice Pro VERIFYING CIRCUIT THEOREMS WITH PSPICE In this section, we lern how to use PSpice to verify the theorems covered in this chpter. Specificlly, we will consider using dc sweep nlysis to find the Thevenin or Norton equivlent t ny pir of nodes in circuit nd the mximum power trnsfer to lod. The reder is dvised to red Section D.3 of Appendix D in preprtion for this section. To find the Thevenin equivlent of circuit t pir of open terminls using PSpice, we use the schemtic editor to drw the circuit nd insert n independent proing current source, sy, Ip, t the terminls. The proing current source must hve prt nme ISRC. We then perform DC Sweep on Ip, s discussed in Section D.3. Typiclly, we my let the current through Ip vry from 0 to 1 A in 0.1-A increments. After simulting the circuit, we use Proe to disply plot of the voltge cross Ip versus the current through Ip. The zero intercept of the plot gives us the Thevenin equivlent voltge, while the slope of the plot is equl to the Thevenin resistnce. To find the Norton equivlent involves similr steps except tht we insert proing independent voltge source (with prt nme VSRC), sy, Vp, t the terminls. We perform DC Sweep on Vp nd let Vp vry from 0 to 1 V in 0.1-V increments. A plot of the current through

27 CHAPTER 4 Circuit Theorems 145 Vp versus the voltge cross Vp is otined using the Proe menu fter simultion. The zero intercept is equl to the Norton current, while the slope of the plot is equl to the Norton conductnce. To find the mximum power trnsfer to lod using PSpice involves performing dc prmetric sweep on the component vlue of R L in Fig nd plotting the power delivered to the lod s function of R L. According to Fig. 4.49, the mximum power occurs when R L = R Th. This is est illustrted with n exmple, nd Exmple 4.15 provides one. We use VSRC nd ISRC s prt nmes for the independent voltge nd current sources. E X A M P L E Consider the circuit is in Fig (see Exmple 4.9). Use PSpice to find the Thevenin nd Norton equivlent circuits. Solution: () To find the Thevenin resistnce R Th nd Thevenin voltge V Th t the terminls - in the circuit in Fig. 4.31, we first use Schemtics to drw the circuit s shown in Fig. 4.53(). Notice tht proing current source I2 is inserted t the terminls. Under Anlysis/Setput, we select DC Sweep. In the DC Sweep dilog ox, we select Liner for the Sweep Type nd Current Source for the Sweep Vr. Type. We enter I2 under the Nme ox, 0 s Strt Vlue, 1sEnd Vlue, nd 0.1 s Increment. After simultion, we dd trce V(I2:) from the Proe menu nd otin the plot shown in Fig. 4.53(). From the plot, we otin V Th = Zero intercept = 20 V, R Th = Slope = = 6 1 These gree with wht we got nlyticlly in Exmple V R2 R4 I1 2 2 E1 R4 4 R3 6 I2 GAIN=2 24 V 22 V () 0 20 V 0 A 0.2 A 0.4 A 0.6 A 0.8 A 1.0 A = V(I2:-) () Figure 4.53 For Exmple 4.14: () schemtic nd () plot for finding R Th nd V Th. () To find the Norton equivlent, we modify the schemtic in Fig. 4.53() y replying the proing current source with proing voltge source V1. The result is the schemtic in Fig. 4.54(). Agin, in the DC Sweep dilog ox, we select Liner for the Sweep Type nd Voltge Source for the Sweep Vr. Type. We enter V1 under Nme ox, 0 s Strt Vlue,1sEnd Vlue,

28 146 PART 1 DC Circuits nd 0.1 s Increment. When the Proe is running, we dd trce I(V1) nd otin the plot in Fig. 4.54(). From the plot, we otin I N = Zero intercept = A G N = Slope = = 0.17 S 3.4 A R2 R1 I1 2 2 E1 R4 4 R3 6 V1 GAIN=2 3.3 A 3.2 A 3.1 A 0 V 0.2 V 0.4 V 0.6 V 0.8 V 1.0 V () 0 I(V1) V_V1 () Figure 4.54 For Exmple 4.14: () schemtic nd () plot for finding G N nd I N. P R A C T I C E P R O B L E M Rework Prctice Pro. 4.9 using PSpice. Answer: V Th = 5.33 V, R Th = E X A M P L E V 1 kω R L Figure 4.55 For Exmple DC=1 V Figure 4.56 PARAMETERS: RL 2k R1 V1 1k 0 R2 {RL} Schemtic for the circuit in Fig Refer to the circuit in Fig Use PSpice to find the mximum power trnsfer to R L. Solution: We need to perform dc sweep on R L to determine when the power cross it is mximum. We first drw the circuit using Schemtics s shown in Fig Once the circuit is drwn, we tke the following three steps to further prepre the circuit for dc sweep. The first step involves defining the vlue of R L s prmeter, since we wnt to vry it. To do this: 1. DCLICKL the vlue 1k of R2 (representing R L ) to open up the Set Attriute Vlue dilog ox. 2. Replce 1k with {RL} nd click OK to ccept the chnge. Note tht the curly rckets re necessry. The second step is to define prmeter. To chieve this: 1. Select Drw/Get New Prt/Lirries /specil.sl. 2. Type PARAM in the PrtNme ox nd click OK. 3. DRAG the ox to ny position ner the circuit. 4. CLICKL to end plcement mode.

29 CHAPTER 4 Circuit Theorems DCLICKL to open up the PrtNme: PARAM dilog ox. 6. CLICKL on NAME1 = nd enter RL (with no curly rckets) in the Vlue ox, nd CLICKL Sve Attr to ccept chnge. 7. CLICKL on VALUE1 = nd enter 2k in the Vlue ox, nd CLICKL Sve Attr to ccept chnge. 8. Click OK. The vlue 2k in item 7 is necessry for is point clcultion; it cnnot e left lnk. The third step is to set up the DC Sweep to sweep the prmeter. To do this: 1. Select Anlysis/Setput to ring up the DC Sweep dilog ox. 2. For the Sweep Type, select Liner (or Octve for wide rnge of R L ). 3. For the Sweep Vr. Type, select Glol Prmeter. 4. Under the Nme ox, enter RL. 5. In the Strt Vlue ox, enter In the End Vlue ox, enter 5k. 7. In the Increment ox, enter Click OK nd Close to ccept the prmeters. After tking these steps nd sving the circuit, we re redy to simulte. Select Anlysis/Simulte. If there re no errors, we select Add Trce in the Proe menu nd type V(R2:2) I(R2) in the Trce Commnd ox. [The negtive sign is needed since I(R2) is negtive.] This gives the plot of the power delivered to R L s R L vries from 100 to5k. We cn lso otin the power sored y R L y typing V(R2:2) V(R2:2)/RL in the Trce Commnd ox. Either wy, we otin the plot in Fig It is evident from the plot tht the mximum power is 250 µw. Notice tht the mximum occurs when R L = 1k, s expected nlyticlly. 250 uw 200 uw 150 uw 100 uw 50 uw K 4.0 K 6.0 K Figure V(R2:2)*I(R2) RL For Exmple 4.15: the plot of power cross P L. P R A C T I C E P R O B L E M Find the mximum power trnsferred to R L if the 1-k resistor in Fig is replced y 2-k resistor. Answer: 125 µw APPLICATIONS In this section we will discuss two importnt prcticl pplictions of the concepts covered in this chpter: source modeling nd resistnce mesurement Source Modeling Source modeling provides n exmple of the usefulness of the Thevenin or the Norton equivlent. An ctive source such s ttery is often chrcterized y its Thevenin or Norton equivlent circuit. An idel voltge source provides constnt voltge irrespective of the current

30 148 PART 1 DC Circuits v s R s drwn y the lod, while n idel current source supplies constnt current regrdless of the lod voltge. As Fig shows, prcticl voltge nd current sources re not idel, due to their internl resistnces or source resistnces R s nd R p. They ecome idel s R s 0 nd R p. To show tht this is the cse, consider the effect of the lod on voltge sources, s shown in Fig. 4.59(). By the voltge division principle, the lod voltge is i s Figure 4.58 () () R p () Prcticl voltge source, () prcticl current source. v L = R L v s (4.25) R s R L As R L increses, the lod voltge pproches source voltge v s,s illustrted in Fig. 4.59(). From Eq. (4.25), we should note tht: 1. The lod voltge will e constnt if the internl resistnce R s of the source is zero or, t lest, R s R L. In other words, the smller R s is compred to R L, the closer the voltge source is to eing idel. 2. When the lod is disconnected (i.e., the source is opencircuited so tht R L ), v oc = v s. Thus, v s my e regrded s the unloded source voltge. The connection of the lod cuses the terminl voltge to drop in mgnitude; this is known s the loding effect. I L v s R s v L R L v L v s Idel source Prcticl source i s R p R L () 0 () R L I L i s 0 Figure 4.60 () Idel source Prcticl source () R L () Prcticl current source connected to lod R L, () lod current decreses s R L increses. Figure 4.59 () Prcticl voltge source connected to lod R L, () lod voltge decreses s R L decreses. The sme rgument cn e mde for prcticl current source when connected to lod s shown in Fig. 4.60(). By the current division principle, R p i L = i s (4.26) R p R L Figure 4.60() shows the vrition in the lod current s the lod resistnce increses. Agin, we notice drop in current due to the lod (loding effect), nd lod current is constnt (idel current source) when the internl resistnce is very lrge (i.e., R p or, t lest, R p R L ). Sometimes, we need to know the unloded source voltge v s nd the internl resistnce R s of voltge source. To find v s nd R s, we follow the procedure illustrted in Fig First, we mesure the open-circuit voltge v oc s in Fig. 4.61() nd set v s = v oc (4.27)

31 CHAPTER 4 Circuit Theorems 149 Then, we connect vrile lod R L cross the terminls s in Fig. 4.61(). We djust the resistnce R L until we mesure lod voltge of exctly one-hlf of the open-circuit voltge, v L = v oc /2, ecuse now R L = R Th = R s. At tht point, we disconnect R L nd mesure it. We set R s = R L (4.28) For exmple, cr ttery my hve v s = 12 V nd R s = Signl source v oc Signl source v L R L () () Figure 4.61 () Mesuring v oc, () mesuring v L. E X A M P L E The terminl voltge of voltge source is 12 V when connected to 2-W lod. When the lod is disconnected, the terminl voltge rises to 12.4 V. () Clculte the source voltge v s nd internl resistnce R s. () Determine the voltge when n 8- lod is connected to the source. Solution: () We replce the source y its Thevenin equivlent. The terminl voltge when the lod is disconnected is the open-circuit voltge, v s = v oc = 12.4V When the lod is connected, s shown in Fig. 4.62(), v L = 12 V nd p L = 2 W. Hence, p L = vl2 R L = v2 L = 122 = 72 R L p L 2 The lod current is i L = v L = 12 R L 72 = 1 6 A The voltge cross R s is the difference etween the source voltge v s nd the lod voltge v L,or = 0.4 = R s i L, R s = 0.4 = 2.4 I L () Now tht we hve the Thevenin equivlent of the source, we connect the 8- lod cross the Thevenin equivlent s shown in Fig. 4.62(). Using voltge division, we otin 8 v = (12) = V R s i L v s v L () V v () Figure 4.62 For Exmple R L 8 Ω