Methods of Analysis and Selected Topics (dc)

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1 8 N A Methods of Anlysis nd Selected Topics (dc) 8. INTRODUCTION The circuits descried in the previous chpters hd only one source or two or more sources in series or prllel present. The step-y-step procedure outlined in those chpters cnnot e pplied if the sources re not in series or prllel. There will e n interction of sources tht will not permit the reduction technique used in Chpter 7 to find quntities such s the totl resistnce nd source current. Methods of nlysis hve een developed tht llow us to pproch, in systemtic mnner, network with ny numer of sources in ny rrngement. Fortuntely, these methods cn lso e pplied to networks with only one source. The methods to e discussed in detil in this chpter include rnch-current nlysis, mesh nlysis, nd nodl nlysis. ch cn e pplied to the sme network. The est method cnnot e defined y set of rules ut cn e determined only y cquiring firm understnding of the reltive dvntges of ech. All the methods cn e pplied to liner ilterl networks. The term liner indictes tht the chrcteristics of the network elements (such s the resistors) re independent of the voltge cross or current through them. The second term, ilterl, refers to the fct tht there is no chnge in the ehvior or chrcteristics of n element if the current through or voltge cross the element is reversed. Of the three methods listed ove, the rnchcurrent method is the only one not restricted to ilterl devices. Before discussing the methods in detil, we shll consider the current source nd conversions etween voltge nd current sources. At the end of the chpter we shll consider ridge networks nd D-Y nd Y-D conversions. Chpter 9 will present the importnt theorems of network nlysis tht cn lso e employed to solve networks with more thn one source. 8.2 CURRNT SOURCS The concept of the current source ws introduced in Section 2.4 with the photogrph of commercilly ville unit. We must now investi-

2 256 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A gte its chrcteristics in greter detil so tht we cn properly determine its effect on the networks to e exmined in this chpter. The current source is often referred to s the dul of the voltge source. A ttery supplies fixed voltge, nd the source current cn vry; ut the current source supplies fixed current to the rnch in which it is locted, while its terminl voltge my vry s determined y the network to which it is pplied. Note from the ove tht dulity simply implies n interchnge of current nd voltge to distinguish the chrcteristics of one source from the other. The interest in the current source is due primrily to semiconductor devices such s the trnsistor. In the sic electronics courses, you will find tht the trnsistor is current-controlled device. In the physicl model (equivlent circuit) of trnsistor used in the nlysis of trnsistor networks, there ppers current source s indicted in Fig. 8.. The symol for current source ppers in Fig. 8.(). The direction of the rrow within the circle indictes the direction in which current is eing supplied. C B I βi Current source C B = βr e () Trnsistor symol () Trnsistor equivlent circuit FIG. 8. Current source within the trnsistor equivlent circuit. For further comprison, the terminl chrcteristics of n idel dc voltge nd current source re presented in Fig. 8.2, idel implying perfect sources, or no internl losses sensitive to the demnd from the pplied lod. Note tht for the voltge source, the terminl voltge is fixed t volts independent of the direction of the current I. The direction nd mgnitude of I will e determined y the network to which the supply is connected. I I Voltge 0 I () () I V s () 0 () I Current V s FIG. 8.2 Compring the chrcteristics of n idel voltge nd current source. The chrcteristics of the idel current source, shown in Fig. 8.2(), revel tht the mgnitude of the supply current is independent of the polrity of the voltge cross the source. The polrity nd mgnitude of the source voltge V s will e determined y the network to which the source is connected. For ll one-voltge-source networks the current will hve the direction indicted to the right of the ttery in Fig. 8.2(). For ll single-

3 N A SOURC CONVRSIONS 257 current-source networks, it will hve the polrity indicted to the right of the current source in Fig. 8.2(). In review: A current source determines the current in the rnch in which it is locted nd the mgnitude nd polrity of the voltge cross current source re function of the network to which it is pplied. XAMPL 8. Find the source voltge V s nd the current I for the circuit of Fig Solution: I I 0 ma V s V I R (0 ma)(20 k) 200 V I = 0 ma I V s R 20 k V XAMPL 8.2 Find the voltge V s nd the currents I nd I 2 for the network of Fig Solution: FIG. 8.3 xmple 8.. V s 2 V I 2 V R 2 V R 4 Applying Kirchhoff s current lw: I I I 2 A V s I 7 A I I 2 V 4 nd I I I 2 7 A 3 A 4 A XAMPL 8.3 Determine the current I nd the voltge V s for the network of Fig FIG. 8.4 xmple 8.2. Solution: Using the current divider rule: I ( )(6 A) I 2 A R2 R 2 The voltge V is I V R 2 20 V V I R (2 A)(2 ) 4 V nd, pplying Kirchhoff s voltge lw, V s V 20 V 0 V s I 6 A nd V s V 20 V 4 V 20 V 24 V Note the polrity of V s s determined y the multisource network. FIG. 8.5 xmple SOURC CONVRSIONS The current source descried in the previous section is clled n idel source due to the sence of ny internl resistnce. In relity, ll

4 258 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A R s R L I L FIG. 8.6 Prcticl voltge source. I = R s R s R L FIG. 8.7 Prcticl current source. I L sources whether they re voltge or current hve some internl resistnce in the reltive positions shown in Figs. 8.6 nd 8.7. For the voltge source, if R s 0 or is so smll compred to ny series resistor tht it cn e ignored, then we hve n idel voltge source. For the current source, if R s or is lrge enough compred to other prllel elements tht it cn e ignored, then we hve n idel current source. If the internl resistnce is included with either source, then tht source cn e converted to the other type using the procedure to e descried in this section. Since it is often dvntgeous to mke such mneuver, this entire section is devoted to eing sure tht the steps re understood. It is importnt to relize, however, s we proceed through this section, tht source conversions re equivlent only t their externl terminls. The internl chrcteristics of ech re quite different. We wnt the equivlence to ensure tht the pplied lod of Figs. 8.6 nd 8.7 will receive the sme current, voltge, nd power from ech source nd in effect not know, or cre, which source is present. In Fig. 8.6 if we solve for the lod current I L, we otin I L (8.) Rs R L If we multiply this y fctor of, which we cn choose to e R s /R s, we otin () I L ( Rs/R s ) R s( /Rs) R si (8.2) Rs R L Rs RL Rs RL Rs R L If we define I /R s, qution (8.2) is the sme s tht otined y pplying the current divider rule to the network of Fig The result is n equivlence etween the networks of Figs. 8.6 nd 8.7 tht simply requires tht I /R s nd the series resistor R s of Fig. 8.6 e plced in prllel, s in Fig The vlidity of this is demonstrted in xmple 8.4 of this section. For clrity, the equivlent sources, s fr s terminls nd re concerned, re repeted in Fig. 8.8 with the equtions for converting in either direction. Note, s just indicted, tht the resistor R s is the sme in ech source; only its position chnges. The current of the current source or the voltge of the voltge source is determined using Ohm s lw nd the prmeters of the other configurtion. It ws pointed out in some detil in Chpter 6 tht every source of voltge hs some internl series resistnce. Forthe current source, some internl prllel resistnce will lwys exist in the prcticl world. However, in mny cses, it is n R s I = R s R s = IR s FIG. 8.8 Source conversion.

5 N A SOURC CONVRSIONS 259 excellent pproximtion to drop the internl resistnce of source due to the mgnitude of the elements of the network to which it is pplied. For this reson, in the nlyses to follow, voltge sources my pper without series resistor, nd current sources my pper without prllel resistnce. Relize, however, tht for us to perform conversion from one type of source to nother, voltge source must hve resistor in series with it, nd current source must hve resistor in prllel. XAMPL 8.4. Convert the voltge source of Fig. 8.9() to current source, nd clculte the current through the 4- lod for ech source.. Replce the 4- lod with -k lod, nd clculte the current I L for the voltge source. c. Repet the clcultion of prt () ssuming tht the voltge source is idel (R s 0 ) ecuse R L is so much lrger thn R s. Is this one of those situtions where ssuming tht the source is idel is n pproprite pproximtion? Solutions:. See Fig Fig. 8.9(): Fig. 8.9(): 6 V. I L Rs 2 k R L 6 V I L A Rs R L 2 4 R I L si (2 )(3 A) A Rs 2 4 R L 5.99 ma 6 V c. I L 6 ma 5.99 ma R L k Yes, R L k R s (voltge source). XAMPL 8.5. Convert the current source of Fig. 8.0() to voltge source, nd find the lod current for ech source.. Replce the 6-k lod with 0- lod, nd clculte the current I L for the current source. c. Repet the clcultion of prt () ssuming tht the current source is idel (R s ) ecuse R L is so much smller thn R s. Is this one of those situtions where ssuming tht the source is idel is n pproprite pproximtion? I = R s = 3 A R s 2 6 V 3 A () () R s R L FIG. 8.9 xmple 8.4. I L 4 I L 2 R L 4 9 ma I R s 9 ma () 3 k R L 6 k I L FIG. 8.0 xmple 8.5. R s = IR s = 27 V 3 k RL () 6 k I L

6 260 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Solutions:. See Fig Fig. 8.0(): Fig. 8.0(): R I L si (3 k)(9 ma) 3 ma Rs R L 3 k6 k 27 V 27 V I L 3 ma Rs 3 k6 k 9 k R L R. I L si (3 k)(9 ma) 8.97 ma Rs R L 3 k0 c. I L I 9 ma 8.97 ma Yes, R s k R L (current source). 8.4 CURRNT SOURCS IN PARALLL If two or more current sources re in prllel, they my ll e replced y one current source hving the mgnitude nd direction of the resultnt, which cn e found y summing the currents in one direction nd sutrcting the sum of the currents in the opposite direction. The new prllel resistnce is determined y methods descried in the discussion of prllel resistors in Chpter 5. Consider the following exmples. XAMPL 8.6 Reduce the prllel current sources of Figs. 8. nd 8.2 to single current source. 6 A R 3 0 A 6 I s 4 A 2 I s = 0 A 6 A = 4 A R s = 3 6 = 2 FIG. 8. xmple A 3 A R 4 4 A I s 8 A R s 4 FIG. 8.2 xmple 8.6. I s = 7 A 4 A 3 A = 8 A R s = R = 4 Solution: Note the solution in ech figure.

7 N A BRANCH-CURRNT ANALYSIS 26 XAMPL 8.7 Reduce the network of Fig. 8.3 to single current source, nd clculte the current through R L. Solution: In this exmple, the voltge source will first e converted to current source s shown in Fig Comining current sources, R 8 32 V I 2 6 A 24 R L 4 I L I 4 A R 8 I L I 2 6 A 24 R L 4 FIG. 8.3 xmple 8.7. I = R = 32 V 8 = 4 A FIG. 8.4 Network of Fig. 8.3 following the conversion of the voltge source to current source. I s I I 2 4 A 6 A 0 A nd R s R Applying the current divider rule to the resulting network of Fig. 8.5, R I L si s (6 )(0 A) 60 A 3 A Rs R L XAMPL 8.8 Determine the current I 2 in the network of Fig Solution: Although it might pper tht the network cnnot e solved using methods introduced thus fr, one source conversion s shown in Fig. 8.7 will result in simple series circuit: s I R (4 A)(3 ) 2 V nd R s R 3 s 2 2 V 5 V 7 V nd I A Rs CURRNT SOURCS IN SRIS The current through ny rnch of network cn e only single-vlued. For the sitution indicted t point in Fig. 8.8, we find y ppliction of Kirchhoff s current lw tht the current leving tht point is greter thn tht entering n impossile sitution. Therefore, current sources of different current rtings re not connected in series, just s voltge sources of different voltge rtings re not connected in prllel. 8.6 BRANCH-CURRNT ANALYSIS We will now consider the first in series of methods for solving networks with two or more sources. Once the rnch-current method is I s I s 0 A R s 6 R L 4 FIG. 8.5 Network of Fig. 8.4 reduced to its simplest form. 5 V I 4 A R 3 2 s R s 3 2 V FIG. 8.6 xmple V 2 2 I L 2 FIG. 8.7 Network of Fig. 8.6 following the conversion of the current source to voltge source. No! 6 A 7 A FIG. 8.8 Invlid sitution. I 2 I 2

8 262 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A mstered, there is no liner dc network for which solution cnnot e found. Keep in mind tht networks with two isolted voltge sources cnnot e solved using the pproch of Chpter 7. For dditionl evidence of this fct, try solving for the unknown elements of xmple 8.9 using the methods introduced in Chpter 7. The network of Fig. 8.2 cn e solved using the source conversions descried in the lst section, ut the method to e descried in this section hs pplictions fr eyond the configurtion of this network. The most direct introduction to method of this type is to list the series of steps required for its ppliction. There re four steps, s indicted elow. Before continuing, understnd tht this method will produce the current through ech rnch of the network, the rnch current. Once this is known, ll other quntities, such s voltge or power, cn e determined.. Assign distinct current of ritrry direction to ech rnch of the network. 2. Indicte the polrities for ech resistor s determined y the ssumed current direction. 3. Apply Kirchhoff s voltge lw round ech closed, independent loop of the network. The est wy to determine how mny times Kirchhoff s voltge lw will hve to e pplied is to determine the numer of windows in the network. The network of xmple 8.9 hs definite similrity to the two-window configurtion of Fig. 8.9(). The result is need to pply Kirchhoff s voltge lw twice. For networks with three windows, s shown in Fig. 8.9(), three pplictions of Kirchhoff s voltge lw re required, nd so on () () FIG. 8.9 Determining the numer of independent closed loops. 4. Apply Kirchhoff s current lw t the minimum numer of nodes tht will include ll the rnch currents of the network. The minimum numer is one less thn the numer of independent nodes of the network. For the purposes of this nlysis, node is junction of two or more rnches, where rnch is ny comintion (4 nodes) (4 nodes) 3 (2 nodes) 2 (2 nodes) = eq. 2 = eq. 4 = 3 eq. 4 = 3 eq. FIG Determining the numer of pplictions of Kirchhoff s current lw required.

9 N A BRANCH-CURRNT ANALYSIS 263 of series elements. Figure 8.20 defines the numer of pplictions of Kirchhoff s current lw for ech configurtion of Fig Solve the resulting simultneous liner equtions for ssumed rnch currents. It is ssumed tht the use of the determinnts method to solve for the currents I, I 2, nd I 3 is understood nd is prt of the student s mthemticl ckground. If not, detiled explntion of the procedure is provided in Appendix C. Clcultors nd computer softwre pckges such s Mthcd cn find the solutions quickly nd ccurtely. XAMPL 8.9 Apply the rnch-current method to the network of Fig Solution : Step : Since there re three distinct rnches (cd, c, c), three currents of ritrry directions (I, I 2, I 3 ) re chosen, s indicted in Fig The current directions for I nd I 2 were chosen to mtch the pressure pplied y sources nd 2, respectively. Since oth I nd I 2 enter node, I 3 is leving. Step 2: Polrities for ech resistor re drwn to gree with ssumed current directions, s indicted in Fig I I 2 R 2 d 2 V I 3 c V Defined y I 2 I Defined y I 3 I2 Defined y I 2 FIG. 8.2 xmple 8.9. Fixed polrity 2 V I V Fixed polrity FIG Inserting the polrities cross the resistive elements s defined y the chosen rnch currents. Step 3: Kirchhoff s voltge lw is pplied round ech closed loop ( nd 2) in the clockwise direction: Rise in potentil loop : V V R V R 0 3 Drop in potentil nd Rise in potentil loop 2: V V V R3 R Drop in potentil loop : V 2 V 2 I 4 I 0 3 Bttery Voltge drop potentil cross 2- resistor Voltge drop cross 4- resistor loop 2: V 4 I I V 0

10 264 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Step 4: Applying Kirchhoff s current lw t node (in two-node network, the lw is pplied t only one node), I I 2 I 3 Step 5: There re three equtions nd three unknowns (units removed for clrity): 2 2I 4I 3 0 Rewritten: 2I 0 4I 3 2 4I 3 I I 2 4I 3 6 I I 2 I 3 I I 2 I 3 0 Using third-order determinnts (Appendix C), we hve I D I D A 2 A A negtive sign in front of rnch current indictes only tht the ctul current is in the direction opposite to tht ssumed. I D A Mthcd Solution: Once you understnd the procedure for entering the prmeters, you cn use Mthcd to solve determinnts such s FIG Using Mthcd to verify the numericl clcultions of xmple 8.9.

11 N A BRANCH-CURRNT ANALYSIS 265 ppering in Solution in very short time frme. The numertor is defined y n in the sme mnner descried for erlier exercises. Then the sequence View-Toolrs-Mtrix is pplied to otin the Mtrix toolr ppering in Fig Selecting the top left option clled Mtrix will result in the Insert Mtrix dilog ox in which 3 3 is selected. The 3 3 mtrix will pper with rcket to signl which prmeter should e entered. nter tht prmeter, nd then use the left click of the mouse to select the next prmeter you wnt to enter. When you hve finished, move on to define the denomintor d in the sme mnner. Then define the current of interest, select Determinnt from the Mtrix toolr, nd insert the numertor vrile n. Follow with division sign, nd enter the Determinnt of the denomintor s shown in Fig Retype I nd select the equl sign; the correct result of will pper. Once you hve mstered the rther simple nd direct process just descried, the vilility of Mthcd s checking tool or solving mechnism will e deeply pprecited. Solution 2: Insted of using third-order determinnts s in Solution, we could reduce the three equtions to two y sustituting the third eqution in the first nd second equtions: I 3 2 2I 4 I I I 4I 4I 2 0 I 3 4 I I 2 I I 4I 2 I or 6I 4I 2 2 4I 5I 2 6 Multiplying through y in the top eqution yields 6I 4I 2 2 4I 5I 2 6 nd using determinnts, I A Using the TI-86 clcultor: det[[2,4][6,5]]/det[[6,4][4,5]] NTR CALC. 8. Note the det (determinnt) otined from Mth listing under MATRX menu nd the fct tht ech determinnt must e determined individully. The first set of rckets within the overll determinnt rckets of the first determinnt defines the first row of the determinnt, while the second set of rckets within the sme determinnt defines the second row. A comm seprtes the entries for ech row. Oviously, the time to lern how to enter the prmeters is miniml when you consider the svings in time nd the ccurcy otined.

12 266 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A I 2 2 A I 3 I I 2 2 A It is now importnt tht the impct of the results otined e understood. The currents I, I 2, nd I 3 re the ctul currents in the rnches in which they were defined. A negtive sign in the solution simply revels tht the ctul current hs the opposite direction thn initilly defined the mgnitude is correct. Once the ctul current directions nd their mgnitudes re inserted in the originl network, the vrious voltges nd power levels cn e determined. For this exmple, the ctul current directions nd their mgnitudes hve een entered on the originl network in Fig Note tht the current through the series elements R nd is A; the current through, A; nd the current through the series elements nd 2, 2 A. Due to the minus sign in the solution, the direction of I is opposite to tht shown in Fig The voltge cross ny resistor cn now e found using Ohm s lw, nd the power delivered y either source or to ny one of the three resistors cn e found using the pproprite power eqution. I = A I 2 = 2 A R 2 I 3 = A 4 2 V 2 6 V FIG Reviewing the results of the nlysis of the network of Fig Applying Kirchhoff s voltge lw round the loop indicted in Fig. 8.24, V (4 )I 3 ( )I 2 6 V 0 or (4 )I 3 ( )I 2 6 V nd (4 )( A) ( )(2 A) 6 V 4 V 2 V 6 V 6 V 6 V (checks) XAMPL 8.0 Apply rnch-current nlysis to the network of Fig Solution: Agin, the current directions were chosen to mtch the pressure of ech ttery. The polrities re then dded nd Kirchhoff s voltge lw is pplied round ech closed loop in the clockwise direction. The result is s follows: loop : 5 V (4 )I (0 )I 3 20 V 0 loop 2: 20 V (0 )I 3 (5 )I 2 40 V 0

13 N A MSH ANALYSIS (GNRAL APPROACH) 267 R 4 I 0 I V 3 20 V I 2 2 V 40 FIG xmple 8.0. Applying Kirchhoff s current lw t node, I I 3 I 2 Sustituting the third eqution into the other two yields (with units removed for clrity) 5 4I 0I Sustituting for I 2 (since it occurs only once in the two equtions) 20 0I 3 5(I I 3 ) 40 0 or 4I 0I 3 5 5I 5I 3 60 Multiplying the lower eqution y, we hve 4I 0I 3 5 5I 5I I A I A I 2 I I A reveling tht the ssumed directions were the ctul directions, with I 2 equl to the sum of I nd I MSH ANALYSIS (GNRAL APPROACH) The second method of nlysis to e descried is clled mesh nlysis. The term mesh is derived from the similrities in ppernce etween the closed loops of network nd wire mesh fence. Although this pproch is on more sophisticted plne thn the rnch-current method, it incorportes mny of the ides just developed. Of the two methods, mesh nlysis is the one more frequently pplied tody. Brnch-current nlysis is introduced s stepping stone to mesh nlysis ecuse rnch currents re initilly more rel to the student thn the mesh (loop) currents employed in mesh nlysis. ssentilly,

14 268 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A R 2 2 V 4 I FIG Defining the mesh currents for twowindow network. 2 I 2 6 V 2 I 3 the mesh-nlysis pproch simply elimintes the need to sustitute the results of Kirchhoff s current lw into the equtions derived from Kirchhoff s voltge lw. It is now ccomplished in the initil writing of the equtions. The systemtic pproch outlined elow should e followed when pplying this method.. Assign distinct current in the clockwise direction to ech independent, closed loop of the network. It is not solutely necessry to choose the clockwise direction for ech loop current. In fct, ny direction cn e chosen for ech loop current with no loss in ccurcy, s long s the remining steps re followed properly. However, y choosing the clockwise direction s stndrd, we cn develop shorthnd method (Section 8.8) for writing the required equtions tht will sve time nd possily prevent some common errors. This first step is ccomplished most effectively y plcing loop current within ech window of the network, s demonstrted in the previous section, to ensure tht they re ll independent. A vriety of other loop currents cn e ssigned. In ech cse, however, e sure tht the informtion crried y ny one loop eqution is not included in comintion of the other network equtions. This is the crux of the terminology: independent. No mtter how you choose your loop currents, the numer of loop currents required is lwys equl to the numer of windows of plnr (no-crossovers) network. On occsion network my pper to e nonplnr. However, redrwing of the network my revel tht it is, in fct, plnr. Such my e the cse in one or two prolems t the end of the chpter. Before continuing to the next step, let us ensure tht the concept of loop current is cler. For the network of Fig. 8.26, the loop current I is the rnch current of the rnch contining the 2- resistor nd 2-V ttery. The current through the 4- resistor is not I, however, since there is lso loop current I 2 through it. Since they hve opposite directions, I 4 equls the difference etween the two, I I 2 or I 2 I, depending on which you choose to e the defining direction. In other words, loop current is rnch current only when it is the only loop current ssigned to tht rnch. 2. Indicte the polrities within ech loop for ech resistor s determined y the ssumed direction of loop current for tht loop. Note the requirement tht the polrities e plced within ech loop. This requires, s shown in Fig. 8.26, tht the 4- resistor hve two sets of polrities cross it. 3. Apply Kirchhoff s voltge lw round ech closed loop in the clockwise direction. Agin, the clockwise direction ws chosen to estlish uniformity nd prepre us for the method to e introduced in the next section.. If resistor hs two or more ssumed currents through it, the totl current through the resistor is the ssumed current of the loop in which Kirchhoff s voltge lw is eing pplied, plus the ssumed currents of the other loops pssing through in the sme direction, minus the ssumed currents through in the opposite direction.. The polrity of voltge source is unffected y the direction of the ssigned loop currents. 4. Solve the resulting simultneous liner equtions for the ssumed loop currents.

15 N A MSH ANALYSIS (GNRAL APPROACH) 269 XAMPL 8. Consider the sme sic network s in xmple 8.9 of the preceding section, now ppering in Fig Solution: Step : Two loop currents (I nd I 2 ) re ssigned in the clockwise direction in the windows of the network. A third loop (I 3 ) could hve een included round the entire network, ut the informtion crried y this loop is lredy included in the other two. Step 2: Polrities re drwn within ech window to gree with ssumed current directions. Note tht for this cse, the polrities cross the 4- resistor re the opposite for ech loop current. Step 3: Kirchhoff s voltge lw is pplied round ech loop in the clockwise direction. Keep in mind s this step is performed tht the lw is concerned only with the mgnitude nd polrity of the voltges round the closed loop nd not with whether voltge rise or drop is due to ttery or resistive element. The voltge cross ech resistor is determined y V IR, nd for resistor with more thn one current through it, the current is the loop current of the loop eing exmined plus or minus the other loop currents s determined y their directions. If clockwise pplictions of Kirchhoff s voltge lw re lwys chosen, the other loop currents will lwys e sutrcted from the loop current of the loop eing nlyzed. loop : V V 3 0 (clockwise strting t point ) Voltge drop cross 4- resistor 2 V 2 I 4 I I 2 0 loop 2: V 3 V (clockwise strting t point ) (4 )(I 2 I ) ( )I 2 6 V 0 Step 4: The equtions re then rewritten s follows (without units for clrity): loop : 2 2I 4I 4I 2 0 loop 2: 4I 2 4I I nd loop : 2 6I 4I 2 0 loop 2: 5I 2 4I 6 0 or loop : 6I 4I 2 2 loop 2: 4I 5I 2 6 Applying determinnts will result in Totl current through 4- resistor I A nd I 2 2 A Sutrcted since I 2 is opposite in direction to I. The minus signs indicte tht the currents hve direction opposite to tht indicted y the ssumed loop current. The ctul current through the 2-V source nd 2- resistor is therefore A in the other direction, nd the current through the 6-V source nd - resistor is 2 A in the opposite direction indicted on the circuit. The current through the 4- resistor is determined y the following eqution from the originl network:

16 270 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A loop : I 4 I I 2 A (2 A) A 2 A A (in the direction of I ) The outer loop (I 3 ) nd one inner loop (either I or I 2 ) would lso hve produced the correct results. This pproch, however, will often led to errors since the loop equtions my e more difficult to write. The est method of picking these loop currents is to use the window pproch. R 6 5 V I V I 2 2 XAMPL 8.2 Find the current through ech rnch of the network of Fig Solution: Steps nd 2 re s indicted in the circuit. Note tht the polrities of the 6- resistor re different for ech loop current. Step 3: Kirchhoff s voltge lw is pplied round ech closed loop in the clockwise direction: loop : V V (clockwise strting t point ) 5 V ( )I (6 )(I I 2 ) 0 V 0 FIG xmple 8.2. I 2 flows through the 6-Q resistor in the direction opposite to I. loop 2: 2 V 2 V 3 0 (clockwise strting t point ) 0 V (6 )(I 2 I ) (2 )I 2 0 The equtions re rewritten s 5 I 6I 6I I 6I I 2 6I 2I 2 0 6I 8I 2 0 Step 4: I A I 2 2 A Since I nd I 2 re positive nd flow in opposite directions through the 6- resistor nd 0-V source, the totl current in this rnch is equl to the difference of the two currents in the direction of the lrger: I 2 > I (2 A > A) Therefore, I R2 I 2 I 2A A A in the direction of I 2 It is sometimes imprcticl to drw ll the rnches of circuit t right ngles to one nother. The next exmple demonstrtes how portion of network my pper due to vrious constrints. The method of nlysis does not chnge with this chnge in configurtion.

17 N A MSH ANALYSIS (GNRAL APPROACH) 27 XAMPL 8.3 Find the rnch currents of the network of Fig Solution: Steps nd 2 re s indicted in the circuit. Step 3: Kirchhoff s voltge lw is pplied round ech closed loop: loop : I R 2 V 2 0 (clockwise from point ) 6 V (2 )I 4 V (4 )(I I 2 ) 0 loop 2: V 2 2 V (clockwise from point ) (4 )(I 2 I ) 4 V (6 )(I 2 ) 3 V 0 which re rewritten s 0 4I 2I 4I 2 0 6I 4I 2 0 4I 4I 2 6I 2 0 4I 0I 2 R = = 6 4 V = 6 V R 3 = 3 V 2 4 I I 2 FIG xmple 8.3. or, y multiplying the top eqution y, we otin 6I 4I 2 0 4I 0I 2 Step 4: I 2.82 A Using the TI-86 clcultor: det[[0,4][,0]]/det[[6,4][4,0]] NTR 2.82 CALC I A The current in the 4- resistor nd 4-V source for loop is I I A (0.773 A) 2.82 A A.409 A reveling tht it is.409 A in direction opposite (due to the minus sign) to I in loop. Supermesh Currents On occsion there will e current sources in the network to which mesh nlysis is to e pplied. In such cses one cn convert the current source to voltge source (if prllel resistor is present) nd proceed s efore or utilize supermesh current nd proceed s follows. Strt s efore nd ssign mesh current to ech independent loop, including the current sources, s if they were resistors or voltge sources. Then mentlly (redrw the network if necessry) remove the current sources (replce with open-circuit equivlents), nd pply

18 272 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Kirchhoff s voltge lw to ll the remining independent pths of the network using the mesh currents just defined. Any resulting pth, including two or more mesh currents, is sid to e the pth of supermesh current. Then relte the chosen mesh currents of the network to the independent current sources of the network, nd solve for the mesh currents. The next exmple will clrify the definition of supermesh current nd the procedure. XAMPL 8.4 Using mesh nlysis, determine the currents of the network of Fig R 6 4 I 4 A V 20 V FIG xmple 8.4. Solution: First, the mesh currents for the network re defined, s shown in Fig Then the current source is mentlly removed, s shown in Fig. 8.3, nd Kirchhoff s voltge lw is pplied to the resulting network. The single pth now including the effects of two mesh currents is referred to s the pth of supermesh current. R I I 4 A I V 20 V FIG Defining the mesh currents for the network of Fig R I I V 2 V Supermesh current FIG. 8.3 Defining the supermesh current. Applying Kirchhoff s lw: 20 V I (6 ) I (4 ) I 2 (2 ) 2 V 0 or 0I 2I 2 32

19 N A MSH ANALYSIS (GNRAL APPROACH) 273 Node is then used to relte the mesh currents nd the current source using Kirchhoff s current lw: I I I 2 The result is two equtions nd two unknowns: 0I 2I 2 32 I I 2 4 Applying determinnts: (32)() (2)(4) 40 I 3.33 A 0 2 (0)() (2)() 2 nd I 2 I I 3.33 A 4 A 0.67 A In the ove nlysis, it might pper tht when the current source ws removed, I I 2. However, the supermesh pproch requires tht we stick with the originl definition of ech mesh current nd not lter those definitions when current sources re removed. XAMPL 8.5 Using mesh nlysis, determine the currents for the network of Fig A A FIG xmple 8.5. Solution: The mesh currents re defined in Fig The current sources re removed, nd the single supermesh pth is defined in Fig A I 2 I 2 8 I 3 8 A 6 I 2 I 2 8 I 3 Supermesh current FIG Defining the mesh currents for the network of Fig FIG Defining the supermesh current for the network of Fig Applying Kirchhoff s voltge lw round the supermesh pth: V 2 V 6 V 8 0 (I 2 I )2 I 2 (6 ) (I 2 I 3 )8 0 2I 2 2I 6I 2 8I 2 8I 3 0 2I 6I 2 8I 3 0

20 274 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Introducing the reltionship etween the mesh currents nd the current sources: I 6 A I 3 8 A results in the following solutions: 2I 6I 2 8I 3 0 2(6 A) 6I 2 8(8 A) 0 76 A nd I A 6 Then I 2 I I 2 6 A 4.75 A.25 A nd I 8 I 3 I 2 8 A 4.75 A 3.25 A Agin, note tht you must stick with your originl definitions of the vrious mesh currents when pplying Kirchhoff s voltge lw round the resulting supermesh pths. R 6 5 V V I I MSH ANALYSIS (FORMAT APPROACH) Now tht the sis for the mesh-nlysis pproch hs een estlished, we will now exmine technique for writing the mesh equtions more rpidly nd usully with fewer errors. As n id in introducing the procedure, the network of xmple 8.2 (Fig. 8.27) hs een redrwn in Fig with the ssigned loop currents. (Note tht ech loop current hs clockwise direction.) The equtions otined re 7I 6I 2 5 6I 8I 2 0 FIG Network of Fig redrwn with ssigned loop currents. which cn lso e written s 7I 6I 2 5 8I 2 6I 0 nd expnded s Col. Col. 2 Col. 3 ( 6)I 6I 2 (5 0) (2 6)I 2 6I 0 Note in the ove equtions tht column is composed of loop current times the sum of the resistors through which tht loop current psses. Column 2 is the product of the resistors common to nother loop current times tht other loop current. Note tht in ech eqution, this column is sutrcted from column. Column 3 is the lgeric sum of the voltge sources through which the loop current of interest psses. A source is ssigned positive sign if the loop current psses from the negtive to the positive terminl, nd negtive vlue is ssigned if the polrities re reversed. The comments ove re correct only for stndrd direction of loop current in ech window, the one chosen eing the clockwise direction. The ove sttements cn e extended to develop the following formt pproch to mesh nlysis:

21 N A MSH ANALYSIS (FORMAT APPROACH) 275. Assign loop current to ech independent, closed loop (s in the previous section) in clockwise direction. 2. The numer of required equtions is equl to the numer of chosen independent, closed loops. Column of ech eqution is formed y summing the resistnce vlues of those resistors through which the loop current of interest psses nd multiplying the result y tht loop current. 3. We must now consider the mutul terms, which, s noted in the exmples ove, re lwys sutrcted from the first column. A mutul term is simply ny resistive element hving n dditionl loop current pssing through it. It is possile to hve more thn one mutul term if the loop current of interest hs n element in common with more thn one other loop current. This will e demonstrted in n exmple to follow. ch term is the product of the mutul resistor nd the other loop current pssing through the sme element. 4. The column to the right of the equlity sign is the lgeric sum of the voltge sources through which the loop current of interest psses. Positive signs re ssigned to those sources of voltge hving polrity such tht the loop current psses from the negtive to the positive terminl. A negtive sign is ssigned to those potentils for which the reverse is true. 5. Solve the resulting simultneous equtions for the desired loop currents. Before considering few exmples, e wre tht since the column to the right of the equls sign is the lgeric sum of the voltge sources in tht loop, the formt pproch cn e pplied only to networks in which ll current sources hve een converted to their equivlent voltge source. XAMPL 8.6 Write the mesh equtions for the network of Fig. 8.36, nd find the current through the 7- resistor. Solution: Step : As indicted in Fig. 8.36, ech ssigned loop current hs clockwise direction. Steps 2 to 4: I : (8 6 2 )I (2 )I 2 4 V I 2 : (7 2 )I 2 (2 )I 9 V nd 6I 2I 2 4 9I 2 2I 9 6 I I V FIG xmple V which, for determinnts, re 6I 2I 2 4 2I 9I nd I 2 I A

22 276 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A XAMPL 8.7 Write the mesh equtions for the network of Fig V 4 V 2 I I I 3 2 V 4 FIG xmple 8.7. Solution: Step : ch window is ssigned loop current in the clockwise direction: I does not pss through n element mutul with I 3. I : I 2 : I 3 : I I V 4 V 2 3 I 2 I 3 I 3 4 V 3 4 I 3 3 I V I 3 does not pss through n element mutul with I. Summing terms yields 2I I I 2 I 3I 3 4 7I 3 3I which re rewritten for determinnts s c 2I I I 6I 2 3I I 2 7I 3 2 Note tht the coefficients of the nd digonls re equl. This symmetry out the c-xis will lwys e true for equtions written using the formt pproch. It is check on whether the equtions were otined correctly. We will now consider network with only one source of voltge to point out tht mesh nlysis cn e used to dvntge in other thn multisource networks.

23 N A MSH ANALYSIS (FORMAT APPROACH) 277 XAMPL 8.8 Find the current through the 0- resistor of the network of Fig I 0 = I V I I 2 I 3 FIG xmple 8.8. Solution : I : (8 3 )I (8 )I 3 (3 )I 2 5 V I 2 : (3 5 2 )I 2 (3 )I (5 )I 3 0 I 3 : (8 0 5 )I 3 (8 )I (5 )I 2 0 I 8I 3 3I 2 5 0I 2 3I 5I I 3 8I 5I 2 0 or I 3I 2 8I 3 5 3I 0I 2 5I 3 0 8I 5I 2 23I 3 0 nd I 3 I A Mthcd Solution: For this exmple, rther thn tke the time to develop the determinnt form for ech vrile, we will pply Mthcd directly to the resulting equtions. As shown in Fig. 8.39, Guess vlue for ech vrile must first e defined. Such guessing helps the computer egin its itertion process s it serches for the solution. By providing rough estimte of, the computer recognizes tht the result will proly e numer with mgnitude less thn 00 rther thn hve to worry out solutions tht extend into the thousnds or tens of thousnds the serch hs een nrrowed considerly. Next, s shown, the word Given must e entered to tell the computer tht the defining equtions will follow. Finlly, ech eqution must e crefully entered nd set equl to the constnt on the right using the Ctrl opertion. The results re then otined with the Find(I,I2,I3) expression nd n equl sign. As shown, the results re ville with n cceptle degree of ccurcy even though entering the equtions nd performing the nlysis took only minute or two (with prctice).

24 278 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A FIG Using Mthcd to verify the numericl clcultions of xmple 8.8. Solution 2: Using the TI-86 clcultor: det[[,3,5][3,0,0][8,5,0]]/det[[,3,8][3,0,5][8,5,23]] NTR.220 CALC. 8.3 This disply certinly requires some cre in entering the correct sequence of rckets in the required formt, ut it is still rther net, compct formt. 8.9 NODAL ANALYSIS (GNRAL APPROACH) Recll from the development of loop nlysis tht the generl network equtions were otined y pplying Kirchhoff s voltge lw round ech closed loop. We will now employ Kirchhoff s current lw to develop method referred to s nodl nlysis. A node is defined s junction of two or more rnches. If we now define one node of ny network s reference (tht is, point of zero potentil or ground), the remining nodes of the network will ll hve fixed potentil reltive to this reference. For network of N nodes, therefore, there will exist (N ) nodes with fixed potentil reltive to the ssigned reference node. qutions relting these nodl voltges cn e written y pplying Kirchhoff s current lw t ech of the (N ) nodes. To otin the complete solution of network, these nodl voltges re then evluted in the sme mnner in which loop currents were found in loop nlysis.

25 N A NODAL ANALYSIS (GNRAL APPROACH) 279 The nodl nlysis method is pplied s follows:. Determine the numer of nodes within the network. 2. Pick reference node, nd lel ech remining node with suscripted vlue of voltge: V, V 2, nd so on. 3. Apply Kirchhoff s current lw t ech node except the reference. Assume tht ll unknown currents leve the node for ech ppliction of Kirchhoff s current lw. In other words, for ech node, don t e influenced y the direction tht n unknown current for nother node my hve hd. ch node is to e treted s seprte entity, independent of the ppliction of Kirchhoff s current lw to the other nodes. 4. Solve the resulting equtions for the nodl voltges. A few exmples will clrify the procedure defined y step 3. It will initilly tke some prctice writing the equtions for Kirchhoff s current lw correctly, ut in time the dvntge of ssuming tht ll the currents leve node rther thn identifying specific direction for ech rnch will ecome ovious. (The sme type of dvntge is ssocited with ssuming tht ll the mesh currents re clockwise when pplying mesh nlysis.) XAMPL 8.9 Apply nodl nlysis to the network of Fig Solution: Steps nd 2: The network hs two nodes, s shown in Fig The lower node is defined s the reference node t ground potentil (zero volts), nd the other node s V, the voltge from node to ground. Step 3: I nd I 2 re defined s leving the node in Fig. 8.42, nd Kirchhoff s current lw is pplied s follows: I I I 2 The current I 2 is relted to the nodl voltge V y Ohm s lw: I 2 The current I is lso determined y Ohm s lw s follows: I with V R V Sustituting into the Kirchhoff s current lw eqution: I nd rerrnging, we hve V V I V R R or V R R2 V R2 R2 R2 V R R V R V R2 V R2 R I R R2 R R R 6 24 V 6 24 V 2 FIG xmple 8.9. V 2 I (0 V) I A A FIG. 8.4 Network of Fig with ssigned nodes. R I 6 24 V V I 2 2 (0 V) I A FIG Applying Kirchhoff s current lw to the node V.

26 280 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Sustituting numericl vlues, we otin R 8 64 V 4 I 2 A 0 V 6 2 V 5 A 4 V 20 V 24 V A 4 A A 6 The currents I nd I 2 cn then e determined using the preceding equtions: FIG xmple V 20 V 24 V 4V I R A V R 8 4 I 2 A V 2 0 The minus sign indictes simply tht the current I hs direction opposite to tht ppering in Fig V 20 V I A R V XAMPL 8.20 Apply nodl nlysis to the network of Fig FIG Defining the nodes for the network of Fig I R V 8 I 2 4 I 2 A V 2 0 Solution : Steps nd 2: The network hs three nodes, s defined in Fig. 8.44, with the ottom node gin defined s the reference node (t ground potentil, or zero volts), nd the other nodes s V nd V 2. Step 3: For node V the currents re defined s shown in Fig. 8.45, nd Kirchhoff s current lw is pplied: 0 I I 2 I with I V R 64 V V R2 V V 2 nd I 2 R2 R2 FIG Applying Kirchhoff s current lw to node V. V V V 2 so tht I 0 R V V V 2 or I 0 R R R2 R2 R2 V 4 I I 2 V 2 nd V V R R2 2 R2 Sustituting vlues: I R R 8 2 A I 3 0 V V V 2 A 6 A 8 64 V For node V 2 the currents re defined s shown in Fig. 8.46, nd Kirchhoff s current lw is pplied: I I 2 I 3 FIG Applying Kirchhoff s current lw to node V 2. V with I V 2 V 2 R2 R3

27 N A NODAL ANALYSIS (GNRAL APPROACH) 28 or I nd V 2 V I Sustituting vlues: V 2 V 2 A Step 4: The result is two equtions nd two unknowns: V V 2 6 A 4 R2 8 V 2 R2 R3 4 4 V R2 V 2 R3 4 0 V V 2 2 A R2 which ecome Using determinnts, 0.375V 0.25V V 0.35V 2 2 V V V V Since is greter thn V, the current I flows from ground to V nd is equl to V 64 V V I R A R 8 The positive vlue for V 2 results in current I R3 from node V 2 to ground equl to V R3 V V I R3 R A R3 0 Since V is greter thn V 2, the current I R2 flows from V to V 2 nd is equl to V V V V I R2.273 A R2 4 Mthcd Solution: For this exmple, we will use Mthcd to work directly with the Kirchhoff s current lw equtions rther thn tking the mthemticl process down the line to more fmilir forms. Simply define everything correctly, provide the Guess vlues, nd insert Given where required. The process should e quite strightforwrd. Note in Fig tht the first eqution comes from the fct tht I I 2 I 0 while the second eqution comes from I 2 I 3 I. Py prticulr ttention to the fct tht the first eqution is defined y Fig nd the second y Fig ecuse the direction of I 2 is different for ech. The results of V V nd V V confirm the theoreticl solution.

28 282 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A FIG Using Mthcd to verify the mthemticl clcultions of xmple XAMPL 8.2 Determine the nodl voltges for the network of Fig A R A FIG xmple 8.2. Solution: Steps nd 2: As indicted in Fig I 3 V V 2 = 2 4 A R 2 I 6 2 A Reference FIG Defining the nodes nd pplying Kirchhoff s current lw to the node V.

29 N A NODAL ANALYSIS (GNRAL APPROACH) 283 Step 3: Included in Fig for the node V. Applying Kirchhoff s current lw: 4 A I I 3 V V V 2 V V V 2 nd 4 A R R3 2 2 xpnding nd rerrnging: V V 2 4 A For node V 2 the currents re defined s in Fig V I 3 V 2 = 2 4 A R 2 6 I 2 2 A Reference FIG Applying Kirchhoff s current lw to the node V 2. Applying Kirchhoff s current lw: 0 I 3 I 2 2 A V 2 V V 2 V 2 V V 2 nd 2 A 0 2 A 0 R3 R2 2 6 xpnding nd rerrnging: V 2 V 2 A resulting in two equtions nd two unknowns (numered for lter reference): producing 2 V V 2 4 A (8.3) V 2 V 2 A V V 2 4 7V V V V 2 2 V 3V nd V 6 V V 2 6 V 20 20

30 284 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Since V is greter thn V 2, the current through psses from V to V 2. Its vlue is V V 2 6V (6V) 2 V I R3 A R3 2 2 The fct tht V is positive results in current I R from V to ground equl to V R V 6V I R R 3 A Finlly, since V 2 is negtive, the current I R2 flows from ground to V 2 nd is equl to V R2 V 2 6V I R2 R2 A R2 6 Supernode On occsion there will e independent voltge sources in the network to which nodl nlysis is to e pplied. In such cses we cn convert the voltge source to current source (if series resistor is present) nd proceed s efore, or we cn introduce the concept of supernode nd proceed s follows. Strt s efore nd ssign nodl voltge to ech independent node of the network, including ech independent voltge source s if it were resistor or current source. Then mentlly replce the independent voltge sources with short-circuit equivlents, nd pply Kirchhoff s current lw to the defined nodes of the network. Any node including the effect of elements tied only to other nodes is referred to s supernode (since it hs n dditionl numer of terms). Finlly, relte the defined nodes to the independent voltge sources of the network, nd solve for the nodl voltges. The next exmple will clrify the definition of supernode. XAMPL 8.22 Determine the nodl voltges V nd V 2 of Fig. 8.5 using the concept of supernode. V 0 V 2 2 V 6 A R A FIG. 8.5 xmple Solution: Replcing the independent voltge source of 2 V with short-circuit equivlent will result in the network of Fig ven though the mentl ppliction of short-circuit equivlent is discussed ove, it would e wise in the erly stge of development to redrw the

31 N A NODAL ANALYSIS (GNRAL APPROACH) 285 I 3 0 I 3 Supernode V V 2 I I 2 6 A R A FIG Defining the supernode for the network of Fig network s shown in Fig The result is single supernode for which Kirchhoff s current lw must e pplied. Be sure to leve the other defined nodes in plce nd use them to define the currents from tht region of the network. In prticulr, note tht the current I 3 will leve the supernode t V nd then enter the sme supernode t V 2.Itmust therefore pper twice when pplying Kirchhoff s current lw, s shown elow: Σ I i Σ I o or 6 A I 3 I I 2 4 A I 3 I I 2 6 A 4 A 2 A V R V 2 R2 Then 2 A V V 2 nd 2 A 4 2 Relting the defined nodl voltges to the independent voltge source, we hve V V 2 2 V which results in two equtions nd two unknowns: 0.25V 0.5V 2 2 V V 2 2 Sustituting: V V (V 2 2) 0.5V 2 2 nd 0.75V so tht V V 0.75 nd V V 2 2 V.333 V 2 V V The current of the network cn then e determined s follows: V V I A R 4 V V I A R2 2 V V V (.333 V) 2 V I 3.2 A 0 0 0

32 286 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A A creful exmintion of the network t the eginning of the nlysis would hve reveled tht the voltge cross the resistor must e 2 V nd I 3 must e equl to.2 A. 8.0 NODAL ANALYSIS (FORMAT APPROACH) A close exmintion of q. (8.3) ppering in xmple 8.2 revels tht the suscripted voltge t the node in which Kirchhoff s current lw is pplied is multiplied y the sum of the conductnces ttched to tht node. Note lso tht the other nodl voltges within the sme eqution re multiplied y the negtive of the conductnce etween the two nodes. The current sources re represented to the right of the equls sign with positive sign if they supply current to the node nd with negtive sign if they drw current from the node. These conclusions cn e expnded to include networks with ny numer of nodes. This will llow us to write nodl equtions rpidly nd in form tht is convenient for the use of determinnts. A mjor requirement, however, is tht ll voltge sources must first e converted to current sources efore the procedure is pplied. Note the prllelism etween the following four steps of ppliction nd those required for mesh nlysis in Section 8.8:. Choose reference node nd ssign suscripted voltge lel to the (N ) remining nodes of the network. 2. The numer of equtions required for complete solution is equl to the numer of suscripted voltges (N ). Column of ech eqution is formed y summing the conductnces tied to the node of interest nd multiplying the result y tht suscripted nodl voltge. 3. We must now consider the mutul terms tht, s noted in the preceding exmple, re lwys sutrcted from the first column. It is possile to hve more thn one mutul term if the nodl voltge of current interest hs n element in common with more thn one other nodl voltge. This will e demonstrted in n exmple to follow. ch mutul term is the product of the mutul conductnce nd the other nodl voltge tied to tht conductnce. 4. The column to the right of the equlity sign is the lgeric sum of the current sources tied to the node of interest. A current source is ssigned positive sign if it supplies current to node nd negtive sign if it drws current from the node. 5. Solve the resulting simultneous equtions for the desired voltges. Let us now consider few exmples.

33 N A NODAL ANALYSIS (FORMAT APPROACH) 287 XAMPL 8.23 Write the nodl equtions for the network of Fig I 2 A R 6 I 2 3 A 4 FIG xmple Solution: Step : The figure is redrwn with ssigned suscripted voltges in Fig V V 2 3 I 2 A R 6 I 2 3 A 4 Reference FIG Defining the nodes for the network of Fig Steps 2 to 4: Drwing current from node V : V V A Sum of conductnces connected to node Mutul conductnce Supplying current to node 2 V 2 : V 2 V A Sum of conductnces connected to node 2 Mutul conductnce nd V V V V

34 288 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A XAMPL 8.24 Find the voltge cross the 3- resistor of Fig y nodl nlysis. 8 V V 3 3 V FIG xmple Solution: hve Converting sources nd choosing nodes (Fig. 8.56), we V V A 2 4 V A Reference FIG Defining the nodes for the network of Fig V V 2 4 A V 2 V 0. A V V V V resulting in V 2V V 8V 2 3 nd V 2 V 3.0 V As demonstrted for mesh nlysis, nodl nlysis cn lso e very useful technique for solving networks with only one source.

35 N A NODAL ANALYSIS (FORMAT APPROACH) 289 XAMPL 8.25 Using nodl nlysis, determine the potentil cross the 4- resistor in Fig Solution : The reference nd four suscripted voltge levels were chosen s shown in Fig A moment of reflection should revel tht for ny difference in potentil etween V nd V 3, the current through nd the potentil drop cross ech 5- resistor will e the sme. Therefore, V 4 is simply midvoltge level etween V nd V 3 nd is known if V nd V 3 re ville. We will therefore not include it in nodl voltge nd will redrw the network s shown in Fig Understnd, however, tht V 4 cn e included if desired, lthough four nodl voltges will result rther thn the three to e otined in the solution of this prolem A 2 FIG xmple V : V V 2 V 3 0 V V 2 : V 2 V V 3 3 A V 3 : V 3 V 2 V 0 V 2 V 2 2 V 3 which re rewritten s.v 0.5V 2 0.V 3 0 V 2 0.5V 0.5V V 3 0.5V 2 0.V 0 For determinnts, c.v 0.5V 2 0.V V V 2 0.5V V 0.5V V 3 0 V 2 3 A (0 V) 4 FIG Defining the nodes for the network of Fig V 2 2 V 3 Before continuing, note the symmetry out the mjor digonl in the eqution ove. Recll similr result for mesh nlysis. xmples 8.23 nd 8.24 lso exhiit this property in the resulting equtions. Keep this thought in mind s check on future pplictions of nodl nlysis. 2 3 A (0 V) V 3 V V FIG Reducing the numer of nodes for the network of Fig y comining the two 5- resistors. Mthcd Solution: By now the sequence of steps necessry to solve series of equtions using Mthcd should e quite fmilir nd less thretening thn the first encounter. For this exmple, ll the prmeters were entered in the three simultneous equtions, voiding the

36 290 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A need to define ech prmeter of the network. Simply provide Guess t the three nodl voltges, pply the word Given, nd enter the three equtions properly s shown in Fig It does tke some prctice to ensure tht the rcket is moved to the proper loction efore mking n entry, ut this is simply prt of the rules set up to mintin control of the opertions to e performed. Finlly, request the desired nodl voltges using the correct formt. The numericl results will pper, gin confirming our theoreticl solutions. FIG Using Mthcd to verify the mthemticl clcultions of xmple The next exmple hs only one source pplied to ldder network. XAMPL 8.26 Write the nodl equtions nd find the voltge cross the 2- resistor for the network of Fig V FIG. 8.6 xmple 8.26.

37 N A BRIDG NTWORKS 29 Solution: The nodl voltges re chosen s shown in Fig V V 2 V A (0 V) FIG Converting the voltge source to current source nd defining the nodes for the network of Fig V : V V V V 2 : V 2 V V V 3 : V 3 V nd 0.5V 0.25V V V 2 V V 2.5V 3 0 Note the symmetry present out the mjor xis. Appliction of determinnts revels tht V 3 V V 8. BRIDG NTWORKS This section introduces the ridge network, configurtion tht hs multitude of pplictions. In the chpters to follow, it will e employed in oth dc nd c meters. In the electronics courses it will e encountered erly in the discussion of rectifying circuits employed in converting vrying signl to one of stedy nture (such s dc). A numer of other res of ppliction lso require some knowledge of c networks; these res will e discussed lter. The ridge network my pper in one of the three forms s indicted in Fig The network of Fig. 8.63(c) is lso clled symmetricl lttice network if nd R R 4. Figure 8.63(c) is n excellent exmple of how plnr network cn e mde to pper nonplnr. For the purposes of investigtion, let us exmine the network of Fig using mesh nd nodl nlysis.

38 292 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A R R 5 R R 5 R R 4 R 5 R 4 R 4 () () (c) FIG Vrious formts for ridge network. R 2 R s 3 4 R 5 20 V 5 2 R 4 FIG Stndrd ridge configurtion. R s 3 R 4 2 R5 I2 20 V I 5 2 R 4 I 3 FIG Assigning the mesh currents to the network of Fig V V 2 I R s A R 4 R5 5 R 4 2 (0 V) 2 FIG Defining the nodl voltges for the network of Fig V 3 Mesh nlysis (Fig. 8.65) yields (3 4 2 )I (4 )I 2 (2 )I 3 20 V (4 5 2 )I 2 (4 )I (5 )I 3 0 (2 5 )I 3 (2 )I (5 )I 2 0 nd 009I 4I 2 2I I I 2 5I 3 0 2I 5I 2 8I 3 0 with the result tht I 4 A I A I A The net current through the 5- resistor is I 5 I 2 I A A 0 A Nodl nlysis (Fig. 8.66) yields nd V V 2 20 V 3 A V 2 V V V 3 V V V V 2 20 V 3 A V V 2 V V V 2 V 3 0 Note the symmetry of the solution. With the TI-86 clcultor, the top prt of the determinnt is determined y the following (tke note of the clcultions within prentheses): det[[20/3,/4,/2][0,(/4/2/5),/5][0,/5,(/5/2/)]] NTR 0.5 CALC. 8.4

39 N A BRIDG NTWORKS 293 with the ottom of the determinnt determined y: det[[(/3/4/2),/4,/2][/4,(/4/2/5),/5][/2,/5,(/5/2/)]] NTR.32 CALC. 8.5 Finlly, 0.5/.32 NTR 8 CALC. 8.6 nd V 8 V Similrly, V V nd V V nd the voltge cross the 5- resistor is V 5 V 2 V V V 0 V Since V 5 0V,wecn insert short in plce of the ridge rm without ffecting the network ehvior. (Certinly V IR I (0) 0V.) In Fig. 8.67, short circuit hs replced the resistor R 5, nd the voltge cross R 4 is to e determined. The network is redrwn in Fig. 8.68, nd V (2 )20 V (2 ) (4 2 ) 3 2 (20 V) (20 V) (voltge divider rule) R s 3 20 V R 4 V = 0 2 R 4 2 V 2(20 V) 40 V V s otined erlier. We found through mesh nlysis tht I 5 0A,which hs s its equivlent n open circuit s shown in Fig. 8.69(). (Certinly I V/R 0/( ) 0A.) The voltge cross the resistor R 4 will gin e determined nd compred with the result ove. The network is redrwn fter comining series elements, s shown in Fig. 8.69(), nd (6 3 )(20 V) 2 (20 V) V 3 8 V (8 V) 8 V nd V V 2 3 s ove. The condition V 5 0 V or I 5 0 A exists only for prticulr reltionship etween the resistors of the network. Let us now derive this reltionship using the network of Fig. 8.70, in which it is indicted tht I 0 A nd V 0 V. Note tht resistor R s of the network of Fig will not pper in the following nlysis. The ridge network is sid to e lnced when the condition of I 0AorV 0Vexists. If V 0 V (short circuit etween nd ), then FIG Sustituting the short-circuit equivlent for the lnce rm of lnced ridge. R s 3 R V 2 R 4 V FIG Redrwing the network of Fig V V 2

40 294 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A R s 3 20 V R 4 I = 0 2 R 4 2 V R s 3 20 V 6 3 () () FIG Sustituting the open-circuit equivlent for the lnce rm of lnced ridge. nd I R I 2 R s V I R V = 0 I 3 I 2 V 2 V 3 I = 0 I 4 R 4V4 FIG stlishing the lnce criteri for ridge network. or In ddition, when V 0 V, I V 3 V 4 nd I 3 I 4 R 4 If we set I 0 A, then I 3 I nd I 4 I 2, with the result tht the ove eqution ecomes I I 2 R 4 Sustituting for I from ove yields I 2 R I 2 I 2 R 4 R R or, rerrnging, we hve R 4 R = R 4 FIG. 8.7 A visul pproch to rememering the lnce condition. (8.4) This conclusion sttes tht if the rtio of R to is equl to tht of to R 4, the ridge will e lnced, nd I 0 A or V 0 V. A method of memorizing this form is indicted in Fig For the exmple ove, R 4, 2, 2, R 4, nd R R3 R R R R R The emphsis in this section hs een on the lnced sitution. Understnd tht if the rtio is not stisfied, there will e potentil drop cross the lnce rm nd current through it. The methods just descried (mesh nd nodl nlysis) will yield ny nd ll potentils or currents desired, just s they did for the lnced sitution. 8.2 Y-D (T-p) AND D-Y (p-t) CONVRSIONS Circuit configurtions re often encountered in which the resistors do not pper to e in series or prllel. Under these conditions, it my e necessry to convert the circuit from one form to nother to solve for

41 N A Y-D (T-p) AND D-Y (p-t) CONVRSIONS 295 ny unknown quntities if mesh or nodl nlysis is not pplied. Two circuit configurtions tht often ccount for these difficulties re the wye (Y) nd delt () configurtions, depicted in Fig. 8.72(). They re lso referred to s the tee (T) nd pi (), respectively, s indicted in Fig. 8.72(). Note tht the pi is ctully n inverted delt. R R C R R B R A R B R A R C () () FIG The Y (T) nd D (p) configurtions. The purpose of this section is to develop the equtions for converting from D to Y, or vice vers. This type of conversion will normlly led to network tht cn e solved using techniques such s those descried in Chpter 7. In other words, in Fig. 8.73, with terminls,, nd c held fst, if the wye (Y) configurtion were desired insted of the inverted delt (D) configurtion, ll tht would e necessry is direct ppliction of the equtions to e derived. The phrse insted of is emphsized to ensure tht it is understood tht only one of these configurtions is to pper t one time etween the indicted terminls. It is our purpose (referring to Fig. 8.73) to find some expression for R,, nd in terms of R A, R B, nd R C, nd vice vers, tht will ensure tht the resistnce etween ny two terminls of the Y configurtion will e the sme with the D configurtion inserted in plce of the Y configurtion (nd vice vers). If the two circuits re to e equivlent, the totl resistnce etween ny two terminls must e the sme. Consider terminls -c in the D-Y configurtions of Fig R R C R B c R A FIG Introducing the concept of D-Y or Y-D conversions. R C R R C R -c RB R R A -c c xternl to pth of mesurement R -c R B RA c c FIG Finding the resistnce R -c for the Y nd D configurtions.

42 296 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A Let us first ssume tht we wnt to convert the D (R A,R B,R C )tothey (R,, ). This requires tht we hve reltionship for R,, nd in terms of R A,R B, nd R C.Ifthe resistnce is to e the sme etween terminls -c for oth the D nd the Y, the following must e true: R -c (Y) R -c (D) so tht RB(RA R C ) R -c R RB ( R A RC) (8.5) Using the sme pproch for - nd -c, we otin the following reltionships: R C (RA R B ) R - R RC ( R A RB) (8.5) nd R A (RB R C ) R -c RA ( R B RC) (8.5c) Sutrcting q. (8.5) from q. (8.5), we hve R C R B R C R A R B R A R B R C (R ) (R ) RA R B R C RA R B R C so tht R R A RC A RB RA R R B C (8.5d) Sutrcting q. (8.5d) from q. (8.5c) yields ( ) ( ) so tht R A R B R A R C RA R B R C 2RBRA 2 RA R resulting in the following expression for in terms of R A, R B, nd R C : B R C R A R C R B R A RA R B R C RA R B RA R R C B (8.6) Following the sme procedure for R nd, we hve R C R RA RB R C B R (8.6) nd R C RA RB R C A R (8.6c) Note tht ech resistor of the Y is equl to the product of the resistors in the two closest rnches of the D divided y the sum of the resistors in the D.

43 N A Y-D (T-p) AND D-Y (p-t) CONVRSIONS 297 To otin the reltionships necessry to convert from Y to D, first divide q. (8.6) y q. (8.6): R (R A R B )/(R A R B R C ) RA (R B R C )/(R A R B R C ) R C or R A R C R Then divide q. (8.6) y q. (8.6c): R2 (R A R B )/(R A R B R C ) RB (R A R C )/(R A R B R C ) R C or R B R C R2 Sustituting for R A nd R B in q. (8.6c) yields (R C /R )R C ( R C / ) (R C /R ) R C ( /R )R C ( / ) ( /R ) Plcing these over common denomintor, we otin ( R C /R ) (R R )/(R ) R C R R R R nd R C (8.7) R3 We follow the sme procedure for R B nd R A : R A R R R (8.7) R R nd R B (8.7c) Note tht the vlue of ech resistor of the D is equl to the sum of the possile product comintions of the resistnces of the Y divided y the resistnce of the Y frthest from the resistor to e determined. Let us consider wht would occur if ll the vlues of D or Y were the sme. If R A R B R C, qution (8.6) would ecome (using R A only) the following: 2 R ARB R ARA R A R A RA RB R C RA RA R A 3 RA 3 nd, following the sme procedure, R2 R R A 3 R A 3

44 298 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A In generl, therefore, R Y R D 3 (8.8) or R D 3R Y (8.8) which indictes tht for Y of three equl resistors, the vlue of ech resistor of the D is equl to three times the vlue of ny resistor of the Y. If only two elements of Y or D re the sme, the corresponding D or Y of ech will lso hve two equl elements. The converting of equtions will e left s n exercise for the reder. The Y nd the D will often pper s shown in Fig They re then referred to s tee (T) nd pi () network, respectively. The equtions used to convert from one form to the other re exctly the sme s those developed for the Y nd D trnsformtion. 3 3 R R C R B R A () () FIG The reltionship etween the Y nd T configurtions nd the D nd p configurtions. XAMPL 8.27 Convert the D of Fig to Y. R C 0 R 3 /3 5 R B 20 R A 30 0 c c c c FIG xmple FIG The Y equivlent for the D of Fig

45 N A Y-D (T-p) AND D-Y (p-t) CONVRSIONS 299 Solution: R B R (20 )(0 ) 200 R C 3 3 RA R B R C R A R (30 )(0 ) 300 C 5 RA R B R C R A R B (20 )(30 ) RA R B R C R The equivlent network is shown in Fig (pge 298). c c XAMPL 8.28 Convert the Y of Fig to D. Solution: R A R R R (60 )(60 ) (60 )(60 ) (60 )(60 ) R A 80 However, the three resistors for the Y re equl, permitting the use of q. (8.8) nd yielding R D 3R Y 3(60 ) 80 nd R B R C 80 The equivlent network is shown in Fig , c FIG xmple R C 80 R B 80 R A c 80 FIG The D equivlent for the Y of Fig XAMPL 8.29 Find the totl resistnce of the network of Fig. 8.80, where R A 3, R B 3, nd R C 6. Solution: Two resistors of the D were equl; therefore, two resistors of the Y will e equl. R B R (3 )(6 ) 8 R C.5 RA R B R C R A R (3 )(6 ) 8 C.5 RA R B R C 2 2 R A R B (3 )(3 ) RA R B R C 2 2 Replcing the D y the Y, s shown in Fig. 8.8, yields (4.5 )(2.5 ) R T 0.75 (4.5 ) (2.5 ) (5.5 )(3.5 ) R T R T R T 4 2 R C R B 3 R A 6 c FIG xmple R FIG. 8.8 Sustituting the Y equivlent for the ottom D of Fig c

46 300 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A XAMPL 8.30 Find the totl resistnce of the network of Fig R T c 6 d FIG xmple Solutions: Since ll the resistors of the D or Y re the sme, qutions (8.8) nd (8.8) cn e used to convert either form to the other.. Converting the D to Y. Note: When this is done, the resulting d of the new Y will e the sme s the point d shown in the originl figure, only ecuse oth systems re lnced. Tht is, the resistnce in ech rnch of ech system hs the sme vlue: R D 6 R Y 2 (Fig. 8.83) d* c c FIG Converting the D configurtion of Fig to Y configurtion. R T 2 2 c 9 d, d FIG Sustituting the Y configurtion for the converted D into the network of Fig The network then ppers s shown in Fig R T 2 (2 )(9 ) Converting the Y to D: R D 3R Y (3)(9 ) 27 (Fig. 8.85) (6 )(27 ) 62 R T R R 2R R T T (R T R T ) T 2R T 3 T 3R T R T (R T R T ) 2(4.909 ) which checks with the previous solution. R T c 6 FIG Sustituting the converted Y configurtion into the network of Fig

47 N A APPLICATIONS APPLICATIONS The Applictions section of this chpter will discuss the constnt current chrcteristic in the design of security systems, the ridge circuit in common residentil smoke detector, nd the nodl voltges of digitl logic proe. Constnt Current Alrm Systems The sic components of n lrm system employing constnt current supply re provided in Fig This design is improved over tht provided in Chpter 5 in the sense tht it is less sensitive to chnges in resistnce in the circuit due to heting, humidity, chnges in the length of the line to the sensors, nd so on. The.5-k rheostt (totl resistnce etween points nd ) is djusted to ensure current of 5 ma through the single-series security circuit. The djustle rheostt is necessry to compenste for vritions in the totl resistnce of the circuit introduced y the resistnce of the wire, sensors, sensing rely, nd millimmeter. The millimmeter is included to set the rheostt nd ensure current of 5 ma. Sensing rely Door switch Window foil Mgnetic switch 5 ma kω To ell circuit N/C N/O 5 5 ma kω 0-mA movement Rheostt 0.5 kω 0 V FIG Constnt current lrm system. If ny of the sensors should open, the current through the entire circuit will drop to zero, the coil of the rely will relese the plunger, nd contct will e mde with the N/C position of the rely. This ction will complete the circuit for the ell circuit, nd the lrm will sound. For the future, keep in mind tht switch positions for rely re lwys shown with no power to the network, resulting in the N/C position of Fig When power is pplied, the switch will hve the position indicted y the dshed line. Tht is, vrious fctors, such s chnge in resistnce of ny of the elements due to heting, humidity, nd so on, would cuse the pplied voltge to redistriute itself nd crete sensitive sitution. With n djusted 5 ma, the loding cn chnge, ut the current will lwys e 5 ma nd the chnce of tripping reduced. Tke note of the fct tht the rely is rted s 5 V t 5 ma, indicting tht in the on stte the voltge cross the rely is 5 V nd the current through the rely 5 ma. Its internl resistnce is therefore 5 V/5 ma k in this stte. A more dvnced lrm system using constnt current is provided in Fig In this cse n electronic system employing single trn-

48 302 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A 5 V Door switch 5 V 4 ma R Window foil Mgnetic switch 2 ma 4 ma R ref 3 5 V Op-Amp LM2900 Constnt R current source Output To lrm ell circuit On pckge to identify pin numers 3 Input 2 Input 0 V () 200 µa 7 () V high R series 7 (c) Dul-in-line pckge V INPUT 3 INPUT 4 INPUT 4 OUTPUT 4 OUTPUT 3 INPUT INPUT INPUT 2 INPUT 2 OUTPUT 2 OUTPUT INPUT GND TOP VIW V 4 V low R low 3 4 Output Op-Amp FIG LM2900 opertionl mplifier: () dul-inline pckge (DIP); () components; (c) impct of low-input impednce. FIG Constnt current lrm system with electronic components. sistor, ising resistors, nd dc ttery re estlishing current of 4 ma through the series sensor circuit connected to the positive side of n opertionl mplifier (op-mp). Although the trnsistor nd op-mp devices my e new to you, they will e discussed in detil in your electronics courses you do not need to e wre of the detils of their opertion for now. Suffice it to sy for the moment tht the trnsistor in this ppliction is eing used not s n mplifier ut s prt of design to estlish constnt current through the circuit. The op-mp is very useful component of numerous electronic systems, nd it hs importnt terminl chrcteristics estlished y vriety of components internl to its design. The LM2900 opertionl mplifier of Fig is one of four found in the dul-in-line integrted circuit pckge ppering in Fig. 8.88(). Pins 2, 3, 4, 7, nd 4 were used for the design of Fig Note in Fig. 8.88() the numer of elements required to estlish the desired terminl chrcteristics the detils of which will e investigted in your electronics courses. In Fig. 8.87, the designed 5-V dc supply, ising resistors, nd trnsistor in the upper right-hnd corner of the schemtic estlish constnt 4-mA current through the circuit. It is referred to s constnt current source ecuse the current will remin firly constnt t 4 ma even though there my e moderte vritions in the totl resistnce of the series sensor circuit connected to the trnsistor. Following the 4 ma through the circuit, we find tht it enters terminl 2 (positive side of the input) of the op-mp. A second current of 2 ma, clled the reference current, is estlished y the 5-V source nd resistnce R nd enters terminl 3 (negtive side of the input) of the op-mp. The reference current of 2 ma is necessry to estlish current for the 4-mA current of the network to e compred ginst. So long s the 4-mA current exists, the opertionl mplifier will provide high output voltge tht exceeds 3.5 V, with typicl level of 4.2 V (ccording to the specifiction sheet for the op-mp). However, if the sensor current drops from 4 ma to level elow the reference level of 2 ma, the op-mp will respond with low output voltge tht is typiclly out 0. V. The output of the opertionl mplifier will then signl the lrm circuit out the disturnce. Note from the ove tht it is not necessry for the sensor current to drop to 0 ma to signl the lrm circuit just vrition round the reference level tht ppers unusul. One very importnt chrcteristic of this prticulr op-mp is tht the input impednce to the op-mp is reltively low. This feture is importnt ecuse you don t wnt lrm circuits recting to every voltge spike or turulence tht comes down the line ecuse of externl switching ction

49 N A APPLICATIONS 303 or outside forces such s lightning. In Fig. 8.88(c), for instnce, if high voltge should pper t the input to the series configurtion, most of the voltge will e sored y the series resistnce of the sensor circuit rther thn trveling cross the input terminls of the opertionl mplifier thus preventing flse output nd n ctivtion of the lrm. Whetstone Bridge Smoke Detector TheWhetstone ridge is populr network configurtion whenever detection of smll chnges in quntity is required. In Fig. 8.89(), the dc ridge configurtion is employing photoelectric device to detect the presence of smoke nd to sound the lrm. A photogrph of n ctul photoelectric smoke detector ppers in Fig. 8.89(), nd the internl construction of the unit is shown in Fig. 8.89(c). First note tht ir vents re provided to permit thesmoketoenterthechmerelowtheclerplstic.theclerplsticwill prevent the smoke from entering the upper chmer ut will permit the light Blnce djust R lnce Smoke detector Lmp DC power V lnce R Reference Sensitive rely N/C To lrm circuit N/O () Test module socket LD (light-emitting diode) Screen Recessed test switch () FIG. 8.89()() Whetstone ridge detector: () dc ridge configurtion; () outside ppernce.

50 Ceiling Reflector Photoconductive cells (Resistnce function of pplied light) Reference cell Smoke detector Seled chmer Solid rrier Reflector Light source Cler plstic Room Vents for the pssge of ir or smoke FIG. 8.89(c) Whetstone ridge smoke detector: (c) internl construction. (c) 304 from the ul in the upper chmer to ounce off the lower reflector to the semiconductor light sensor ( cdmium photocell) t the left side of the chmer. The cler plstic seprtion ensures tht the light hitting the light sensor in the upper chmer is not ffected y the entering smoke. It estlishes reference level to compre ginst the chmer with the entering smoke. If no smoke is present, the difference in response etween the sensor cells will e registered s the norml sitution. Of course, if oth cells were exctly identicl, nd if the cler plstic did not cut down on the light, oth sensors would estlish the sme reference level, nd their difference would e zero. However, this is seldom the cse, so reference difference is recognized s the sign tht smoke is not present. However, once smoke is present, there will e shrp difference in the sensor rection from the norm, nd the lrm should e sounded. In Fig. 8.89(), we find tht the two sensors re locted on opposite rms of the ridge. With no smoke present the lnce-djust rheostt will e used to ensure tht the voltge V etween points nd is zero volts nd the resulting current through the primry of the sensitive rely will e zero mperes. Tking look t the rely, we find tht the sence of voltge from to will leve the rely coil unenergized nd the switch in the N/O position (recll tht the position of rely switch is lwys drwn in the unenergized stte). An unlnced sitution will result in voltge cross the coil nd ctivtion of the rely, nd the switch will move to the N/C position to complete the lrm circuit nd ctivte the lrm. Relys with two contcts nd one movle rm re clled single-poledoule-throw (SPDT) relys. The dc power is required to set up the lnce sitution, energize the prllel ul so we know tht the system is on, nd provide the voltge from to if n unlnced sitution should develop. One my sk why only one sensor isn t used since its resistnce would e sensitive to the presence of smoke. The nswer lies in the fct tht the smoke detector might generte flse redout if the supply voltge or output light intensity of the ul should vry. Smoke detectors of the type just descried must e used in gs sttions, kitchens, dentist offices, etc., where the rnge of gs fumes present my set off n ionizing type smoke detector.

51 N A APPLICATIONS 305 Schemtic with Nodl Voltges When n investigtor is presented with system tht is down or not operting properly, one of the first options is to check the system s specified voltges on the schemtic. These specified voltge levels re ctully the nodl voltges determined in this chpter. Nodl voltge is simply specil term for voltge mesured from tht point to ground. The technicin will ttch the negtive or lower-potentil led to the ground of the network (often the chssis) nd then plce the positive or higher-potentil led on the specified points of the network to check the nodl voltges. If they mtch, it is good sign tht tht section of the system is operting properly. If one or more fil to mtch the given vlues, the prolem re cn usully e identified. Be wre tht reding of 5.87 V is significntly different from n expected reding of 6 V if the leds hve een properly ttched. Although the ctul numers seem close, the difference is ctully more thn 30 V. One must expect some devition from the given vlue s shown, ut lwys e very sensitive to the resulting sign of the reding. The schemtic of Fig. 8.90() includes the nodl voltges for logic proe used to mesure the input nd output sttes of integrted circuit logic chips. In other words, the proe determines whether the mesured voltge is one of two sttes: high or low (often referred to s on or off or or 0). If the LOGIC IN terminl of the proe is plced on chip t loction where the voltge is etween 0 nd.2 V, the voltge is considered low level, nd the green LD will light. (LDs re lightemitting semiconductor diodes tht will emit light when current is pssed through them.) If the mesured voltge is etween.8 V nd 5V, the reding is considered high, nd the red LD will light. Any voltge etween.2 V nd.8 V is considered floting level nd is n indiction tht the system eing mesured is not operting correctly. Note tht the reference levels mentioned ove re estlished y the voltge divider network to the right of the schemtic. The op-mps employed re of such high input impednce tht their loding on the voltge divider network cn e ignored nd the voltge divider network considered network unto itself. ven though three 5.5-V dc supply voltges re indicted on the digrm, e wre tht ll three points re connected to the sme supply. The other voltges provided (the nodl voltges) re the voltge levels tht should e present from tht point to ground if the system is working properly. The op-mps re used to sense the difference etween the reference t points 3 nd 6 nd the voltge picked up in LOGIC IN. Any difference will result in n output tht will light either the green or the red LD. Be wre, ecuse of the direct connection, tht the voltge t point 3 is the sme s shown y the nodl voltge to the left, or.8 V. Likewise, the voltge t point 6 is.2 V for comprison with the voltges t points 5 nd 2, which reflect the mesured voltge. If the input voltge hppened to e.0 V, the difference etween the voltges t points 5 nd 6 would e 0.2 V, which idelly would pper t point 7. This low potentil t point 7 would result in current flowing from the much higher 5.5-V dc supply through the green LD, cusing it to light nd indicting low condition. By the wy, LDs, like diodes, permit current through them only in the direction of the rrow in the symol. Also note tht the voltge t point 6 must e higher thn tht t point 5 for the output to turn on the LD. The sme is true for point 2 over point 3, which revels why the red LD does not light when the.0-v level is mesured.

52 306 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A 5.5 V R.8 V.5 V.2 V R kω 560 Ω R 5 MΩ 560 Ω 2.2 kω 5.5 V U2A 3 4 LM324 2 High 5.5 V 5 4 U2B Low LM LD Red R 7.2 kω LD 2 Green 5.5 V () R 6 0 kω TP LOGIC IN 5.5 V R.8 V.5 V.2 V R kω 560 Ω R 5 MΩ 560 Ω 2.2 kω 5.5 V U2A 3 4 LM324 2 High 5.5 V 5 4 U2B Low LM LD Red R 7.2 kω LD 2 Green 5.5 V () R 6 0 kω TP LOGIC IN IC Printed LDs IC Resistors Cpcitors circuit ord (c) FIG Logic proe: () schemtic with nodl voltges; () network with glol connections; (c) photogrph of commercilly ville unit. Oftentimes it is imprcticl to drw the full network s shown in Fig. 8.90() ecuse there re spce limittions or ecuse the sme voltge divider network is used to supply other prts of the system. In such cses one must recognize tht points hving the sme shpe re connected, nd the numer in the figure revels how mny connections re mde to tht point.

53 N A COMPUTR ANALYSIS 307 A photogrph of the outside nd inside of commercilly ville logic proe is provided in Fig. 8.90(c). Note the incresed complexity of system ecuse of the vriety of functions tht the proe cn perform. 8.4 COMPUTR ANALYSIS PSpice The ridge network of Fig will now e nlyzed using PSpice to ensure tht it is in the lnced stte. The only component tht hs not een introduced in erlier chpters is the dc current source. It cn e otined y first selecting the Plce prt key nd then the SOURC lirry. Scrolling the Prt List will result in the option IDC. A left click of IDC followed y OK will result in dc current source whose direction is towrd the ottom of the screen. One left click of the mouse (to mke it red ctive) followed y right click of the mouse will result in listing hving Mirror Verticlly option. Selecting tht option will flip the source nd give it the direction of Fig The remining prts of the PSpice nlysis re pretty strightforwrd, with the results of Fig. 8.9 mtching those otined in the nlysis of Fig The voltge cross the current source is 8 V positive to ground, nd the voltge t either end of the ridge rm is V. The voltge cross R 5 is oviously 0 V for the level of ccurcy displyed, nd the current is of such smll mgnitude compred to the other current levels of the network tht it cn essentilly e considered 0 A. Note lso for the lnced ridge tht the current through R equls tht of, nd the current through equls tht of R 4. FIG. 8.9 Applying PSpice to the ridge network of Fig

54 308 MTHODS OF ANALYSIS AND SLCTD TOPICS (dc) N A lectronics Workench lectronics Workench will now e used to verify the results of xmple 8.8. All the elements of creting the schemtic of Fig hve een presented in erlier chpters; they will not e repeted here in order to demonstrte how little documenttion is now necessry to crry you through firly complex network. FIG Using lectronics Workench to verify the results of xmple 8.8. For the nlysis, oth indictors nd meter will e used to disply the desired results. An A indictor in the H position ws used for the current through R 5, nd V indictor in the V position ws used for the voltge cross. A multimeter in the voltmeter mode ws plced to red the voltge cross R 4. The mmeter is reding the mesh or loop current for tht rnch, nd the two voltmeters re displying the nodl voltges of the network. After simultion, the results displyed re n exct mtch with those of xmple 8.8.

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