Resistive Network Analysis

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1 C H A P T E R 3 Resistive Network Anlysis his chpter will illustrte the fundmentl techniques for the nlysis of resistive circuits. The methods introduced re sed on the circuit lws presented in Chpter 2: Kirchhoff s nd Ohm s lws. The min thrust of the chpter is to introduce nd illustrte vrious methods of circuit nlysis tht will e pplied throughout the ook. The first topic is the nlysis of resistive circuits y the methods of mesh currents nd node voltges; these re fundmentl techniques, which you should mster s erly s possile. The second topic is rief introduction to the principle of superposition. Section 3.5 introduces nother fundmentl concept in the nlysis of electricl circuits: the reduction of n ritrry circuit to equivlent circuit forms (Thévenin nd Norton equivlent circuits). In this section it will e shown tht it is generlly possile to reduce ll liner circuits to one of two equivlent forms, nd tht ny liner circuit nlysis prolem cn e reduced to simple voltge or current divider prolem. The Thévenin nd Norton equivlent representtions of electricl circuits nturlly led to the description of electricl circuits in terms of sources nd lods. This notion, in turn, leds to the nlysis of the trnsfer of power etween source nd lod, nd of the phenomenon of source loding. Finlly, some grphicl nd numericl techniques re introduced for the nlysis of nonliner circuit elements. Upon completing this chpter, you should hve developed confidence in your ility to compute numericl solutions for wide rnge of resistive circuits. Good 71

2 72 Chpter 3 Resistive Network Anlysis fmilirity with the techniques illustrted in this chpter will gretly simplify the study of AC circuits in Chpter 4. The ojective of the chpter is to develop solid understnding of the following topics: Node voltge nd mesh current nlysis. The principle of superposition. Thévenin nd Norton equivlent circuits. Numericl nd grphicl (lod-line) nlysis of nonliner circuit elements. In the node voltge method, we ssign the node voltges v nd v ; the rnch current flowing from to is then expressed in terms of these node voltges. v i = v v R R i v Figure 3.1 Brnch current formultion in nodl nlysis 3.1 THE NODE VOLTAGE METHOD Chpter 2 introduced the essentil elements of network nlysis, pving the wy for systemtic tretment of the nlysis methods tht will e introduced in this chpter. You re y now fmilir with the ppliction of the three fundmentl lws of network nlysis: KCL, KVL, nd Ohm s lw; these will e employed to develop vriety of solution methods tht cn e pplied to liner resistive circuits. The mteril presented in the following sections presumes good understnding of Chpter 2. You cn resolve mny of the douts nd questions tht my occsionlly rise y reviewing the mteril presented in the preceding chpter. Node voltge nlysis is the most generl method for the nlysis of electricl circuits. In this section, its ppliction to liner resistive circuits will e illustrted. The node voltge method is sed on defining the voltge t ech node s n independent vrile. One of the nodes is selected s reference node (usully ut not necessrily ground), nd ech of the other node voltges is referenced to this node. Once ech node voltge is defined, Ohm s lw my e pplied etween ny two djcent nodes in order to determine the current flowing in ech rnch. In the node voltge method, ech rnch current is expressed in terms of one or more node voltges; thus, currents do not explicitly enter into the equtions. Figure 3.1 illustrtes how one defines rnch currents in this method. You my recll similr description given in Chpter 2. Once ech rnch current is defined in terms of the node voltges, Kirchhoff s current lw is pplied t ech node: i = 0 (3.1) By KCL: i 1 i 2 i 3 = 0. In the node voltge method, we express KCL y v v v v c v v i 1 i 2 i 3 v c v v d = 0 Figure 3.2 Use of KCL in nodl nlysis v d Figure 3.2 illustrtes this procedure. The systemtic ppliction of this method to circuit with n nodes would led to writing n liner equtions. However, one of the node voltges is the reference voltge nd is therefore lredy known, since it is usully ssumed to e zero (recll tht the choice of reference voltge is dictted mostly y convenience, s explined in Chpter 2). Thus, we cn write n 1 independent liner equtions in the n 1 independent vriles (the node voltges). Nodl nlysis provides the minimum numer of equtions required to solve the circuit, since ny rnch voltge or current my e determined from knowledge of nodl voltges. At this stge, you might wish to review Exmple 2.12, to verify tht, indeed, knowledge of the node voltges is sufficient to solve for ny other current or voltge in the circuit. The nodl nlysis method my lso e defined s sequence of steps, s outlined in the following ox:

3 Prt I Circuits 73 FOCUS ON METHODOLOGY Node Voltge Anlysis Method 1. Select reference node (usully ground). All other node voltges will e referenced to this node. 2. Define the remining n 1 node voltges s the independent vriles. 3. Apply KCL t ech of the n 1 nodes, expressing ech current in terms of the djcent node voltges. 4. Solve the liner system of n 1 equtions in n 1 unknowns. Following the procedure outlined in the ox gurntees tht the correct solution to given circuit will e found, provided tht the nodes re properly identified nd KCL is pplied consistently. As n illustrtion of the method, consider the circuit shown in Figure 3.3. The circuit is shown in two different forms to illustrte equivlent grphicl representtions of the sme circuit. The ottom circuit leves no question where the nodes re. The direction of current flow is selected ritrrily (ssuming tht i S is positive current). Appliction of KCL t node yields: Node Node i S i 1 i 2 = 0 (3.2) i S wheres, t node, i 2 i 3 = 0 (3.3) Node c It is instructive to verify (t lest the first time the method is pplied) tht it is not necessry to pply KCL t the reference node. The eqution otined t node c, i 1 i 3 i S = 0 (3.4) v v is not independent of equtions 3.2 nd 3.3; in fct, it my e otined y dding the equtions otined t nodes nd (verify this, s n exercise). This oservtion confirms the sttement mde erlier: i S i i 2 1 i S i 3 In circuit contining n nodes, we cn write t most n 1 independent equtions. v c = 0 Now, in pplying the node voltge method, the currents i 1, i 2, nd i 3 re expressed s functions of v, v, nd v c, the independent vriles. Ohm s lw requires tht i 1, for exmple, e given y Figure 3.3 Illustrtion of nodl nlysis i 1 = v v c (3.5) since it is the potentil difference, v v c, cross tht cuses the current i 1 to flow from node to node c. Similrly, i 2 = v v i 3 = v v c (3.6)

4 74 Chpter 3 Resistive Network Anlysis Sustituting the expression for the three currents in the nodl equtions (equtions 3.2 nd 3.3), we otin the following reltionships: i S v v v = 0 (3.7) v v v = 0 (3.8) Equtions 3.7 nd 3.8 my e otined directly from the circuit, with little prctice. Note tht these equtions my e solved for v nd v, ssuming tht i S,,, nd re known. The sme equtions my e reformulted s follows: ( 1 1 ) ( 1R2 v ) v ( 1R2 ) v = i S ( 1 1 ) v = 0 The following exmples further illustrte the ppliction of the method. (3.9) EXAMPLE 3.1 Nodl Anlysis Prolem Solve for ll unknown currents nd voltges in the circuit of Figure 3.4. Solution Known Quntities: Source currents, resistor vlues. Find: All node voltges nd rnch currents. Schemtics, Digrms, Circuits, nd Given Dt: I 1 = 10 ma; I 2 = 50 ma; = 1k ; = 2k ; = 10 k ; R 4 = 2k. R 4 I 1 I 2 Assumptions: circuit. The reference (ground) node is chosen to e the node t the ottom of the Figure 3.4 Anlysis: The circuit of Figure 3.4 is shown gin in Figure 3.5, with grphicl indiction of how KCL will e pplied to determine the nodl equtions. Note tht we hve selected to ground the lower prt of the circuit, resulting in reference voltge of zero t tht node. Applying KCL t nodes 1 nd 2 we otin I 1 v 1 0 v 1 v 2 v 1 v 2 = 0 (node 1) v 1 v 2 v 1 v 2 v 2 0 I 2 = 0 (node 2) R4 Now we cn write the sme equtions more systemticlly s function of the unknown node voltges, s ws done in eqution 3.9. ( ) ) 1 v 1 ( 1R2 1R3 v 2 = I 1 (node 1) 1 1 ) ( 1R2 1R3 v 1 ( R 4 ) v 2 = I 2 (node 2)

5 Prt I Circuits 75 With some mnipultion, the equtions finlly led to the following form: 1.6v 1 0.6v 2 = v 1 1.1v 2 = 50 Node 1 These equtions my e solved simultneously to otin v 1 = V v 2 = V Knowing the node voltges, we cn determine ech of the rnch currents nd voltges in the circuit. For exmple, the current through the 10-k resistor is given y: i 10 k = v 1 v 2 = 3.93 ma 10,000 R 4 I 1 Node 2 I 2 indicting tht the initil (ritrry) choice of direction for this current ws the sme s the ctul direction of current flow. As nother exmple, consider the current through the 1-k resistor: i 1k = v 1 = ma 1,000 In this cse, the current is negtive, indicting tht current ctully flows from ground to node 1, s it should, since the voltge t node 1 is negtive with respect to ground. You my continue the rnch-y-rnch nlysis strted in this exmple to verify tht the solution otined in the exmple is indeed correct. Comments: Note tht we hve chose to ssign positive sign to currents entering node, nd negtive sign to currents exiting node; this choice is ritrry (one could use the opposite convention), ut we shll use it consistently in this ook. R 4 I 1 Figure 3.5 I 2 EXAMPLE Prolem 3.2 Nodl Anlysis Write the nodl equtions nd solve for the node voltges in the circuit of Figure 3.6. i i R 4 Solution Known Quntities: Source currents, resistor vlues. Find: All node voltges nd rnch currents. Figure 3.6 v v Schemtics, Digrms, Circuits, nd Given Dt: i = 1 ma; i = 2 ma; = 1k ; = 500 ; = 2.2 k ; R 4 = 4.7 k. Assumptions: The reference (ground) node is chosen to e the node t the ottom of the circuit. Anlysis: To write the node equtions, we strt y selecting the reference node (step 1). Figure 3.7 illustrtes tht two nodes remin fter the selection of the reference node. Let us lel these nd nd define voltges v nd v (step 2). i 2 i1 i i R 4 i 3 Figure V i 4

6 76 Chpter 3 Resistive Network Anlysis Next, we pply KCL t ech of the nodes, nd (step 3): v v i v v v = 0 (node ) i v v R 4 = 0 (node ) nd rewrite the equtions to otin liner system: ( 1 1 ) ) v ( 1R2 v = i ) ( ( 1R2 1 v 1 1 ) v = i R 4 Sustituting the numericl vlues in these equtions, we get or v v = v v = v 2v = 1 2v 2.67v = 2 The solution v = V, v = 2 V my then e otined y solving the system of equtions. EXAMPLE 3.3 Solution of Liner System of Equtions Using Crmer s Rule Prolem Solve the circuit equtions otined in Exmple 3.2 using Crmer s rule (see Appendix A). Solution Known Quntities: Liner system of equtions. Find: Node voltges. Anlysis: The system of equtions generted in Exmple 3.2 my lso e solved y using liner lger methods, y recognizing tht the system of equtions cn e written s: [ ][ ] [ ] 3 2 v 1V = V v By using Crmer s rule (see Appendix A), the solution for the two unknown vriles, v nd v, cn e written s follows: (1)(2.67) ( 2)(2) v = = 3 2 (3)(2.67) ( 2)( 2) = 6.67 = V (3)(2) ( 2)(1) v = = 3 2 (3)(2.67) ( 2)( 2) = 8 4 = 2V The result is the sme s in Exmple 3.2.

7 Prt I Circuits 77 Comments: While Crmer s rule is n efficient solution method for simple circuits (e.g., two nodes), it is customry to use computer-ided methods for lrger circuits. Once the nodl equtions hve een set in the generl form presented in eqution 3.9, vriety of computer ids my e employed to compute the solution. You will find the solution to the sme exmple computed using MthCd in the electronic files tht ccompny this ook. Nodl Anlysis with Voltge Sources It would pper from the exmples just shown tht the node voltge method is very esily pplied when current sources re present in circuit. This is, in fct, the cse, since current sources re directly ccounted for y KCL. Some confusion occsionlly rises, however, when voltge sources re present in circuit nlyzed y the node voltge method. In fct, the presence of voltge sources ctully simplifies the clcultions. To further illustrte this point, consider the circuit of Figure 3.8. Note immeditely tht one of the node voltges is known lredy! The voltge t node is forced to e equl to tht of the voltge source; tht is, v = v S. Thus, only two nodl equtions will e needed, t nodes nd c: v v v c v S v v v v c = 0 (node ) v v c i S v c R 4 = 0 (node c) (3.10) Rewriting these equtions, we otin: ( ) ) v ( 1R3 v c = v S ) ( ( 1R3 1 v 1 ) (3.11) v c = i S R 4 _ v S R 4 i S Figure 3.8 Nodl nlysis with voltge sources Note how the term v S / on the right-hnd side of the first eqution is relly current, s is dimensionlly required y the nture of the node equtions. EXAMPLE 3.4 Nodl Anlysis with Voltge Sources Prolem Find the node voltges in the circuit of Figure 3.9. Solution Known Quntities: Source current nd voltge; resistor vlues. Find: Node voltges. v Node I R2 v V _ Node Schemtics, Digrms, Circuits, nd Given dt: = 2k ; = 3k. I = 2 ma; V = 3V; = 1k ; Figure 3.9 Assumptions: Plce the reference node t the ottom of the circuit.

8 78 Chpter 3 Resistive Network Anlysis Anlysis: Apply KCL t nodes nd : I v 0 v v = 0 v v v 3 = 0 Reformulting the lst two equtions, we derive the following system: 1.5v 0.5v = 2 0.5v 0.833v = 1 Solving the lst set of equtions, we otin the following vlues: v = V nd v = 0.5 V Comments: To compute the current flowing through resistor we noted tht the voltge immeditely ove resistor (t the negtive terminl of the voltge source) must e 3 volts lower thn v ; thus, the current through is equl to (v 3)/. Check Your Understnding 3.1 Find the current i L in the circuit shown on the left, using the node voltge method. 100 Ω 1 A 50 Ω 50 Ω 75 Ω i L 10 Ω v x 30 Ω 10 V 2 A 20 Ω 20 Ω 3.2 Find the voltge v x y the node voltge method for the circuit shown on the right. 3.3 Show tht the nswer to Exmple 3.2 is correct y pplying KCL t one or more nodes. The current i, defined s flowing from left to right, estlishes the polrity of the voltge cross R. v R i R Figure 3.10 Bsic principle of mesh nlysis 3.2 THE MESH CURRENT METHOD The second method of circuit nlysis discussed in this chpter, which is in mny respects nlogous to the method of node voltges, employs mesh currents s the independent vriles. The ide is to write the pproprite numer of independent equtions, using mesh currents s the independent vriles. Anlysis y mesh currents consists of defining the currents round the individul meshes s the independent vriles. Susequent ppliction of Kirchhoff s voltge lw round ech mesh provides the desired system of equtions. In the mesh current method, we oserve tht current flowing through resistor in specified direction defines the polrity of the voltge cross the resistor, s illustrted in Figure 3.10, nd tht the sum of the voltges round closed circuit

9 Prt I Circuits 79 must equl zero, y KVL. Once convention is estlished regrding the direction of current flow round mesh, simple ppliction of KVL provides the desired eqution. Figure 3.11 illustrtes this point. The numer of equtions one otins y this technique is equl to the numer of meshes in the circuit. All rnch currents nd voltges my susequently e otined from the mesh currents, s will presently e shown. Since meshes re esily identified in circuit, this method provides very efficient nd systemtic procedure for the nlysis of electricl circuits. The following ox outlines the procedure used in pplying the mesh current method to liner circuit. Once the direction of current flow hs een selected, KVL requires tht v 1 v 2 v 3 = 0. v 2 v 1 i v 3 A mesh FOCUS ON METHODOLOGY Mesh Current Anlysis Method 1. Define ech mesh current consistently. We shll lwys define mesh currents clockwise, for convenience. 2. Apply KVL round ech mesh, expressing ech voltge in terms of one or more mesh currents. 3. Solve the resulting liner system of equtions with mesh currents s the independent vriles. Figure 3.11 Use of KVL in mesh nlysis In mesh nlysis, it is importnt to e consistent in choosing the direction of current flow. To void confusion in writing the circuit equtions, mesh currents will e defined exclusively clockwise when we re using this method. To illustrte the mesh current method, consider the simple two-mesh circuit shown in Figure This circuit will e used to generte two equtions in the two unknowns, the mesh currents i 1 nd i 2. It is instructive to first consider ech mesh y itself. Beginning with mesh 1, note tht the voltges round the mesh hve een ssigned in Figure 3.13 ccording to the direction of the mesh current, i 1. Recll tht s long s signs re ssigned consistently, n ritrry direction my e ssumed for ny current in circuit; if the resulting numericl nswer for the current is negtive, then the chosen reference direction is opposite to the direction of ctul current flow. Thus, one need not e concerned out the ctul direction of current flow in mesh nlysis, once the directions of the mesh currents hve een ssigned. The correct solution will result, eventully. According to the sign convention, then, the voltges v 1 nd v 2 re defined s shown in Figure Now, it is importnt to oserve tht while mesh current i 1 is equl to the current flowing through resistor (nd is therefore lso the rnch current through ), it is not equl to the current through. The rnch current through is the difference etween the two mesh currents, i 1 i 2. Thus, since the polrity of the voltge v 2 hs lredy een ssigned, ccording to the convention discussed in the previous prgrph, it follows tht the voltge v 2 is given y: v 2 = (i 1 i 2 ) (3.12) Finlly, the complete expression for mesh 1 is v S i 1 (i 1 i 2 ) = 0 (3.13) v S _ i 1 i 2 Figure 3.12 A two-mesh circuit Mesh 1: KVL requires tht v S v 1 v 2 = 0, where v 1 = i 1, v 2 = (i 1 i 2 ). v S v 1 _ i 1 v 2 i 2 R 4 R 4 Figure 3.13 Assignment of currents nd voltges round mesh 1

10 80 Chpter 3 Resistive Network Anlysis Mesh 2: KVL requires tht where v S v 2 v 3 v 4 = 0 v 2 = (i 2 i 1 ), v 3 = i 2, v 4 = i 2 R 4 v 3 _ i 1 v 2 i 2 R 4 v 4 Figure 3.14 Assignment of currents nd voltges round mesh 2 The sme line of resoning pplies to the second mesh. Figure 3.14 depicts the voltge ssignment round the second mesh, following the clockwise direction of mesh current i 2. The mesh current i 2 is lso the rnch current through resistors nd R 4 ; however, the current through the resistor tht is shred y the two meshes,, is now equl to (i 2 i 1 ), nd the voltge cross this resistor is v 2 = (i 2 i 1 ) (3.14) nd the complete expression for mesh 2 is (i 2 i 1 ) i 2 i 2 R 4 = 0 (3.15) Why is the expression for v 2 otined in eqution 3.14 different from eqution 3.12? The reson for this pprent discrepncy is tht the voltge ssignment for ech mesh ws dictted y the (clockwise) mesh current. Thus, since the mesh currents flow through in opposing directions, the voltge ssignments for v 2 in the two meshes will lso e opposite. This is perhps potentil source of confusion in pplying the mesh current method; you should e very creful to crry out the ssignment of the voltges round ech mesh seprtely. Comining the equtions for the two meshes, we otin the following system of equtions: ( )i 1 i 2 = v S i 1 ( R 4 )i 2 = 0 (3.16) These equtions my e solved simultneously to otin the desired solution, nmely, the mesh currents, i 1 nd i 2. You should verify tht knowledge of the mesh currents permits determintion of ll the other voltges nd currents in the circuit. The following exmples further illustrte some of the detils of this method. EXAMPLE 3.5 Mesh Anlysis Prolem Find the mesh currents in the circuit of Figure Solution Known Quntities: Source voltges; resistor vlues. V 1 V2 _ V 3 R 4 Find: Mesh currents. Schemtics, Digrms, Circuits, nd Given Dt: V 1 = 10 V; V 2 = 9V;V 3 = 1V; = 5 ; = 10 ; = 5 ; R 4 = 5. Figure 3.15 Assumptions: Assume clockwise mesh currents i 1 nd i 2. Anlysis: The circuit of Figure 3.15 will yield two equtions in two unknowns, i 1 nd i 2. It is instructive to consider ech mesh seprtely in writing the mesh equtions; to this end, Figure 3.16 depicts the pproprite voltge ssignments round the two meshes,

11 Prt I Circuits 81 sed on the ssumed directions of the mesh currents. From Figure 3.16, we write the mesh equtions: V 1 i 1 V 2 (i 1 i 2 ) = 0 (i 2 i 1 ) V 2 i 2 V 3 R 4 i 2 = 0 Rerrnging the liner system of the eqution, we otin 15i 1 10i 2 = 1 10i 1 20i 2 = 8 which cn e solved to otin i 1 nd i 2 : i 1 = 0.5 A nd i 2 = 0.65 A Comments: Note how the voltge v 2 cross resistor hs different polrity in Figure 3.16, depending on whether we re working in mesh 1 or mesh 2. V 1 V 1 v 1 _ V2 _ V 3 _ i 1 i 2 v 2 R 4 Anlysis of mesh 1 v 3 _ V2 _ V 3 _ i 1 i 2 v 2 v 4 R 4 Figure 3.16 Anlysis of mesh 2 EXAMPLE 3.6 Mesh Anlysis Prolem Write the mesh current equtions for the circuit of Figure R 4 i 3 Solution Known Quntities: Source voltges; resistor vlues. Find: Mesh current equtions. _ V 1 i 1 i 2 V 2 _ Schemtics, Digrms, Circuits, nd Given Dt: V 1 = 12 V; V 2 = 6V; = 3 ; = 8 ; = 6 ; R 4 = 4. Assumptions: Assume clockwise mesh currents i 1, i 2, nd i 3. Figure 3.17 Anlysis: Strting from mesh 1 we pply KVL to otin V 1 (i 1 i 3 ) (i 1 i 2 ) = 0. KVL pplied to mesh 2 yields (i 2 i 1 ) (i 2 i 3 ) V 2 = 0 while in mesh 3 we find (i 3 i 1 ) R 4 i 3 (i 3 i 2 ) = 0. These equtions cn e rerrnged in stndrd form to otin (3 8)i 1 8i 2 3i 3 = 12 8i 1 (6 8)i 2 6i 3 = 6 3i 1 6i 2 (3 6 4)i 3 = 0 You my verify tht KVL holds round ny one of the meshes, s test to check tht the nswer is indeed correct.

12 82 Chpter 3 Resistive Network Anlysis Comments: The solution of the mesh current equtions with computer-ided tools (MthCd) my e found in the electronic files tht ccompny this ook. A comprison of this result with the nlogous result otined y the node voltge method revels tht we re using Ohm s lw in conjunction with KVL (in contrst with the use of KCL in the node voltge method) to determine the minimum set of equtions required to solve the circuit. 5 Ω 2 Ω 10 V 2 A _ i v x 1 i2 4 Ω Figure 3.18 Mesh nlysis with current sources Mesh Anlysis with Current Sources Mesh nlysis is prticulrly effective when pplied to circuits contining voltge sources exclusively; however, it my e pplied to mixed circuits, contining oth voltge nd current sources, if cre is tken in identifying the proper current in ech mesh. The method is illustrted y solving the circuit shown in Figure The first oservtion in nlyzing this circuit is tht the presence of the current source requires tht the following reltionship hold true: i 1 i 2 = 2A (3.17) If the unknown voltge cross the current source is leled v x, ppliction of KVL round mesh 1 yields: 10 5i 1 v x = 0 (3.18) while KVL round mesh 2 dicttes tht v x 2i 2 4i 2 = 0 (3.19) Sustituting eqution 3.19 in eqution 3.18, nd using eqution 3.17, we cn then otin the system of equtions 5i 1 6i 2 = 10 i 1 i 2 = 2 which we cn solve to otin i 1 = 2A i 2 = 0A (3.20) (3.21) Note lso tht the voltge cross the current source my e found y using either eqution 3.18 or eqution 3.19; for exmple, using eqution 3.19, v x = 6i 2 = 0V (3.22) The following exmple further illustrtes the solution of this type of circuit. EXAMPLE 3.7 Mesh Anlysis with Current Sources Prolem Find the mesh currents in the circuit of Figure 3.19.

13 Prt I Circuits 83 R 4 Solution Known Quntities: Source current nd voltge; resistor vlues. i 3 Find: Mesh currents. Schemtics, Digrms, Circuits, nd Given Dt: = 8 ; = 6 ; R 4 = 4. I = 0.5 A;V = 6V; = 3 ; I i 1 i 2 V _ Assumptions: Assume clockwise mesh currents i 1, i 2, nd i 3. Anlysis: Strting from mesh 1, we see immeditely tht the current source forces the mesh current to e equl to I: Figure 3.19 i 1 = I There is no need to write ny further equtions round mesh 1, since we lredy know the vlue of the mesh current. Now we turn to meshes 2 nd 3 to otin: (i 2 i 1 ) (i 2 i 3 ) V = 0 mesh 2 (i 3 i 1 ) R 4 i 3 (i 3 i 2 ) = 0 mesh 3 Rerrnging the equtions nd sustituting the known vlue of i 1, we otin system of two equtions in two unknowns: 14i 2 6i 3 = 10 6i 2 13i 3 = 1.5 which cn e solved to otin i 2 = 0.95 A i 3 = 0.55 A As usul, you should verify tht the solution is correct y pplying KVL. Comments: Note tht the current source hs ctully simplified the prolem y constrining mesh current to fixed vlue. Check Your Understnding 3.4 Find the unknown voltge, v x, y mesh current nlysis in the circuit of Figure Ω 12 Ω 3 Ω 60 Ω 5 Ω 15 V _ 6 Ω v x 24 V _ 6 Ω I x _ 15 V Figure 3.20 Figure Find the unknown current, I x, using mesh current methods in the circuit of Figure 3.21.

14 84 Chpter 3 Resistive Network Anlysis 3.6 Show tht the equtions given in Exmple 3.6 re correct, y pplying KCL t ech node. 3.3 NODAL AND MESH ANALYSIS WITH CONTROLLED SOURCES The methods just descried lso pply, with reltively minor modifictions, in the presence of dependent (controlled) sources. Solution methods tht llow for the presence of controlled sources will e prticulrly useful in the study of trnsistor mplifiers in Chpter 8. Recll from the discussion in Section 2.3 tht dependent source is source tht genertes voltge or current tht depends on the vlue of nother voltge or current in the circuit. When dependent source is present in circuit to e nlyzed y node or mesh nlysis, one cn initilly tret it s n idel source nd write the node or mesh equtions ccordingly. In ddition to the eqution otined in this fshion, there will lso e n eqution relting the dependent source to one of the circuit voltges or currents. This constrint eqution cn then e sustituted in the set of equtions otined y the techniques of nodl nd mesh nlysis, nd the equtions cn susequently e solved for the unknowns. It is importnt to remrk tht once the constrint eqution hs een sustituted in the initil system of equtions, the numer of unknowns remins unchnged. Consider, for exmple, the circuit of Figure 3.22, which is simplified model of ipolr trnsistor mplifier (trnsistors will e introduced in Chpter 8). In the circuit of Figure 3.22, two nodes re esily recognized, nd therefore nodl nlysis is chosen s the preferred method. Applying KCL t node 1, we otin the following eqution: i S = v 1 ( 1 R S 1 R ) (3.23) KCL pplied t the second node yields: βi v 2 R C = 0 (3.24) Next, it should e oserved tht the current i cn e determined y mens of simple current divider: 1/R R S i = i S = i S (3.25) 1/R 1/R S R R S Node 1 Node 2 i i S R S R βi R C V O Figure 3.22 Circuit with dependent source

15 Prt I Circuits 85 which, when inserted in eqution 3.24, yields system of two equtions: ( 1 i S = v 1 1 ) R S R R S βi S = v (3.26) 2 R R S R C which cn e used to solve for v 1 nd v 2. Note tht, in this prticulr cse, the two equtions re independent of ech other. The following exmple illustrtes cse in which the resulting equtions re not independent. EXAMPLE 3.8 Anlysis with Dependent Sources Prolem Find the node voltges in the circuit of Figure Solution Known Quntities: Source current; resistor vlues; dependent voltge source reltionship. Find: Unknown node voltge v. Schemtics, Digrms, Circuits, nd Given Dt: I = 0.5 A; = 5 ; = 2 ; = 4. Dependent source reltionship: v x = 2 v 3. Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: Applying KCL to node v we find tht v x v I v v 3 = 0 Applying KCL to node v 3 we find v v 3 v 3 = 0 If we sustitute the dependent source reltionship into the first eqution, we otin system of equtions in the two unknowns v nd v 3 : ( 1 1 ) ) v ( 2R1 1R2 v 3 = I ) ( ( 1R2 1 v 1 ) v 3 = 0 Sustituting numericl vlues, we otin: 0.7v 0.9v 3 = v 0.75v 3 = 0 Solution of the ove equtions yields v = 5V;v 3 = 3.33 V. Comments: You will find the solution to the sme exmple computed using MthCd in the electronic files tht ccompny this ook. v v x _ I v 3 Figure 3.23

16 86 Chpter 3 Resistive Network Anlysis Remrks on Node Voltge nd Mesh Current Methods The techniques presented in this section nd the two preceding sections find use more generlly thn just in the nlysis of resistive circuits. These methods should e viewed s generl techniques for the nlysis of ny liner circuit; they provide systemtic nd effective mens of otining the minimum numer of equtions necessry to solve network prolem. Since these methods re sed on the fundmentl lws of circuit nlysis, KVL nd KCL, they lso pply to ny electricl circuit, even circuits contining nonliner circuit elements, such s those to e introduced lter in this chpter. You should mster oth methods s erly s possile. Proficiency in these circuit nlysis techniques will gretly simplify the lerning process for more dvnced concepts. Check Your Understnding 3.7 The current source i x is relted to the voltge v x in Figure 3.24 y the reltion i x = v x 3 Find the voltge cross the 8- resistor y nodl nlysis. v x 12 Ω 3 Ω i x 8 Ω 6 Ω _ 6 Ω 6 Ω 15 V _ v x i 12 6 Ω i x 15 V _ Figure 3.24 Figure Find the unknown current i x in Figure 3.25 using the mesh current method. The dependent voltge source is relted to the current i 12 through the 12- resistor y v x = 2i THE PRINCIPLE OF SUPERPOSITION This rief section discusses concept tht is frequently clled upon in the nlysis of liner circuits. Rther thn precise nlysis technique, like the mesh current nd node voltge methods, the principle of superposition is conceptul id tht cn e very useful in visulizing the ehvior of circuit contining multiple sources. The principle of superposition pplies to ny liner system nd for liner circuit my e stted s follows: In liner circuit contining N sources, ech rnch voltge nd current is the sum of N voltges nd currents ech of which my e computed y setting ll ut one source equl to zero nd solving the circuit contining tht single source.

17 Prt I Circuits 87 An elementry illustrtion of the concept my esily e otined y simply considering circuit with two sources connected in series, s shown in Figure v B2 v B1 i v B2 _ R = R he net current through v B1 i _ B1 i B2 R is the sum of the individul source currents: i = i B1 i B2. Figure 3.26 The principle of superposition The circuit of Figure 3.26 is more formlly nlyzed s follows. The current, i, flowing in the circuit on the left-hnd side of Figure 3.26 my e expressed s: i = v B1 v B2 R = v B1 R v B2 R = i B1 i B2 (3.27) Figure 3.26 lso depicts the circuit s eing equivlent to the comined effects of two circuits, ech contining single source. In ech of the two sucircuits, short circuit hs een sustituted for the missing ttery. This should pper s sensile procedure, since short circuit y definition will lwys see zero voltge cross itself, nd therefore this procedure is equivlent to zeroing the output of one of the voltge sources. If, on the other hnd, one wished to cncel the effects of current source, it would stnd to reson tht n open circuit could e sustituted for the current source, since n open circuit is y definition circuit element through which no current cn flow (nd which will therefore generte zero current). These sic principles re used frequently in the nlysis of circuits, nd re summrized in Figure The principle of superposition cn esily e pplied to circuits contining multiple sources nd is sometimes n effective solution technique. More often, 1. In order to set voltge source equl to zero, we replce it with short circuit. v S _ i S i S A circuit The sme circuit with v S = 0 2. In order to set current source equl to zero, we replce it with n open circuit. _ v S i S v S _ A circuit The sme circuit with i S = 0 Figure 3.27 Zeroing voltge nd current sources

18 88 Chpter 3 Resistive Network Anlysis however, other methods result in more efficient solution. Exmple 3.9 further illustrtes the use of superposition to nlyze simple network. The Check Your Understnding exercises t the end of the section illustrte the fct tht superposition is often cumersome solution method. EXAMPLE 3.9 Principle of Superposition Prolem Determine the current i 2 in the circuit of Figure 3.18 using the principle of superposition. Solution Known Quntities: Source voltge nd current vlues. Resistor vlues. Find: Unknown current i 2. Given Dt Figure Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: Prt 1: Zero the current source. Once the current source hs een set to zero (replced y n open circuit), the resulting circuit is simple series circuit; the current flowing in this circuit, i 2 V, is the current we seek. Since the totl series resistnce is = 11, wefind tht i 2 V = 10/11 = A. Prt 2: Zero the voltge source. After zeroing of the voltge source y replcing it with short circuit, the resulting circuit consists of three prllel rnches: On the left we hve single 5- resistor; in the center we hve 2-A current source (negtive ecuse the source current is shown to flow into the ground node); on the right we hve totl resistnce of 2 4 = 6. Using the current divider rule, we find tht the current flowing in the right rnch, i 2 I, is given y: 1 i 2 I = ( 2) = A 6 And, finlly, the unknown current i 2 is found to e i 2 = i 2-V i 2 I = 0A. The result is, of course, identicl to tht otined y mesh nlysis. Comments: Superposition my pper to e very efficient tool. However, eginners my find it preferle to rely on more systemtic methods, such s nodl nlysis, to solve circuits. Eventully, experience will suggest the preferred method for ny given circuit. Check Your Understnding 3.9 Find the voltges v nd v for the circuits of Exmple 3.4 y superposition Repet Check Your Understnding Exercise 3.2, using superposition. This exercise illustrtes tht superposition is not necessrily computtionlly efficient solution method.

19 Prt I Circuits Solve Exmple 3.5, using superposition Solve Exmple 3.7, using superposition. 3.5 ONE-PORT NETWORKS AND EQUIVALENT CIRCUITS You my recll tht, in the discussion of idel sources in Chpter 2, the flow of energy from source to lod ws descried in very generl form, y showing the connection of two lck oxes leled source nd lod (see Figure 2.10). In the sme figure, two other descriptions were shown: symolic one, depicting n idel voltge source nd n idel resistor; nd physicl representtion, in which the lod ws represented y hedlight nd the source y n utomotive ttery. Whtever the form chosen for source-lod representtion, ech lock source or lod my e viewed s two-terminl device, descried y n i-v chrcteristic. This generl circuit representtion is shown in Figure This configurtion is clled one-port network nd is prticulrly useful for introducing the notion of equivlent circuits. Note tht the network of Figure 3.28 is completely descried y its i-v chrcteristic; this point is est illustrted y the next exmple. v i Liner network Figure 3.28 One-port network EXAMPLE 3.10 Equivlent Resistnce Clcultion Prolem Determine the source (lod) current i in the circuit of Figure 3.29 using equivlent resistnce ides. i v S _ v Source Lod Figure 3.29 Illustrtion of equivlent-circuit concept Lod circuit Solution Known Quntities: Source voltge, resistor vlues. R EQ Find: Source current. Given Dt: Figures 3.29, Assumptions: Assume reference node is t the ottom of the circuit. Equivlent lod circuit Figure 3.30 Equivlent lod resistnce concept

20 90 Chpter 3 Resistive Network Anlysis Anlysis: Insofr s the source is concerned, the three prllel resistors pper identicl to single equivlent resistnce of vlue 1 R EQ = Thus, we cn replce the three lod resistors with the single equivlent resistor R EQ,s shown in Figure 3.30, nd clculte i = v S R EQ Comments: Similrly, insofr s the lod is concerned, it would not mtter whether the source consisted, sy, of single 6-V ttery or of four 1.5-V tteries connected in series. For the reminder of this chpter, we shll focus on developing techniques for computing equivlent representtions of liner networks. Such representtions will e useful in deriving some simple yet generl results for liner circuits, s well s nlyzing simple nonliner circuits. Thévenin nd Norton Equivlent Circuits This section discusses one of the most importnt topics in the nlysis of electricl circuits: the concept of n equivlent circuit. It will e shown tht it is lwys possile to view even very complicted circuit in terms of much simpler equivlent source nd lod circuits, nd tht the trnsformtions leding to equivlent circuits re esily mnged, with little prctice. In studying node voltge nd mesh current nlysis, you my hve oserved tht there is certin correspondence (clled dulity) etween current sources nd voltge sources, on the one hnd, nd prllel nd series circuits, on the other. This dulity ppers gin very clerly in the nlysis of equivlent circuits: it will shortly e shown tht equivlent circuits fll into one of two clsses, involving either voltge or current sources nd (respectively) either series or prllel resistors, reflecting this sme principle of dulity. The discussion of equivlent circuits egins with the sttement of two very importnt theorems, summrized in Figures 3.31 nd i i Source v Lod v T _ v Lod Figure 3.31 Illustrtion of Thévenin theorem i i Source v Lod i N R N v Lod Figure 3.32 Illustrtion of Norton theorem

21 Prt I Circuits 91 The Thévenin Theorem As fr s lod is concerned, ny network composed of idel voltge nd current sources, nd of liner resistors, my e represented y n equivlent circuit consisting of n idel voltge source, v T, in series with n equivlent resistnce,. The Norton Theorem As fr s lod is concerned, ny network composed of idel voltge nd current sources, nd of liner resistors, my e represented y n equivlent circuit consisting of n idel current source, i N, in prllel with n equivlent resistnce, R N. The first ovious question to rise is, how re these equivlent source voltges, currents, nd resistnces computed? The next few sections illustrte the computtion of these equivlent circuit prmeters, mostly through exmples. A sustntil numer of Check Your Understnding exercises re lso provided, with the following cution: The only wy to mster the computtion of Thévenin nd Norton equivlent circuits is y ptient repetition. Determintion of Norton or Thévenin Equivlent Resistnce The first step in computing Thévenin or Norton equivlent circuit consists of finding the equivlent resistnce presented y the circuit t its terminls. This is done y setting ll sources in the circuit equl to zero nd computing the effective resistnce etween terminls. The voltge nd current sources present in the circuit re set to zero y the sme technique used with the principle of superposition: voltge sources re replced y short circuits, current sources y open circuits. To illustrte the procedure, consider the simple circuit of Figure 3.33; the ojective is to compute the equivlent resistnce the lod R L sees t port -. In order to compute the equivlent resistnce, we remove the lod resistnce from the circuit nd replce the voltge source, v S, y short circuit. At this point seen from the lod terminls the circuit ppers s shown in Figure You cn see tht nd re in prllel, since they re connected etween the sme two nodes. If the totl resistnce etween terminls nd is denoted y, its vlue cn e determined s follows: v S _ Complete circuit R L = (3.28) v S An lterntive wy of viewing is depicted in Figure 3.35, where hypotheticl 1-A current source hs een connected to the terminls nd. The voltge v x ppering cross the - pir will then e numericlly equl to (only ecuse i S = 1 A!). With the 1-A source current flowing in the circuit, it should e pprent tht the source current encounters s resistor in series with the prllel comintion of nd, prior to completing the loop. Circuit with lod removed for computtion of. The voltge source is replced y short circuit. Figure 3.33 Computtion of Thévenin resistnce

22 92 Chpter 3 Resistive Network Anlysis Wht is the totl resistnce the current i S will encounter in flowing round the circuit? v x i S Figure 3.34 Equivlent resistnce seen y the lod i S i S = Figure 3.35 An lterntive method of determining the Thévenin resistnce Summrizing the procedure, we cn produce set of simple rules s n id in the computtion of the Thévenin (or Norton) equivlent resistnce for liner resistive circuit: FOCUS ON METHODOLOGY Computtion of Equivlent Resistnce of One-Port Network 1. Remove the lod. 2. Zero ll independent voltge nd current sources. 3. Compute the totl resistnce etween lod terminls, with the lod removed. This resistnce is equivlent to tht which would e encountered y current source connected to the circuit in plce of the lod. We note immeditely tht this procedure yields result tht is independent of the lod. This is very desirle feture, since once the equivlent resistnce hs een identified for source circuit, the equivlent circuit remins unchnged if we connect different lod. The following exmples further illustrte the procedure. EXAMPLE 3.11 Thévenin Equivlent Resistnce Prolem Find the Thévenin equivlent resistnce seen y the lod R L in the circuit of Figure Solution Known Quntities: Resistor nd current source vlues.

23 Prt I Circuits 93 R 5 I R 4 R L Figure 3.36 Find: Thévenin equivlent resistnce. Schemtics, Digrms, Circuits, nd Given Dt: = 20 ; = 20 ; I = 5A; = 10 ; R 4 = 20 ; R 5 = 10. Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: Following the methodology ox introduced in the present section, we first set the current source equl to zero, y replcing it with n open circuit. The resulting circuit is depicted in Figure Looking into terminl - we recognize tht, strting from the left (wy from the lod) nd moving to the right (towrd the lod) the equivlent resistnce is given y the expression = [(( ) ) R 4 ] R 5 R 5 R 4 = [((20 20) 10) 20] 10 = 20 Figure 3.37 Comments: the lod. Note tht the reduction of the circuit strted t the frthest point wy from EXAMPLE 3.12 Thévenin Equivlent Resistnce Prolem Compute the Thévenin equivlent resistnce seen y the lod in the circuit of Figure V _ I R 4 R L Figure 3.38 Solution Known Quntities: Resistor vlues. Find: Thévenin equivlent resistnce.

24 94 Chpter 3 Resistive Network Anlysis Schemtics, Digrms, Circuits, nd Given Dt: = 1 ; I = 1A,R 4 = 2. V = 5V; = 2 ; = 2 ; Assumptions: Assume reference node is t the ottom of the circuit. R 4 Anlysis: Following the Thévenin equivlent resistnce methodology ox, we first set the current source equl to zero, y replcing it with n open circuit, then set the voltge source equl to zero y replcing it with short circuit. The resulting circuit is depicted in Figure Looking into terminl - we recognize tht, strting from the left (wy from the lod) nd moving to the right (towrd the lod), the equivlent resistnce is given y the expression = (( ) ) R 4 = ((2 2) 1) 2 = 1 Figure 3.39 Comments: the lod. Note tht the reduction of the circuit strted t the frthest point wy from As finl note, it should e remrked tht the Thévenin nd Norton equivlent resistnces re one nd the sme quntity: = R N (3.29) Therefore, the preceding discussion holds whether we wish to compute Norton orthévenin equivlent circuit. From here on we shll use the nottion exclusively, for oth Thévenin nd Norton equivlents. Check Your Understnding Exercise 3.13 will give you n opportunity to explin why the two equivlent resistnces re one nd the sme. Check Your Understnding 3.13 Apply the methods descried in this section to show tht = R N in the circuits of Figure kω _ V T R L I N R N R L 3 kω 2 kω 5 kω 5 V _ 5 kω R L Figure 3.40 Figure Find the Thévenin equivlent resistnce of the circuit of Figure 3.41 seen y the lod resistor, R L Find the Thévenin equivlent resistnce seen y the lod resistor, R L, in the circuit of Figure For the circuit of Figure 3.43, find the Thévenin equivlent resistnce seen y the lod resistor, R L.

25 Prt I Circuits 95 2 Ω 6 Ω 2 Ω 5 Ω 0.5 A 4 Ω 10 V 10 Ω _ 3 Ω R L Figure kω 6 kω 2 kω 1 MΩ 2 kω 20 V _ 6 kω 3 kω R L Figure For the circuit of Figure 3.44, find the Thévenin equivlent resistnce seen y the lod resistor, R L. 10 Ω 1 Ω 12 V _ 10 Ω 20 Ω R L Figure 3.44 Computing the Thévenin Voltge This section descries the computtion of the Thévenin equivlent voltge, v T, for n ritrry liner resistive circuit. The Thévenin equivlent voltge is defined s follows: One-port network v OC The equivlent (Thévenin) source voltge is equl to the open-circuit voltge present t the lod terminls (with the lod removed). v T _ i = 0 v OC = v T This sttes tht in order to compute v T,itissufficient to remove the lod nd to compute the open-circuit voltge t the one-port terminls. Figure 3.45 illustrtes tht the open-circuit voltge, v OC, nd the Thévenin voltge, v T, must Figure 3.45 Equivlence of open-circuit nd Thévenin voltge

26 96 Chpter 3 Resistive Network Anlysis e the sme if the Thévenin theorem is to hold. This is true ecuse in the circuit consisting of v T nd, the voltge v OC must equl v T, since no current flows through nd therefore the voltge cross is zero. Kirchhoff s voltge lw confirms tht v T = (0) v OC = v OC (3.30) FOCUS ON METHODOLOGY Computing the Thévenin Voltge 1. Remove the lod, leving the lod terminls open-circuited. 2. Define the open-circuit voltge v OC cross the open lod terminls 3. Apply ny preferred method (e.g., nodl nlysis) to solve for v OC. 4. The Thévenin voltge is v T = v OC. v S _ Figure 3.46 i L R L The ctul computtion of the open-circuit voltge is est illustrted y exmples; there is no sustitute for prctice in ecoming fmilir with these computtions. To summrize the min points in the computtion of open-circuit voltges, consider the circuit of Figure 3.33, shown gin in Figure 3.46 for convenience. Recll tht the equivlent resistnce of this circuit ws given y =. To compute v OC, we disconnect the lod, s shown in Figure 3.47, nd immeditely oserve tht no current flows through, since there is no closed circuit connection t tht rnch. Therefore, v OC must e equl to the voltge cross, s illustrted in Figure Since the only closed circuit is the mesh consisting of v S,, nd, the nswer we re seeking my e otined y mens of simple voltge divider: v S _ v OC Figure V v OC = v R2 = v S It is instructive to review the sic concepts outlined in the exmple y considering the originl circuit nd its Thévenin equivlent side y side, s shown in Figure The two circuits of Figure 3.49 re equivlent in the sense tht the current drwn y the lod, i L, is the sme in oth circuits, tht current eing given y: i L = v S 1 ( ) R L = v T R L (3.31) v S _ v OC v OC i Figure 3.48 v S _ i L R L v S i L _ R L A circuit Its Thévenin equivlent Figure 3.49 A circuit nd its Thévenin equivlent

27 Prt I Circuits 97 The computtion of Thévenin equivlent circuits is further illustrted in the following exmples. EXAMPLE 3.13 Thévenin Equivlent Voltge (Open-Circuit Lod Voltge) Prolem Compute the open-circuit voltge, v OC, in the circuit of Figure Solution Known Quntities: Source voltge, resistor vlues. Find: Open-circuit voltge, v OC. Schemtics, Digrms, Circuits, nd Given Dt: V = 12 V; = 1 ; = 10 ; = 20. V v 10 Ω _ Figure 3.50 v OC v v Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: Following the Thévenin voltge methodology ox, we first remove the lod nd lel the open-circuit voltge, v OC. Next, we oserve tht, since v is equl to the reference voltge, (i.e., zero), the node voltge v will e equl, numericlly, to the open-circuit voltge. If we define the other node voltge to e v, nodl nlysis will e the nturl technique for rriving t the solution. Figure 3.50 depicts the originl circuit redy for nodl nlysis. Applying KCL t the two nodes, we otin the following two equtions: 12 v 1 v 10 v v 10 = 0 v v v = 0 In mtrix form we cn write: [ ][ ] [ v 12 = v ] Solving the ove mtrix equtions yields: v = V; v = V. Comments: Note tht the determintion of the Thévenin voltge is nothing more thn the creful ppliction of the sic circuit nlysis methods presented in erlier sections. The only difference is tht we first need to properly identify nd define the open-circuit lod voltge. You will find the solution to the sme exmple computed y MthCd in the electronic files tht ccompny this ook. EXAMPLE 3.14 Lod Current Clcultion y Thévenin Equivlent Method Prolem Compute the lod current, i, y the Thévenin equivlent method in the circuit of Figure 3.51.

28 98 Chpter 3 Resistive Network Anlysis I _ V i Solution Known Quntities: Source voltge, resistor vlues. Find: Lod current, i. Schemtics, Digrms, Circuits, nd Given Dt: V = 24 V; I = 3A; = 4 ; = 12 ; = 6. Figure 3.51 Assumptions: Assume reference node is t the ottom of the circuit. Figure 3.52 Anlysis: We first compute the Thévenin equivlent resistnce. According to the method proposed erlier, we zero the two sources y shorting the voltge source nd opening the current source. The resulting circuit is shown in Figure We cn clerly see tht = = 4 12 = 3. Following the Thévenin voltge methodology ox, we first remove the lod nd lel the open-circuit voltge, v OC. The circuit is shown in Figure Next, we oserve tht, since v is equl to the reference voltge (i.e., zero) the node voltge v will e equl, numericlly, to the open-circuit voltge. In this circuit, single nodl eqution is required to rrive t the solution: V v I v = 0 Sustituting numericl vlues, we find tht v = v OC = v T = 27 V. V I _ v v OC 27 V 3 Ω _ 6 Ω i v Figure 3.53 Figure 3.54 Thévenin equivlent Finlly, we ssemle the Thévenin equivlent circuit, shown in Figure 3.54, nd reconnect the lod resistor. Now the lod current cn e esily computed to e: i = v T = 27 R L 3 6 = 3 A Comments: It my pper tht the clcultion of lod current y the Thévenin equivlent method leds to more complex clcultions thn, sy, node voltge nlysis (you might wish to try solving the sme circuit y nodl nlysis to verify this). However, there is one mjor dvntge to equivlent circuit nlysis: Should the lod chnge (s is often the cse in mny prcticl engineering situtions), the equivlent circuit clcultions still hold, nd only the (trivil) lst step in the ove exmple needs to e repeted. Thus, knowing the Thévenin equivlent of prticulr circuit cn e very useful whenever we need to perform computtions pertining to ny lod quntity. Check Your Understnding 3.18 With reference to Figure 3.46, find the lod current, i L, y mesh nlysis, if v S = 10 V, = = 50, = 100, R L = 150.

29 Prt I Circuits Find the Thévenin equivlent circuit seen y the lod resistor, R L, for the circuit of Figure Find the Thévenin equivlent circuit for the circuit of Figure Ω 20 Ω 2.4 Ω 60 Ω 0.5 A 10 Ω R L V _ 40 Ω A A 20 Ω 10 Ω R L 2 4 _ 15 V 0.25 A 30 Ω Figure 3.56 Figure 3.55 Computing the Norton Current The computtion of the Norton equivlent current is very similr in concept to tht of the Thévenin voltge. The following definition will serve s strting point: Definition The Norton equivlent current is equl to the short-circuit current tht would flow were the lod replced y short circuit. An explntion for the definition of the Norton current is esily found y considering, gin, n ritrry one-port network, s shown in Figure 3.57, where the one-port network is shown together with its Norton equivlent circuit. It should e cler tht the current, i SC, flowing through the short circuit replcing the lod is exctly the Norton current, i N, since ll of the source current in the circuit of Figure 3.57 must flow through the short circuit. Consider the circuit of Figure 3.58, shown with short circuit in plce of the lod resistnce. Any of the techniques presented in this chpter could e employed to determine the current i SC. In this prticulr cse, mesh nlysis is convenient tool, once it is recognized tht the short-circuit current is mesh current. Let i 1 nd i 2 = i SC e the mesh currents in the circuit of Figure Then, the following mesh equtions cn e derived nd solved for the short-circuit current: ( )i 1 i SC = v S i 1 ( )i SC = 0 An lterntive formultion would employ nodl nlysis to derive the eqution v S v = v v leding to v = v S i N One-port network = R N i SC Figure 3.57 Illustrtion of Norton equivlent circuit v S _ i 1 i 2 i SC Short circuit replcing the lod v i SC Figure 3.58 Computtion of Norton current

30 100 Chpter 3 Resistive Network Anlysis Recognizing tht i SC = v/, we cn determine the Norton current to e: i N = v v S = Thus, conceptully, the computtion of the Norton current simply requires identifying the pproprite short-circuit current. The following exmple further illustrtes this ide. FOCUS ON METHODOLOGY Computing the Norton Current 1. Replce the lod with short circuit. 2. Define the short circuit current, i SC, to e the Norton equivlent current. 3. Apply ny preferred method (e.g., nodl nlysis) to solve for i SC. 4. The Norton current is i N = i SC. EXAMPLE 3.15 Norton Equivlent Circuit V Prolem Determine the Norton current nd the Norton equivlent for the circuit of Figure I Figure 3.59 Solution Known Quntities: Source voltge nd current, resistor vlues. Find: Equivlent resistnce,. Norton current, i N = i SC. Schemtics, Digrms, Circuits, nd Given Dt: = 3 ; = 2. V = 6V;I = 2A; = 6 ; Figure 3.60 Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: We first compute the Thévenin equivlent resistnce. We zero the two sources y shorting the voltge source nd opening the current source. The resulting circuit is shown in Figure We cn clerly see tht = = = 4. Next we compute the Norton current. Following the Norton current methodology ox, we first replce the lod with short circuit, nd lel the short-circuit current, i SC. The circuit is shown in Figure 3.61 redy for node voltge nlysis. Note tht we hve identified two node voltges, v 1 nd v 2, nd tht the voltge source requires tht v 2 v 1 = V. The unknown current flowing through the voltge source is leled i. Applying KCL t nodes 1 nd 2, we otin the following set of equtions: I v 1 i = 0 node 1 i v 2 v 2 = 0 node 2

31 Prt I Circuits 101 v 1 V v 2 I i 1 i 2 i SC Figure 3.61 To eliminte one of the three unknowns, we sustitute v 2 V = v 1 in the first eqution: I v 2 V i = 0 node 1 nd we rewrite the equtions, recognizing tht the unknowns re i nd v 2. Note tht the short-circuit current is i SC = v 2 /. ( ) ( ) 1 1 (1) i v 2 = I V ( 1 ( 1)i 1 ) v 2 = 0 Sustituting numericl vlues we otin [ ] [ ] [ ] i 3 = v 2 0 nd cn numericlly solve for the two unknowns to find tht i = 2.5 A nd v 2 = 3V. Finlly, the Norton or short-circuit current is i N = i SC = v 2 / = 1.5 A. Comments: In this exmple it ws not ovious whether nodl nlysis, mesh nlysis, or superposition might e the quickest method to rrive t the nswer. It would e very good exercise to try the other two methods nd compre the complexity of the three solutions. The complete Norton equivlent circuit is shown in Figure A 4 Ω Figure 3.62 Norton equivlent circuit Source Trnsformtions This section illustrtes source trnsformtions, procedure tht my e very useful in the computtion of equivlent circuits, permitting, in some circumstnces, replcement of current sources with voltge sources, nd vice vers. The Norton nd Thévenin theorems stte tht ny one-port network cn e represented y voltge source in series with resistnce, or y current source in prllel with resistnce, nd tht either of these representtions is equivlent to the originl circuit, s illustrted in Figure An extension of this result is tht ny circuit in Thévenin equivlent form my e replced y circuit in Norton equivlent form, provided tht we use the following reltionship: v T = i N (3.32) Thus, the sucircuit to the left of the dshed line in Figure 3.64 my e replced y its Norton equivlent, s shown in the figure. Then, the computtion of i SC

32 102 Chpter 3 Resistive Network Anlysis One-port network v T _ i N v S _ i SC Thévenin equivlent Norton equivlent Figure 3.63 Equivlence of Thévenin nd Norton representtions v S i SC Figure 3.64 Effect of source trnsformtion ecomes very strightforwrd, since the three resistors re in prllel with the current source nd therefore simple current divider my e used to compute the short-circuit current. Oserve tht the short-circuit current is the current flowing through ; therefore, i SC = i N = 1/ v S v S = (3.33) 1/ 1/ 1/ which is the identicl result otined for the sme circuit in the preceding section, s you my esily verify. This source trnsformtion method cn e very useful, if employed correctly. Figure 3.65 shows how one cn recognize sucircuits menle to such source trnsformtions. Exmple 3.16 is numericl exmple illustrting the procedure. Node R or _ v S i S R i S R v S _ or Node Thévenin sucircuits Norton sucircuits Figure 3.65 Sucircuits menle to source trnsformtion EXAMPLE 3.16 Source Trnsformtions Prolem Compute the Norton equivlent of the circuit of Fig using source trnsformtions. Solution Known Quntities: Source voltges nd current, resistor vlues. Find: Equivlent resistnce, ; Norton current, i N = i SC.

33 Prt I Circuits 103 ' R 4 V 1 _ I R L V 2 ' Figure 3.66 Schemtics, Digrms, Circuits, nd Given Dt: V 1 = 50 V; I = 0.5 A;V 2 = 5V; = 100 ; = 100 ; = 200 ; R 4 = 160. Assumptions: Assume reference node is t the ottom of the circuit. Anlysis: First, we sketch the circuit gin, to tke dvntge of the source trnsformtion technique; we emphsize the loction of the nodes for this purpose, s shown in Figure Nodes nd hve een purposely seprted from nodes nd even though these re the sme pirs of nodes. We cn now replce the rnch consisting of V 1 nd, which ppers etween nodes nd, with n equivlent Norton circuit with Norton current source V 1 / nd equivlent resistnce. Similrly, the series rnch etween nodes nd is replced y n equivlent Norton circuit with Norton current source V 2 / nd equivlent resistnce. The result of these mnipultions is shown in Figure The sme circuit is now depicted in Figure 3.69 with numericl vlues sustituted for ech component. Note how esy it is to visulize the equivlent resistnce: if ech current source is replced y n open circuit, we find: = R 4 = = 200 " ' R 4 V 1 _ I R L V 2 " ' Figure 3.67 " ' R 4 V 1 I R 3 V 2 R 1 R L " ' Figure 3.68

34 104 Chpter 3 Resistive Network Anlysis 160 Ω 50 A A 1 A Ω 100 Ω 200 Ω R L Figure 3.69 The clcultion of the Norton current is similrly strightforwrd, since it simply involves summing the currents: A 200 Ω R L i N = = A Figure 3.70 Figure 3.70 depicts the complete Norton equivlent circuit connected to the lod. Comments: It is not lwys possile to reduce circuit s esily s ws shown in this exmple y mens of source trnsformtions. However, it my e dvntgeous to use source trnsformtion s mens of converting prts of circuit to different form, perhps more nturlly suited to prticulr solution method (e.g., nodl nlysis). Experimentl Determintion of Thévenin nd Norton Equivlents The ide of equivlent circuits s mens of representing complex nd sometimes unknown networks is useful not only nlyticlly, ut in prcticl engineering pplictions s well. It is very useful to hve mesure, for exmple, of the equivlent internl resistnce of n instrument, so s to hve n ide of its power requirements nd limittions. Fortuntely, Thévenin nd Norton equivlent circuits cn lso e evluted experimentlly y mens of very simple techniques. The sic ide is tht the Thévenin voltge is n open-circuit voltge nd the Norton current is short-circuit current. It should therefore e possile to conduct pproprite mesurements to determine these quntities. Once v T nd i N re known, we cn determine the Thévenin resistnce of the circuit eing nlyzed ccording to the reltionship = v T i N (3.34) How re v T nd i N mesured, then? Figure 3.71 illustrtes the mesurement of the open-circuit voltge nd shortcircuit current for n ritrry network connected to ny lod nd lso illustrtes tht the procedure requires some specil ttention, ecuse of the nonidel nture of ny prcticl mesuring instrument. The figure clerly illustrtes tht in the presence of finite meter resistnce, r m, one must tke this quntity into ccount in the computtion of the short-circuit current nd open-circuit voltge; v OC nd i SC pper etween quottion mrks in the figure specificlly to illustrte tht the mesured open-circuit voltge nd short-circuit current re in fct ffected y the internl resistnce of the mesuring instrument nd re not the true quntities.

35 Prt I Circuits 105 Unknown network Lod An unknown network connected to lod Unknown network i SC A r m Network connected for mesurement of short-circuit current Unknown network v OC V r m Network connected for mesurement of open-circuit voltge Figure 3.71 Mesurement of open-circuit voltge nd short-circuit current You should verify tht the following expressions for the true short-circuit current nd open-circuit voltge pply (see the mteril on nonidel mesuring instruments in Section 2.8): ( i N = i SC 1 r ) m ( v T = v OC 1 r m ) (3.35) where i N is the idel Norton current, v T the Thévenin voltge, nd the true Thévenin resistnce. If you recll the erlier discussion of the properties of idel mmeters nd voltmeters, you will recll tht for n idel mmeter, r m should pproch zero, while in n idel voltmeter, the internl resistnce should pproch n open circuit (infinity); thus, the two expressions just given permit the determintion of the true Thévenin nd Norton equivlent sources from n (imperfect) mesurement of the open-circuit voltge nd short-circuit current, provided tht the internl meter resistnce, r m, is known. Note lso tht, in prctice, the internl resistnce of voltmeters is sufficiently high to e considered infinite reltive to the equivlent resistnce of most prcticl circuits; on the other hnd, it is impossile to construct n mmeter tht hs zero internl resistnce. If the internl mmeter resistnce is known, however, resonly ccurte mesurement of short-circuit current my e otined. The following exmple illustrtes the point.

36 106 Chpter 3 Resistive Network Anlysis FOCUS ON MEASUREMENTS Experimentl Determintion of Thévenin Equivlent Circuit Prolem: Determine the Thévenin equivlent of n unknown circuit from mesurements of open-circuit voltge nd short-circuit current. Solution: Known Quntities Mesurement of short-circuit current nd open-circuit voltge. Internl resistnce of mesuring instrument. Find Equivlent resistnce, ;Thévenin voltge, v T = v OC. Schemtics, Digrms, Circuits, nd Given Dt Mesured v OC = 6.5 V; Mesured i SC = 3.75 ma; r m = 15. Assumptions The unknown circuit is liner circuit contining idel sources nd resistors only. Anlysis The unknown circuit, shown on the top left in Figure 3.72, is replced y its Thévenin equivlent, nd is connected to n mmeter for mesurement of the short-circuit current (Figure 3.72, top right), nd then to voltmeter for the mesurement of the open-circuit voltge (Figure 3.72, ottom). The open-circuit voltge mesurement yields the Thévenin voltge: v OC = v T = 6.5 V To determine the equivlent resistnce, we oserve in the figure depicting the voltge mesurement tht, ccording to the circuit digrm, v OC = r m i SC Thus, = v OC r m = 1, = 1,718 i SC An unknown circuit Lod terminls v T _ i SC A r m Network connected for mesurement of short-circuit current (prcticl mmeter) v T _ v OC V Network connected for mesurement of open-circuit voltge (idel voltmeter) Figure 3.72

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