Fully-parallel linear error block coding and decoding a Boolean approach

Size: px

Start display at page:

Download "Fully-parallel linear error block coding and decoding a Boolean approach"

Stanley Brooks
6 years ago
Views:

1 Fully-parallel linear error block coding and decoding a Boolean approach Hermann Meuth, Hochschule Darmstadt Katrin Tschirpke, Hochschule Aschaffenburg 8th International Workshop on Boolean Problems, 28 Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28

2 Background and of During transmission and storage of digital data, corruption and errors may and will occur. Errors make digital data indecipherable and thus meaningless, unlike errors in analogue data. For digital data there are no insignificant errors in the common sense To allow for error checking, redundancy is required, i.e. additional data without extending information content. Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 2

3 Background and of Digital data come in Bits. Redundancy thus adds further Bits without using them for information content Error coding may - alter message bits - may leave message bits unchanged. Here, redundancy or parity Bits may be interleaved or appended en bloc. This then is called a block code. Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 3

4 : Error Model Errors are superimposed onto the message during storage or transmission Due to the binary property, errors are superimposed bit-by-bit. If an error occurs, this amounts to flipping the respective bit. Otherwise, the bit remains unaltered error message currupted message Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 4

5 and Decoding Model The message is to be transformed by means of a generator, thereby extending the message, to form the coded message The error impacts on the entire coded message The corrupted message is to be decoded by means of a parity check closely related to the generator generator error parity check original message coded message received message syndrome Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 5

6 Linear and Decoding transformations G and H may be represented by matrices messages m, c, r, errors e and syndromes s as vectors algebra is modulo-2, with basic operations ± and may be completely represented by Boolean Algebra, with operations (XOR) and (AND) generator G error e parity check H original message m coded message c received message r syndrome s Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 6

7 Linear Error Block Coding and Decoding message vector of k Bits parity-bit vector of n-k Bits coded message vector of n Bits generator matrix G of k rows and n columns Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 7

8 generator matrix has cyclic property generator reduces to vector of n-k+ elements, of which n-k- may freely be determined for optimum coding regularly implemented serially (for CRC) - in software by modulo-2 or polynomial division scheme - in hardware by Linear-Feedback-Shift-Register Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 8

9 coding procedure by means of the generator matrix G (n-k) parities result from the (n-k) Boolean conditions generator G error e parity check H original message m coded message c received message r syndrome s Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 9

10 decoding procedure by means of the transposed parity check matrix H (n-k) syndromes result from the (n-k) Boolean conditions generator G error e parity check H original message m coded message c received message r syndrome s Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28

11 of Encoder fully-parallel architecture, containing &- and XOR-trees readily formulated in HDL as configurable component, and implemented e.g. in FPGA/CPLD based hardware, which allows for real-time zero-clock delay solutions Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28

12 of Decoder fully-parallel architecture, containing &- and XOR-trees readily formulated in HDL as configurable component, and implemented e.g. in FPGA/CPLD based hardware, which allows for real-time zero-clock delay solutions Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 2

13 generally, a generator matrix G of k rows and n columns contains (n-k) k binary parameters to tailor error coding for optimum or specific feature error detection, these (n-k) k parameters may be chosen suitably at will. for comparison, cyclic codes contain only (n-k-) such free parameters Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 3

14 binary optimization problem input: all (2 n -) possible error vectors of length n e =(,,,,), e 2 =(,,,,), e³=(,,,,), etc. output: the parity bits p ij of generator G and also the indicatorsδ(e r ), where e r is detected δ(e r ) = e r is not detected δ(e r ) = Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 4

15 define an objective function in terms of the indicators δ(e r ) OF = Max n 2 r= 2 r n+ l( e ) δ ( e where l(e r ) is the number of Bit flips = number of errors i.e. OF weights -Bit errors the highest subject to further constraints to improve on optimisation procedure r ) Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 5

16 constraints to detect an error e r, at least one of the n-k syndromes has to be non-zero k r r r s j ( e ) e j = + ei+ n k pi, i= n k j= s n k j= j ( e r j j ) M mod 2 the indicator δ(e r ) for a certain error must be bounded by the sum over all syndromes for this error r s ( e ) δ ( e further, an additional technical constraint is introduced, where M >> to actually detect all m-bit errors M δ ( e r ) δ ( e m + l( e r r r ) ) ) Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 6

17 binary optimization problem input: all (2 n -) possible error vectors of length n e =(,,,,), e 2 =(,,,,), e³=(,,,,), etc. output: the parity bits p ij of generator G and also the indicatorsδ(e r ), where e r is detected δ(e r ) = e r is not detected δ(e r ) = Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 7

18 performance measured against Hamming distance d min = td + tc + = Min q= n CI q CJ q I, J; I J and t D = of detectable, t C = of correctable errors, t D t C achieved number of errors detected, t D, depending on n, k K\N K/N Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 8

19 assigning to each syndrome s j (e r ) one and only one error e r will constrain the doublets (n,k) according to Bose-Chaudhuri- Hocquenghem (BCH) to arrive at of correctable errors t C 2 8 k up to Bit up to 2 Bit up to 3 Bit up to 4 Bit and n the achieved error detection performance is at the theoretical Hamming limit Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 9

20 Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 2 Background and = P 4,4 = P 4,3 sample generator results standard Hamming n=7, k=4 (standard CRC Code for polynomial g(x)=+x+x³) n=8, k=4 all errors up to 3 Bit are detected n=6, k=8 all errors up to 4 Bit are detected Example Results and = P 8,8

21 plain-vanilla FPGA-based simulations on actual hardware implementations show turn-around times of < ns higher gate count is unavoidable in these fully parallel architectures and Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 2

22 new error codes with much higher degree of optimisation potential were presented performance is achieved at the theoretical Hamming limit hardware implementations result as scalable, HDL suitable architectures with hitherto impossible turnaround times Thank you for your attention! Hochschule Darmstadt, Hochschule Aschaffenburg IWSBP28 22

Cyclic Redundancy Check Codes

Cyclic Redundancy Check Codes Lectures No. 17 and 18 Dr. Aoife Moloney School of Electronics and Communications Dublin Institute of Technology Overview These lectures will look at the following: Cyclic