74HC4066; 74HCT4066. Quad single-pole single-throw analog switch
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1 Rev. 7 2 pril 2013 Product data sheet 1. General description The is a quad single pole, single throw analog switch. Each switch features two input/output terminals (ny and nz) and an active HIGH enable input (ne). When ne is LOW, the analog switch is turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of. 2. Features and benefits Input levels ne inputs: For 74HC4066: CMOS level For 74HCT4066: TTL level Low ON resistance: 50 (typical) at = 4.5 V 45 (typical) at = 6.0 V 35 (typical) at = 9.0 V Specified in compliance with JEDEC standard no. 7 ESD protection: HBM JESD22-114F exceeds 2000 V MM JESD exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C
2 3. Ordering information Table 1. Type number Ordering information Package Temperature range Name Description Version 74HC4066N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT HCT4066N 74HC4066D 74HCT4066D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74HC4066DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body 74HCT4066DB width 5.3 mm 74HC4066PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body 74HCT4066PW width 4.4 mm 74HC4066BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very 74HCT4066BQ thin quad flat package; no leads; 14 terminals; body mm 4. Functional diagram SOT108-1 SOT337-1 SOT402-1 SOT Y 1Z E 4 2Y 2Z 3 5 2E 8 3Y 3Z 9 6 3E 11 4Y 4Z E 001aad # 4 3 5# 8 9 6# # (a) # X # X # X # X1 (b) 001aad270 Fig 1. Logic symbol Fig 2. IEC logic symbol Product data sheet Rev. 7 2 pril of 25
3 ny ne GND nz 001aad271 Fig 3. Schematic diagram (one switch) 5. Pinning information 5.1 Pinning 1Y 1 14 terminal 1 index area 1Y VCC 1Z E 1Z E 2Z 2Y 2E 3E E 4Y 4Z 3Z 2Z 2Y 2E 3E V (1) CC E 4Y 4Z 3Z GND 7 8 3Y GND 3Y 001aac aad268 Transparent top view Fig 4. Pin configuration for DIP14, SO14, SSOP14 and TSSOP14 Fig 5. (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Pin configuration for DHVQFN Pin description Table 2. Pin description Symbol Pin Description 1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output 1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output GND 7 ground (0 V) 1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH) 14 supply voltage Product data sheet Rev. 7 2 pril of 25
4 6. Functional description Table 3. Function table [1] Input ne L H Switch OFF ON [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit supply voltage V I IK input clamping current V I < 0.5 V or V I > +0.5V - 20 m I SK switch clamping current V SW < 0.5 V or V SW > +0.5V - 20 m I SW switch current V SW = 0.5 V to +0.5V [1] - 25 m I CC supply current - 50 m I GND ground current - 50 m T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C [2] DIP14 package SO14, (T)SSOP14 and DHVQFN packages P power dissipation per switch mw [1] To avoid drawing current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no current will flow out of terminals Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed or GND. [2] For DIP14 package: P tot derates linearly with 12 mw/k above 70 C. For SO14 package: P tot derates linearly with 8 mw/k above 70 C. For (T)SSOP14 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN14 packages: P tot derates linearly with 4.5 mw/k above 60 C. Product data sheet Rev. 7 2 pril of 25
5 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC HCT4066 Unit 9. Static characteristics Min Typ Max Min Typ Max supply voltage V V I input voltage GND - GND - V V SW switch voltage GND - GND - V T amb ambient temperature C t/ V input transition rise and fall rate = 2.0 V ns/v = 4.5 V ns/v = 6.0 V ns/v = 10.0 V ns/v Table 6. R ON resistance per switch for types 74HC4066 and 74HCT4066 V I = V IH or V IL ; for test circuit see Figure 6. V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4066: GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4066: GND = 4.5 V. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit R ON(peak) ON resistance (peak) V is = to GND R ON(rail) ON resistance (rail) V is = GND Min Typ [1] Max Min Max = 2.0 V; I SW = 100 [2] = 4.5 V; I SW = = 6.0 V; I SW = = 9.0 V; I SW = = 2.0 V; I SW = 100 [2] = 4.5 V; I SW = = 6.0 V; I SW = = 9.0 V; I SW = V is = = 2.0 V; I SW = 100 [2] = 4.5 V; I SW = = 6.0 V; I SW = = 9.0 V; I SW = Product data sheet Rev. 7 2 pril of 25
6 Table 6. R ON resistance per switch for types 74HC4066 and 74HCT4066 continued V I = V IH or V IL ; for test circuit see Figure 6. V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4066: GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4066: GND = 4.5 V. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max R ON ON resistance V is = to GND mismatch between = 2.0 V [2] channels = 4.5 V = 6.0 V = 9.0 V [1] Typical values are measured at T amb = 25 C. [2] t supply voltages ( GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 60 aaa R ON (Ω) 50 = 4.5 V V SW 40 6 V 9 V V IH ne 30 ny nz 20 Vis GND ISW aaa V is (V) V is = 0 V to V is = 0 V to R ON V SW = I SW Fig 6. Test circuit for measuring R ON Fig 7. Typical R ON as a function of input voltage V is Product data sheet Rev. 7 2 pril of 25
7 Table 7. Static characteristics 74HC4066 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ [1] Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage = 2.0 V V = 4.5 V V = 6.0 V V = 9.0 V V V IL LOW-level input voltage = 2.0 V V = 4.5 V V = 6.0 V V = 9.0 V V I I input leakage current V I = or GND = 6.0 V = 10.0 V I S(OFF) OFF-state leakage current = 10.0 V; V I = V IH or V IL ; V SW = GND; see Figure 8 per channel I S(ON) ON-state leakage current = 10.0 V; V I = V IH or V IL ; V SW = GND; see Figure 9 I CC supply current V I = or GND; V is = GND or ; V os = or GND = 6.0 V = 10.0 V C I input capacitance pf C sw switch capacitance pf T amb = 40 C to +125 C V IH HIGH-level input voltage = 2.0 V V = 4.5 V V = 6.0 V V = 9.0 V V V IL LOW-level input voltage = 2.0 V V = 4.5 V V = 6.0 V V = 9.0 V V I I input leakage current V I = or GND = 6.0 V = 10.0 V I S(OFF) OFF-state leakage current = 10.0 V; V I = V IH or V IL ; V SW = GND; see Figure 8 per channel I S(ON) ON-state leakage current = 10.0 V; V I = V IH or V IL ; V SW = GND; see Figure Product data sheet Rev. 7 2 pril of 25
8 Table 7. Static characteristics 74HC4066 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ [1] Max Unit I CC supply current V I = or GND; V is = GND or ; V os = or GND [1] Typical values are measured at T amb = 25 C. = 6.0 V = 10.0 V Table 8. Static characteristics 74HCT4066 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ [1] Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage = 4.5 V to 5.5 V V V IL LOW-level input voltage = 4.5 V to 5.5 V V I I input leakage current V I = or GND; = 5.5 V I S(OFF) OFF-state leakage current = 5.5 V; V I = V IH or V IL ; V SW = GND; see Figure 8 per channel I S(ON) ON-state leakage current = 5.5 V; V I = V IH or V IL ; V SW = GND; see Figure 9 I CC supply current V I = or GND; V is = GND or ; V os = or GND; = 4.5 V to 5.5 V I CC additional supply current per input pin; V I = 2.1 V; other inputs at or GND; = 4.5 V to 5.5 V C I input capacitance pf C sw switch capacitance pf T amb = 40 C to +125 C V IH HIGH-level input voltage = 4.5 V to 5.5 V V V IL LOW-level input voltage = 4.5 V to 5.5 V V I I input leakage current V I = or GND; = 5.5 V I S(OFF) OFF-state leakage current = 5.5 V; V I = V IH or V IL ; V SW = GND; see Figure 8 per channel I S(ON) ON-state leakage current = 5.5 V; V I = V IH or V IL ; V SW = GND; see Figure 9 I CC supply current V I = or GND; V is = GND or ; V os = or GND; = 4.5 V to 5.5 V I CC additional supply current per input pin; V I = 2.1 V; other inputs at or GND; = 4.5 V to 5.5 V [1] Typical values are measured at T amb = 25 C. Product data sheet Rev. 7 2 pril of 25
9 V IL E V IH E Z Yn I SW Yn Z I SW I SW V os Vis GND Vos Vis GND aaa aaa V is = and V os = GND V is = GND and V os = V is = and V os = open V is = GND and V os = open Fig 8. Test circuit for measuring OFF-state leakage current Fig 9. Test circuit for measuring ON-state leakage current 10. Dynamic characteristics Table 9. Dynamic characteristics 74HC4066 GND = 0 V; t r = t f = 6 ns; C L = 50 pf unless specified otherwise; for test circuit see Figure 12. V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max t pd propagation delay ny to nz or nz to ny; R L = ; see Figure 10 [2] = 2.0 V ns = 4.5 V ns = 6.0 V ns = 9.0 V ns t off turn-off time ne to ny or nz; see Figure 11 [4] = 2.0 V ns = 4.5 V ns = 5.0 V; C L = 15 pf ns = 6.0 V ns = 9.0 V ns t on turn-on time ne to ny or nz; see Figure 11 [3] C PD power dissipation capacitance [1] Typical values are measured at T amb = 25 C. [2] t pd is the same as t PHL and t PLH. [3] t on is the same as t PHZ and t PLZ. = 2.0 V ns = 4.5 V ns = 5.0 V; C L = 15 pf ns = 6.0 V ns = 9.0 V ns per switch; V I = GND to [5] pf Product data sheet Rev. 7 2 pril of 25
10 [4] t off is the same as t PZH and t PZL. [5] C PD is used to determine the dynamic power dissipation (P D in W). P D = C PD V 2 CC f i + {(C L +C sw ) V 2 CC f o } where: f i = input frequency in MHz; f o = output frequency in MHz; {(C L +C sw ) V 2 CC f o } = sum of outputs; C L = output load capacitance in pf; C sw = switch capacitance in pf; = supply voltage in V. Table 10. Dynamic characteristics 74HCT4066 GND = 0 V; t r = t f = 6 ns; C L = 50 pf unless specified otherwise; for test circuit see Figure 12. V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max t pd propagation delay [1] Typical values are measured at T amb = 25 C. [2] t pd is the same as t PHL and t PLH. [3] t on is the same as t PHZ and t PLZ. [4] t off is the same as t PZH and t PZL. [5] C PD is used to determine the dynamic power dissipation (P D in W). P D = C PD 2 f i + {(C L +C sw ) 2 f o } where: f i = input frequency in MHz; f o = output frequency in MHz; {(C L +C sw ) 2 f o } = sum of outputs; C L = output load capacitance in pf; C sw = switch capacitance in pf; = supply voltage in V. ny to nz or nz to ny; R L = ; [2] see Figure 10 = 4.5 V ns t off turn-off time ne to ny or nz; see Figure 11 [4] = 4.5 V ns = 5.0 V; C L = 15 pf ns t on turn-on time ne to ny or nz; see Figure 11 [3] C PD power dissipation capacitance = 4.5 V ns = 5.0 V; C L = 15 pf ns per switch; [5] pf V I =GNDto( 1.5 V) Product data sheet Rev. 7 2 pril of 25
11 11. Waveforms V is input 50 % t PLH t PHL V os output 50 % 001aad555 Fig 10. Input (V is ) to output (V os ) propagation delays V I E input V M 0 V t PLZ t PZL V os output 10 % 50 % t PHZ t PZH V os output 90 % 50 % switch ON switch OFF switch ON aaa Fig 11. Measurement points are shown in Table 11. Turn-on and turn-off times Table 11. Measurement points Type V I V M 74HC HCT V 1.3 V Product data sheet Rev. 7 2 pril of 25
12 V I negative pulse 0 V 90 % V M 10 % t W V M t f t r t r t f V I positive pulse 0 V 10 % 90 % V M t W V M V is PULSE GENERTOR V I DUT V os RL S1 open RT CL GND 001aag732 Fig 12. Test data is given in Table 12. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistor. S1 = Test selection switch. Load circuitry for measuring switching times Table 12. Test data Test Input Output S1 position Control E Switch Yn (Z) t r, t f Switch Z (Yn) V [1] I V is C L R L t PHL, t PLH GND GND to 6 ns 50 pf - open t PHZ, t PZH GND to 6ns 50pF, 15pF 1k GND t PLZ, t PZL GND to GND 6 ns 50 pf, 15 pf 1 k [1] For 74HCT4066: maximum input voltage V I = 3.0 V. Product data sheet Rev. 7 2 pril of 25
13 12. dditional dynamic characteristics Table 13. dditional dynamic characteristics Recommended conditions and typical values; GND = 0 V; T amb = 25 C. V is is the input voltage at a Yn or Z terminal, whichever is assigned as an input. V os is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit THD total harmonic distortion f i = 1 khz; R L = 10 k ; C L =50pF; % see Figure 13 = 4.5 V; V I = 4.0 V (p-p) % = 9.0 V; V I = 8.0 V (p-p) % f i =10kHz; R L = 10 k ; C L =50pF; see Figure 13 = 4.5 V; V I = 4.0 V (p-p) % = 9.0 V; V I = 8.0 V (p-p) % f ( 3dB) 3 db frequency response R L = 50 ; C L =10pF; seefigure 15 [2] = 4.5 V MHz = 9.0 V MHz iso isolation (OFF-state) R L = 600 ; C L =50pF; f i = 1 MHz; see Figure 14 [1] = 4.5 V db = 9.0 V db V ct crosstalk voltage between digital input and switch (peak to peak value); R L = 600 ; C L =50pF; f i = 1 MHz; see Figure 16 = 4.5 V mv = 9.0 V mv Xtalk crosstalk between switches; R L = 600 ; C L =50pF; f i = 1 MHz; see Figure 17 [1] = 4.5 V db = 9.0 V db [1] djust input voltage V is to 0 dbm level (0 dbm = 1 mw into 600 ). [2] djust input voltage V is to 0 dbm level at V os for f i = 1 MHz (0 dbm = 1 mw into 50 ). fter set-up, f i is increased to obtain a reading of 3 db at V os. V IH ne 10 μf ny/nz nz/ny V O fi CL D 001aaj468 Fig 13. Test circuit for measuring total harmonic distortion Product data sheet Rev. 7 2 pril of 25
14 0 mna082 (db) f i (khz) a. Isolation (OFF-state) V IL ne 0.1 μf ny/nz nz/ny V O fi CL db 001aaj470 b. Test circuit Fig 14. = 4.5 V; GND = 0 V; R L = 600 ; R source = 1 k. Isolation (OFF-state) as a function of frequency Product data sheet Rev. 7 2 pril of 25
15 5 mna083 (db) f i (khz) a. Typical 3 db frequency response V IH ne 0.1 μf ny/nz nz/ny V O fi CL db 001aaj469 b. Test circuit Fig 15. = 4.5 V; GND = 0 V; R L = 50 ; R source = 1 k. 3 db frequency response Product data sheet Rev. 7 2 pril of 25
16 ny/nz ne DUT GND nz/ny CL oscilloscope GND mnb011 a. Circuit V(p p) mnb012 b. Crosstalk voltage Fig 16. Test circuit for measuring crosstalk voltage (between the digital input and the switch) V IH 1E 0.1 μf RL 1Y or 1Z 1Z or 1Y fi CHNNEL ON CL V VO1 V IL VCC 2E 2Y or 2Z 2Z or 2Y CHNNEL OFF CL V VO2 001aai846 Fig 17. Test circuit for measuring crosstalk (between the switches) Product data sheet Rev. 7 2 pril of 25
17 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT G04 MO-001 SC Fig 18. Package outline SOT27-1 (DIP14) Product data sheet Rev. 7 2 pril of 25
18 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E06 MS Fig 19. Package outline SOT108-1 (SO14) Product data sheet Rev. 7 2 pril of 25
19 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 detail X L p L θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO Fig 20. Package outline SOT337-1 (SSOP14) Product data sheet Rev. 7 2 pril of 25
20 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 21. Package outline SOT402-1 (TSSOP14) Product data sheet Rev. 7 2 pril of 25
21 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M C C B y 1 C C y L 1 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) Eh e e1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 22. Package outline SOT762-1 (DHVQFN14) Product data sheet Rev. 7 2 pril of 25
22 14. bbreviations Table 14. cronym CMOS ESD HBM MM bbreviations Description Complementary Metal Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4066 v Product data sheet - 74HC_HCT4066 v.6 Modifications: Descriptive title corrected (errata). New general description (errata). 74HC_HCT4066 v Product data sheet - 74HC_HCT4066 v.5 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 74HC_HCT4066 v Product data sheet - 74HC_HCT4066 v.4 74HC_HCT4066 v Product data sheet - 74HC_HCT4066_CNV v.3 74HC_HCT4067_CNV v Product data sheet - 74HC_HCT4066_CNV v.2 74HC_HCT4066_CNV v Product specification - - Product data sheet Rev. 7 2 pril of 25
23 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 7 2 pril of 25
24 Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Product data sheet Rev. 7 2 pril of 25
25 18. Contents 1 General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms dditional dynamic characteristics Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 2 pril 2013 Document identifier: 74HC_HCT4066
The 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
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Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
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Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
More informationThe 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
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Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
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Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
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74HC4066-Q100; 74HCT4066-Q100 Rev. 1 12 July 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4066B-Q100. The device is specified
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74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
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Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
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Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
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Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate
Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables
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Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More information74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting
Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
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Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More information74HC08-Q100; 74HCT08-Q100
Rev. 1 16 July 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input ND gate. Inputs include clamp diodes. This
More information74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate
Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
More information74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More information74HC238; 74HCT to-8 line decoder/demultiplexer
Rev. 03 16 July 2007 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238
More information74HC126; 74HCT126. Quad buffer/line driver; 3-state
Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
More information74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer
Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
More information74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer
Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
More information2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
More information74HC30-Q100; 74HCT30-Q100
Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More informationTemperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
More information74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.
Rev. 6 13 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a quad 2-input ND gate. Inputs include
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Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
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Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
More informationHex inverter with open-drain outputs
Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
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Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They
More information74HC32-Q100; 74HCT32-Q100
Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
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Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs
More informationThe 74LV08 provides a quad 2-input AND function.
Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
More information74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
More information74HC365; 74HCT365. Hex buffer/line driver; 3-state
Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn
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Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.
More information74AHC30-Q100; 74AHCT30-Q100
Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
More information74HC151-Q100; 74HCT151-Q100
Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0
More information74HC153-Q100; 74HCT153-Q100
Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
More information74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.
Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
More informationThe 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
More information74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting
Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable
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Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1
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Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators
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Rev. 05 5 May 2008 Product data sheet 1. General description 2. Features 3. pplications The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance
More information74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
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Rev. 9 13 December 2011 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard
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74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
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Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
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Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage
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Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and
More informationThe 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
74BT25 Rev. 6 3 November 20 Product data sheet. General description The 74BT25 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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74HC541-Q100; 74HCT541-Q100 Rev. 1 6 June 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state bus compatible
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Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
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Rev. October 202 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
More information74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe
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Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
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Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
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Rev. 6 17 March 2016 Product data sheet 1. General description The is an with three digital select inputs (S0 to S2), an active-low enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common
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Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
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Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
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Rev. 6 3 ugust 0 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard
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Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
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Rev. 8 11 May 2011 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard no.
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74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.
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Rev. 8 5 February 2016 Product data sheet 1. General description The is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications.
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Rev. 3 5 October 207 Product data sheet General description 2 Features and benefits 3 Ordering information Table. Ordering information Type number Package The is a high-performance, low-power, low-voltage,
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Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed
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Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
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Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
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Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
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Rev. 4 27 June 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The decoder accepts three binary weighted
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Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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74LVC00 Quad 2-input NND gate Rev. 7 25 pril 202 Product data sheet. General description The 74LVC00 provides four 2-input NND gates. Schmitt trigger action at all inputs makes the circuit tolerant of
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Rev. 6 2 September 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The provides four 2-input OR gates. Inputs
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Rev. 5 1 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock
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Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 6 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive
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