Trace Compaction using SAT-based Reachability Analysis

Transcription

1 Trce Compction using SAT-bsed Rechbility Anlysis Sen Sfrpour, Andres Veneris, Hrtch Mngssrin Deprtment of Electricl nd Computer Engineering University of Toronto, Toronto, Cnd {sen, veneris, Abstrct In tody s designs, when functionl verifiction fils, engineers perform debugging using the provided error trces. Reducing the length of error trces cn help the debugging tsk by decresing the number of vribles nd clock cycles tht must be considered. We propose novel trce length compction pproch bsed on SAT-bsed rechbility nlysis. We develop procedures nd lgorithms using pre-imge computtion to efficiently trverse the stte spce nd reduce the trce lengths. We further introduce dt structure used to store the visited sttes which is criticl to the performnce of the proposed pproch. Experiments demonstrte the effectiveness of the rechbility pproch s pproximtely 75% of the trces re reduced by one or two orders of mgnitudes. I. INTRODUCTION Functionl verifiction of digitl circuits is mjor problem for the VLSI design community. It is reported tht up 70% of the cost nd effort of VLSI design is due to verifiction nd debugging []. Debugging, which consists of locting nd fixing errors or bugs in n erroneous design, is responsible for pproximtely 50% of the overll verifiction cost []. Given seuentil circuit nd golden model tht specifies the correct behvior of the circuit, verifiction tools cn determine whether the circuit is consistent with the golden model. Mny different verifiction pproches exist tody such s simultion-bsed methods, nd bounded nd unbounded forml techniues [2]. Despite the recent dvnces in the field of forml verifiction, most VLSI compnies still use simultion techniues s centrl verifiction strtegy []. Performing verifiction vi simultion cnnot prove the correctness of design unless the complete behvior of the design is exercised [2]. Since proving the correctness my not be n option for tody s lrge designs, performing lrge number of simultions cn chieve high level of confidence in the design s correctness. A testbench cn exercise the design with the help of rndom or semi-rndom stimulus genertors. The testbench cn lso determine whether the design nd the model re inconsistent in their response to the stimulus. In this cse, n error trce or counter-exmple, consisting of seuence of ctions or sttes from the initil sttes to the error, is produced. The verifiction engineer hs the responsibility of determining why design nd golden model hve inconsistent behviors bsed on the error trce(s). Since trce is often derived from rndom simultion, the seuence of events leding to the error cn be unnecessrily long. In other words, shorter error trce my be ble to describe the sme erroneous behvior in less clock cycles. With shorter trce, the debugging tsk of the verifiction engineer cn be considerbly reduced s fewer signls nd clock cycles must be considered. As result, reducing the length of trces cn substntilly increse the efficiency of design debugging. Previous work shows tht for rndom nd semi-rndom bsed simultions, error trces cn often be reduced to frction of their initil size [3], [4], [5], [6]. One such techniue uses forwrd imge computtion using Binry Decision Digrms (BDDs) to reduce the trces [3]. In [4], techniues re presented to remove vribles from counter exmples in order to simplify them, but their lengths re not reduced. Another recent work uses severl techniues bsed on performing further simultions nd Bounded Model Checking (BMC) to chieve smll trces [5]. The techniue of [6] is the closest to ours s they utilize seuentil Boolen Stisfibility (SAT) solver to find short-cuts in the originl trce. More specificlly, [6] seeks to find the shortest pth from the initil stte to some cndidte intermedite stte similr to BMC but using seuentil SAT solver. In this work, we propose trce length compction techniue where the shortest pth from the initil stte to finl stte is sought. This pproch is bsed on rechbility nlysis where n ll-solution SAT solver is used s the pre-imge computtion engine [7], [8], [9]. The benefits over the existing BDD [3] nd BMC techniues [5] re tht the BDD memory explosion problem cn be verted nd tht compctions exceeding the finite bound of BMC pproches my be pplied. Our techniue ppers to shre mny of the dvntges of the seuentil SAT pproch proposed in [6]. The min difference is tht ours relies on rechbility nlysis nd pre-imge computtion while mking use of novel dt structure to determine stte continment reltionships. More specificlly, the contributions of this pper re the following. A trce compction techniue bsed purely on pre-imge computtion nd rechbility nlysis using n ll-solution SAT solver. A set of continment rules tht help drw reltionships between existing sttes nd sttes found through pre-imge computtion which my result in shorter trces. A stte selection procedure within the rechbility nlysis engine nd set of heuristics tht improve the performnce of the overll pproch in prctice. A novel dt structure for storing visited sttes tht llows for uick identifiction of stte continment reltionships. This pper is orgnized s follows. In the next section, some bckground informtion is provided on finite stte mchines, preimge computtion, nd rechbility nlysis. Section III presents the proposed trce compction pproch nd discusses its centrl procedures. Section IV, introduces novel dt structure criticl for the efficient performnce of the proposed pproch. Sections V nd VI demonstrte the experimentl results nd conclude the pper, respectively. II. PRELIMINARIES In this section we provide some bckground on Finite Stte Mchines, trces, imge nd pre-imge computtion, nd rechbility nlysis. We ssume tht the reder is fmilir with SAT solver terminology [7]. A. Finite Stte Mchines A seuentil digitl circuit cn be modeled by Finite Stte Mchine (FSM) represented by 6-tuple M := (Q,Σ,, δ, λ, 0)

2 where Q is the finite set of sttes, Σ re re the input nd output lphbets respectively, δ : Q Σ Q is the stte trnsition function, λ : Q Σ is the output function, nd 0 is the initil stte [2]. Figure illustrtes simple FSM where the sttes re represented by nodes nd the trnsitions re represented by edges pre-imge i 0 pre-imge 3 pre-imge 2 pre-imge k Fig.. Finite Stte Mchine with 7 sttes A trce of length k for n FSM is n input seuence <,,, k > tht leds the FSM through seuence of sttes < 0,,, k, k >. Note tht some sttes my be repeted in the stte seuence. Figure 2 represents one possible trce for the FSM of Figure Fig A smple trce for the bove FSM B. Imge nd Pre-imge Computtion Given seuentil circuit with current stte vribles V nd next stte vribles V, set of current sttes nd set of next sttes re lbeled by Q(V ) nd Q(V ) respectively. The trnsition reltion from set of sttes Q(V ) to Q(V ), denoted by T(Q(V ), Q(V )), is true for ech pir of Q(V ) nd Q(V ) if δ(q(v )) = Q(V ) for set of input ssignments [2]. Given the bove, the imge nd pre-imge of circuit cn be defined s follows. IMAGE: Q(V ) = V.(T(Q(V ), Q(V )) Q(V )) PRE-IMAGE: Q(V ) = V.(T(Q(V ), Q(V )) Q(V )) Intuitively, the imge of stte i is ll the sttes tht cn be reched from i under ll possible input combintions in single clock cycle. Similrly, the pre-imge of i comprises of ll the sttes tht cn led to i under ll possible input combintions in one clock cycle. In the FSM of Figure, the imge of stte is { 2, 6} while its pre-imge is { 0, 3}. Although the imge nd pre-imge of circuits re trditionlly computed using BDDs [2], some techniues bsed on ll-solution Boolen Stisfibility (SAT) solvers cn lso be used [8], [9], [0], []. All-solution SAT solvers cn compute the pre-imge set Q(V ) by constrining the circuit CNF to Q(V ) nd itertively finding ll the solutions tht stisfy the CNF in terms of the current stte vribles V [0]. Recent work on SAT-bsed Unbounded Model Checking (UMC) nd pre-imge computtion techniues hve demonstrted considerble dvncements [8], [9], [0], []. In this work, we re minly concerned with SAT-bsed pre-imge computtion. Since this techniue finds sttes one t time, we use the term pre-imge loosely to lso refer to single stte jtht belongs to the pre-imge of i. Furthermore, we use the term stte to refer to stte cube, which is stte encoding tht my contin unssigned or don t cre vribles. As such, stte my be superset (cover) of other sttes. For instnce, the stte cube {v, v 2, v 3} =X covers the sttes {v, v 2, v 3}=0 nd {v, v 2, v 3}=. For brevity, in the remining of this pper we drop the vrible nmes (i.e. v, v 2, v 2) when describing stte vlues. C. Rechbility Anlysis Rechbility nlysis is the process of determining whether stte k is rechble from nother stte 0. In the relm of UMC, 0 6 Fig. 3. initil stte found Illustrtion of rechbility nlysis rechbility nlysis cn be used to check CTL properties of type EF k where k is bd stte nd 0 is legl or initil stte [2]. Intuitively, rechbility nlysis trverses the stte spce bckwrds from stte k until stte 0 is found or fix-point, where no new sttes re found, is reched [2]. Pre-imge computtion is centrl procedure of rechbility nlysis s it performs the single bckwrd steps. The mnner in which the stte spce is trversed depends on which of the visited sttes is selected for ech preimge computtion step. If the visited sttes re stored in stck-like dt structure, depth-first trversl is performed, while ueue-like dt structure results in bredth-first trversl. Figure 3 illustrtes bredth-first rechbility nlysis process tht eventully finds the initil stte 0. In this figure, the blck nodes represent sttes while ech cone represents set of sttes found by one pre-imge computtion step. III. PROPOSED TRACE COMPACTION APPROACH In this section we present our proposed trce length compction pproch. First we introduce the centrl concept followed by detils of the stte selection procedure nd the ll-solution SAT solver. A. Rechbility Bsed Trce Compction A trce cn be represented by directed grph G = (N, E) where the nodes N represent sttes nd the edges E represent trnsitions between sttes. An edge from stte i to j denotes tht i belongs to the pre-imge of j nd j belongs to the imge of i. Our objective is to reduce the length of the pth from the initil stte 0 to the finl stte k by pplying pre-imge computtion nd rechbility nlysis techniues. Our proposed pproch performs rechbility nlysis on ll the sttes belonging to the originl trce. The mnner in which sttes re selected for rechbility nlysis is described in Section III-C. All the sttes (or stte cubes) found by the pre-imge computtion steps of the rechbility engine re dded to the grph G. Grph G is updted with edges denoting tht ech newly found sttes i is pre-imge of some stte j, selected for pre-imge computtion. Fig Updting the grph G with new nodes nd edges When sttes found by pre-imge computtion lredy exist in the grph G, extr edges my be drwn in G to illustrte new legl trnsitions. These trnsitions my provide shorter pth (or short-cut) from the initil stte to the finl stte thus reducing the overll trce length. For exmple consider the sitution described in Figure 4 where the originl trce is shown s the seuence < 0,, 2, 3, 4 > nd the dshed nodes re sttes found through rechbility nlysis. Since 2 is found s pre-imge of 4, nd is the pre-imge of 2 in the originl trce, new edge shown 5 4

3 s dshed line cn be drwn directly from the originl (non-dshed) 2 to 4 nd the dshed 2 cn be removed. The overll result is shorter pth from 0 to 4 which skips node 3. As motivted by the bove exmple, finding stte euivlences in the grph G cn led to more short-cuts which cn reduce the overll trce size. Along with the stte euivlence reltion discussed, there re other stte continment reltionships tht cn led to further short-cuts in the grph. The following rules determine how the grph G is updted fter ech pre-imges computtion step. Consider stte i found s pre-imge of stte i+, nd the seuence < j, j, j+ > existing in the grph G. Rule. If i = j: Stte i is not dded to G, but n edge is drwn from j to i+. Rule 2. If i j: Stte i is dded to G, n edge is drwn from i to i+, nd nother edge is drwn from j to i+. Rule 3. If i j: Stte i is dded to G, n edge is drwn from i to i+, nother edge is drwn from j to i, nd nother edge is drwn from i to j+. The correctness of rule is evident s the imges of euivlent sttes re lso euivlent. Rule 2 cn be explined by expnding the stte cube i, into two components i = { j} S { i j}. From here we use the fct tht ny imge of i is lso n imge of j. Similrly, rule 3 cn be explined by expnding j into two components j = { i} S { j i}. i =X i+ =0 i+ =0 = X j- j j+ j- j j+ () Fig. 5. Illustrting rules 2 nd 3 The following exmple helps clrify rules 2 nd 3. Consider stte i found s pre-imge of stte i+, nd the seuence < j, j, j+ >, where stte i =X nd the stte j = 0. By rule 2, n edge is first drwn from i to i+ to indicte tht i is pre-imge of stte i+. Since X 0 nd i+ is n imge of i =X= {0} S {}, then i+ must lso be n imge of j = 0. This scenrio is illustrted in Figure 5 () with the new edges drwn s dshed lines. Similrly, by rule 3 n edge is first drwn to indicte tht i is pre-imge of stte i+. Since stte i =0 is subset of stte j =X= {0} S {}, then the sttes j nd j+ must be pre-imge nd n imge of i lso, respectively. The three edges dded in this scenrio re drwn s dshed lines in Figure 5 (b). Our overll trce compction techniue using rechbility nlysis is shown in Figure 6. Lines -7 set up the problem, build the initil grph G nd determine the initil trce length. The remining lines perform rechbility nlysis by selecting stte for preimge computtion (line 0), computing the pre-imges (line 2), nd pplying the stte continment rules (line 4). The rechbility nlysis is terminted fter ll sttes hve been selected for pre-imge computtion or fter mximum, mx, number of steps hve been performed determined by the counter. B. Creting More Short-cuts As discussed in the previous section, the continment rules re criticl for creting short-cuts in the grph G. To increse the likelihood of pplying these rules, the rechbility engine is slightly modified from its typicl UMC ppliction. Trditionlly in UMC, rechbility engines focus on finding only new sttes nd block previously visited sttes [8]. This llows them to uickly identify i (b) : G = 2: V isited = 3: counter = 0 4: for ll (sttes i between 0 to k (inclusive)) do 5: V isited.dd( i ) 6: G = dd to grph( i ) 7: end for 8: length = BFS(G, k, 0 ) 9: while (counter mx &&!V isited.empty()) do 0: j = select stte(v isited) : V isited = V isited j 2: PreImges = pre-imge( j ) 3: for ll (sttes i PreImges) do 4: pply rules 2 3(G, i, j ) 5: end for 6: V isited = V isited PreImges 7: counter = counter + 8: length = BFS(G, k, 0 ) 9: Print(Trce is of size length) 20: end while 2: return length Fig. 6. Trce compction procedure using rechbility nlysis when fixed-point is reched, or when ll legl sttes re visited [9]. In contrst, this work encourges finding previous sttes or sttes tht cover or re covered by others. These continment reltionships llow us to drw dditionl edges between nodes nd incresing the likelihood of reducing the trce. It should be noted tht precutions re tken to void repetedly visiting the sme set of sttes. A second techniue used to increse the likelihood of pplying the continment rules is to populte the grph with more sttes thn those provided in the originl trce. Since the originl trce only hs s mny sttes s its trce length, there my not be enough uniue sttes to crete mny short-cuts. We propose populting the grph initilly by computing single pre-imge for the sttes in the originl trce. This pproch llows us to uickly dd stte cubes to the grph which leds to more pplictions of the continment rules. The prcticl dvntge of this techniue is highlighted in the experiments of Section V. C. Stte Selection Procedure During rechbility nlysis, which stte is selected for pre-imge computtion determines the mnner in which the stte spce is trversed. For instnce, if the most recently visited (found) stte is lwys selected, then the stte spce is trversed in depth-first mnner. Here, we develop stte selection criteri tht help guide the rechbility engine towrds finding short-cuts from the initil stte to the finl stte. It should be noted tht these criteris re heuristics which my not lwys be dvntgeous. The first criteri is to select cndidte stte from the set of visited sttes with the smllest hmming distnce to the initil stte 0. The hmming distnce between two sttes is the number of stte vribles with different vlues (0 or ). For sttes with don t cres (X), every X mtches both the 0 nd vlue. For instnce, if sttes {00, 0, 0X, XX0} re visited nd 0 = 0000, then stte XX0 is selected since it hs hmming distnce of with respect to 0. The intuition behind the bove criteri is tht sttes with smller hmming distnce to 0 reuire less stte vribles to chnge to rech 0 s pre-imge. Therefore, the likelihood of finding 0 t the next step my be higher. A second fctor tht influences the stte selection procedure is the pth length from cndidte stte to the lst stte k. If this length is greter thn 50% of the current shortest pth from 0 to k then the stte is not considered for selection. This criteri encourges finding mny pre-imges ner the end of the trce (closer to k ) nd less closer to the initil stte. Together, both criteris increse the probbility of creting lrge short-cuts between sttes t the two ends of the originl trce.

4 D. All-Solution SAT Solver The rechbility engine is highly dependent on the performnce of the pre-imge computtion engine, which is bsed on n llsolution SAT solver. This SAT solver uses circuit don t cres to determine whether vribles my remin unssigned while stisfying the problem [0], [2]. Since the don t cres re propgted bckwrds through gte (from output to input) they re idel for preimge computtion where current stte vribles V cn be viewed s pseudo inputs to the circuit. The ll-solution SAT solver contins mny solution reduction techniues to ensure tht smll solutions re returned in n efficient mnner [8], [9], [0]. For our ppliction, chieving smll stte cubes is criticl to trversing the stte spce efficiently. Ech pre-imge computtion step corresponds to cll to the llsolution SAT solver. Since it my not be prcticl to find ll of the pre-imge sttes due to the exponentil nture of the problem, the ll-solution SAT solver is lso euipped with limit t. If ll the pre-imge stte cubes re not found in time nd memory efficient mnner, the ll-solution SAT solver will return the first t stte cubes it finds. This llows us to perform rechbility nlysis by finding prtil pre-imges. IV. STORING VISITED STATES The success of the rechbility nlysis pproch described in Section III depends on the bility to uickly pply the rules of Section III-A. More specificlly, the situtions where newly found stte i ) is eul to existing sttes, 2) is superset of existing sttes, or 3) is subset of existing sttes must be rpidly identified. In this section we introduce dt structure tht stores ll the sttes belonging to G while identifying the stte continment reltionships uickly. Note tht this dt structure is not only vible for trce compction, but cn lso be used for rechbility nlysis within UMC frmework [9], [8], []. A. Determining Stte Continment Reltionships The dt structure described here is composed of two components ) binry tree T nd 2) hsh tble. The binry tree is used to detect the stte continment reltionships, while the hsh tble is used to locte the exct stte. The stte continment reltionship depends on the number of don t cres in ech stte. A stte with more don t cres my cover one with fewer, while the converse is not true irrespective of the ctul position of the don t cres. To tke dvntge of the bove, we llocte n ordered cube for ech stte. The ordered cube is defined s the stte vlue with ll the zeros in the most significnt positions, followed by ll ones, followed by the don t cres (X) in the lest significnt positions. For exmple, five sttes nd their corresponding ordered cubes re shown below. sttes 0X 00X XX00 X00X XXX ordered cube 0X 00X 00XX 00XX XXX 3 XX00 X00X Fig X Hsh tble XXX 0X Illustrting stte storge dt structure The hsh tble contins ll sttes tht mp to the sme ordered cube. For instnce, t the node corresponding to the ordered cube 00XX in Figure 7, there cn be two uniue stte cubes XX00 nd X00X. Figure 7 illustrtes how the sttes 0X, 00X, XX00, X00X, XXX re stored in the described dt structure. Given stte i, this dt structure cn efficiently determine whether i lredy exists in G, whether i is subset of other sttes in G, nd whether i is superset of other sttes in G. For ll three tsks, first the node n i corresponding to ordered cube of i must be locted in the binry tree. If i exists in the hsh tble pointed by node n i, then i lredy exists in G. To find whether i is proper subset of other sttes, ll the nodes with t lest s mny don t cres (X) s n i hve to be visited. At ech node, the sttes within the hsh tbles must be tested to determine if i is subset. Within the tree T, the nodes with t lest s mny don t cres s n i re found inside n r+ by s+ rectngle, where r is the number of zeros nd s is the number of ones in i. Therefore, there re (r+) (s+) nodes tht cn potentilly contin supersets of i (including node n i). These nodes re illustrted in the dshed rectngle bove node n i in Figure 8. Similrly, to find whether i is proper superset of other sttes, ll the nodes with t lest s mny zeros nd ones must be visited nd the sttes within the hsh tbles must be tested to determine if i is superset. Within the tree T, these nodes re found inside n isosceles tringle with euivlent sides n r s. Therefore, there re (n r s)(n r s+) nodes tht cn potentilly be subsets of 2 i (including node n i). These nodes re illustrted in the dshed tringle under the node n i in Figure 8. As demonstrted through Figure 8, only the white nodes must be considered when serching for subsets nd supersets. Therefore, the number of comprisons reuired my be only frction of the totl number of existing sttes. In prctice, this dt structure is found to be very efficient since the tree T is often not fully populted nd the number of items in ech hsh tble is reltively smll. The procedure for finding the supersets (covers) of given stte i is presented in Figure 9. Lines 2-3 generte the ordered cube nd find its loction in the tree T. Line 4 gets ll the potentil superset When sttes re dded to the grph G, they re lso stored ccording to their ordered cube in the binry tree T. Ech node of given depth in the binry tree corresponds to position in the ordered cube. The top-most node t depth zero of the tree represents the most significnt position, the nodes t depth represent the second most significnt position, the nodes t depth 2 represent the third most significnt position, etc. The left (right) edge of node denotes zero (one) in the ordered cube t the position corresponding to the prent node. There re no edges corresponding to don t cre in the ordered cube. By scnning over the vlues of n ordered cube from the most significnt to the lest significnt, the binry tree is trversed for tht cube. Trversl ends when the ordered cube is fully scnned or when don t cre is encountered. By the end of the trversl, the finl visited node points to hsh tble where the stte vlue is stored. n-r-s Fig. 8. n i s r n-r-s Finding supersets nd subsets in the tree T

5 Fig. 9. : Covers = 2: ordered cube = Order( i ) 3: n i = Get tree node(ordered cube) 4: Supset =get rectngle(n i ) 5: for ll (nodes n j in Supset) do 6: for ll (sttes j in hsh tble of n j ) do 7: if ( j i ) then 8: Covers = Covers j 9: end if 0: end for : end for 2: return Covers Determine the sttes tht re supersets of this stte nodes by finding the nodes contined in the rectngle. The remining lines iterte through these nodes nd test the sttes inside the hsh tbles to determine whether they re supersets of i. Note tht testing whether prticulr node is superset or subset of nother is simple comprison procedure where the sttes must be identicl over ll positions except where the superset is don t cre. A procedure similr to tht of Figure 9 is used to find the subsets of i where the get rectngle procedure is replce with get tringle s described previously. V. EXPERIMENTS In this section we demonstrte the effectiveness nd efficiency of the proposed trce compction pproch. All experiments re conducted on Sun Blde 000 with 750MHz Sprc processor nd 2.5GB of memory. Trces of length 50, 00, nd 000 re obtined vi rndom simultion for the circuits in the ISCAS 89 nd ITC 99 benchmrk suites. The rechbility nlysis engine is developed using the ll-solutions SAT solver of [0] which is circuit vrint of zchff [7] nd Grsp [3]. To evlute the overll proposed pproch we limit the number of stored sttes to t most 0,000 stte cubes nd do not use n explicit timeout. Since the compction techniues of previous works [3], [4], [6] re not publicly vilble nd due to the fct tht the ssertions nd errors used re unknown, we cnnot directly or indirectly compre with them. We first evlute the effectiveness of the stte selection procedure described in Section III-C. We compre this heuristic ginst three other selection pproches, Depth-First Serch (DFS), Bredth-First Serch (BFS), nd rndom selection. The bove techniues re used to perform rechbility nlysis from rndom stte to the initil stte given timeout of 200 seconds. The runtimes over ll the benchmrks re collected nd presented in Figure 0. Both the DFS nd BFS methods result in runtimes of over 4000 seconds, while the rndom method fres better t over 3500 seconds. The proposed stte selection strtegy bsed on the smllest hmming distnce reltive to the initil stte nd the position of the stte in the grph G results in runtimes of just over 3000 seconds. This performnce demonstrtes tht the proposed stte selection heuristics is n efficient overll rechbility nlysis procedure. Runtime (s) BFS DFS rndom proposed Stte selection methods Fig. 0. Comprison of stte selection methods Next, we demonstrte the effectiveness of the overll proposed trce compction pproch. Tble I illustrtes the results of the experiments on ll ISCAS 89 nd ITC 99 circuits for trces of length 50, 00 nd 000. The first column shows the circuit nmes while the remining columns re orgnized into three sections bsed on their originl trce length. The first column of ech section lbeled org describes the originl length of ech trce (50, 00, or 000). The second column of ech section lbeled pre describes the length of the trces fter performing the single step pre-imge process described in Section III-B. We chose to find single step pre-imges for no more thn 50 sttes to chieve blnce between the number of preimges found nd the time reuired to find them. The third column of ech section lbeled rech, presents the length of the trces fter pplying the proposed rechbility nlysis method. As described in section III-B, it is most beneficil to first find the single step preimges followed by the rechbility nlysis (rech) method. The fourth nd fifth columns of ech section, lbeled cpu pre nd cpu rech respectively, present the runtimes in seconds ssocited to the pre nd rech techniues. Tble I shows tht the pre-imge computtion techniues help reduce the trces considerbly. For mny circuits, the originl trce length is first reduced gretly by the single step pre-imge (pre) techniue nd further reduced by the rechbility nlysis (rech). For exmple, the trce for circuit s344 is first reduced from 50 to 33 using pre, nd then gin from 33 to using rech. Anlyzing the results of Tble I, we notice tht mny trces re reduced to hving single clock cycle (length of ) or very smll trce size fter pplying rechbility nlysis. This result cn be prtilly ttributed to the stte selection heuristics of Section III-C nd the performnce improvement techniues of Section III-B. These techniues cn increse the number of short-cuts creted through the grph G nd likelihood tht they will led to the initil stte. Tble II summrizes the results in Tble I by providing the verge length compctions (reductions) chieved by the different components of the proposed pproch for trces of size 50, 00, nd 000. Similr to Tble I, the summries re provided for ech originl trce length seprtely. Column one presents the nme of the compction method: single step pre-imge computtion (pre), rechbility nlysis (rech), or combined. For ech trce length, the overll verge reduction is presented under the lbel vg. reduced. This field is clculted by dding the reduction in size over ll circuits divided over the number of circuits. Since not ll circuit trces re reduced by the proposed method, this number my not provide good representtion of the verge fctor of reduction chieved. Insted, the columns lbeled ffected nd reduced show the percentge of trces tht re ffected by ech pproch nd the mount by which they re reduced, respectively. For exmple, for trces of length 50, the proposed pproches seprtely chieve 0.08 times nd 3.8 times reductions while the combined pproch reches 9.67 times reductions. Furthermore, pproximtely 70% of the circuits re ffected by the pre techniues which results in n verge reduction of 3.77 times. Similrly, the rech techniue nd the combined pproch ffect 37% nd 74% of trces for reduction of 8.45 times nd times, respectively. The experimentl results demonstrte tht not only is the proposed pproch effective for reducing trces, but it is lso very efficient. For the mjority of circuits in Tble I, compcted trces re found within few minutes. This performnce reffirms the prcticlity of the dt structure introduced in Section IV. The memory reuirements of the overll pproch re lso mngeble since memory usge never exceeds 300MB when storing up to 0,000 stte cubes. The bility to uickly reduce trces in memory efficient mnner is crucil for mking this pproch vible in rel-life debugging environments. VI. CONCLUSION This work proposed novel trce reduction techniue using SATbsed rechbility nlysis nd set of stte continment reltionships. The components of the rechbility nlysis engine re finetuned to increse the likelihood of generting short-cuts in the originl

6 circuits org pre rech cpu pre cpu rech org pre rech cpu pre cpu rech org pre rech cpu pre cpu rech s s s s s s s s s s s s526n s s s s s s s s s s s s s s s s s s s b b b b b b b b b b b b b b TABLE I EXPERIMENTAL RESULTS FOR THE PROPOSED TRACE LENGTH COMPACTION APPROACH FOR TRACES OF LENGTH 50, 00 AND 000. orginl size 50 orginl size 00 orginl size 000 pproch vg. reduced ffected reduced vg. reduced ffected reduced vg. reduced ffected reduced pre 0.08 X 70 % 3.77 X 6.88 X 72 % X X 7 % X rech 3.8 X 37 % 8.54 X 6.0 X 35 % 5.36 X 2.77 X 5 % 2.40 X combined 9.67 X 74 % X 36.2 X 72 % 49.0 X X 72 % X TABLE II SUMMARY OF THE RESULTS FOR THE PROPOSED TRACE LENGTH COMPACTION APPROACH trce. Furthermore, novel dt structure is presented which stores visited sttes such tht the stte continment reltionships cn be uickly pplied. Experiments demonstrte the effectiveness of the proposed techniues s pproximtely 75% of the trces re reduced by one or two orders of mgnitude. REFERENCES [] P. Rshinkr, P. Pterson, nd L. Singh, System-on--chip Verifiction: Methodology nd Techniues. Kluwer Acdemic Publisher, 996. [2] T. Kropf, Introduction to Forml Hrdwre Verifiction. Springer, 999. [3] Y. Chen nd F. Chen, Algorithms for compcting error trces, in ASP Design Automtion Conf., 2003, pp [4] S. Shen, Y. Qin, nd S. Li, A fster counterexmple minimiztion lgorithm bsed on refuttion nlysis, in Design, Automtion nd Test in Europe, 2005, pp [5] K. Chng, V. Bertcco, nd I. Mrkov, Simultion-bsed bug trce minimiztion with BMC-bsed refinement, in Int l Conf. on CAD, 2005, pp [6] S.-J. Pn, K.-T. Cheng, J. Moondnos, nd Z. Hnn, Genertion of shorter seuences for high resolution error dignosis using seuentil st, in ASP Design Automtion Conf., 2006, pp [7] J. Mrues-Silv nd K. Skllh, GRASP new serch lgorithm for stisfibility, in Int l Conf. on CAD, 996, pp [8] K. McMilln, Applying SAT methods in unbounded symbolic model checking. in Computer Aided Verifiction, 2002, pp [9] H.-J. Kng nd I.-C. Prk, SAT-bsed unbounded symbolic model checking, IEEE Trns. on CAD, vol. 24, no. 2, pp , [0] S. Sfrpour, A. Veneris, nd R. Drechsler, Integrting observbility don t cres in ll-solution SAT solvers, in IEEE Interntionl Symposium on Circuits nd Systems, 2006, pp [] B. Li, M. Hsio, nd S. Sheng, A novel SAT ll-solutions solver for efficient preimge computtion, in Design, Automtion nd Test in Europe, 2004, pp [2] Q. Zhu, N. Kitchen, A. Kuehlmnn, nd A. Sngiovnni-Vincentelli, St sweeping with locl observbility don t-cres, in Design Automtion Conf., 2006, pp [3] M. Moskewicz, C. Mdign, Y. Zho, L. Zhng, nd S. Mlik, Chff: Engineering n efficient SAT solver, in Design Automtion Conf., 200, pp