THE frequent use of transcendental functions in

Transcription

1 1959 PROCEEDINGS OF THE WESTERN JOINT COMPUTER CONFERENCE 103 Automatic Design of Logical Networks* T. C.BARTEEt THE frequent use of transcendental functions in digital computer programs has presented a basic problem in the design of real-time control systems. Since there are usually no single instructions to perform such functions as sine x, arc sine x, etc., two other techniques have been used. The first technique involves storing a table of values for the function in rapid access memory. The advantage of this technique lies in the speed obtainable; however, in order to provide reasonable accuracy, the table must be of considerable length. Computations which involve physical measurements such as those made by one of the newer radars would require a table which would occupy a 'significant portion of most storage devices. An alternate technique involves storing a smaller table, and then interpolating between the values stored in this table. The principal advantage of table ~torage is then lessened, for the interpolation routine requires time and the function can no longer be generated as quickly. The second technique involves the use of a programmed approximation routine. Most of the routines used are based on polynomial approximations which require several multiplications, and as a consequence, are time-consuming. The utilization of digital computers in real-time control systems which must process large amounts of data at high speeds has made the problem more acute. Most programs for such systems require values for sines, cosines, etc., quite often, and the necessary computations must be made quickly and with considerable accuracy. The need therefore exists for a very fast and accurate method of generating trigonometric functions. Lincoln Laboratory has recently prepared a set of flexible computer programs which automatically perform the design of logical networks which will perform such functions in a single step. These networks may then be connected into the arithmetic element of an internal-binary-operation digital computer, providing the machine with instructions which will yield the sine, arc sine, etc., of an angle stored in one of the registers of the arithmetic element. The design technique yields a logical network with a number of input and output lines, the input lines representing the independent variable and the output lines the dependent variable. The networks are completely digital in operation, utilizing highspeed transistor and diode logical circuitry. Because of the magnitude of the design problem for large logical networks, conventional manual design tech- * The work reported here was performed at Lincoln Lab., Mass. Inst. Tech., Lexington, Mass., with the joint support of the Army, Navy, and Air Force. t Lincoln Lab., M.LT., Lexington, Mass. niques could not be used. For instance, the complete set of expressions needed to describe a 12-input bit and 14- output bit sine network in developed normal form contains approximately 90,000 symbols. Normal design techniques involving manual calculations would prohibit either the generation or simplification of a set of expressions of this complexity. It was necessary, therefore, to design and prepare a set of digital computer programs which would automatically generate the desired set of expressions, simplify them, and then check the simplified equations. The series of programs written are general purpose in design and may be used to generate and simplify the logical equations describing any function with a unique value of the dependent variable for each value of the independent variable. Only three basic logical relationships or operators are used in the equations. These are defined as logical addition, logical multiplication, and complementation. Fig. 1 illustrates a standard diode circuit for the logical addition relationship. The inputs to this diode "or" circuit consist of dc levels of - 5 and + 5 volts corresponding to the logical symbols 0 and 1, respectively. To the left of the figure is the block diagram symbol for the "or" circui t. The plus sign in the block is also used to indicate logical addition in the written expressions. This is, of course, the "inclusive or" function, sometimes referred to as "logical disjunction." Fig. 2 illustrates a diode "and" circuit which performs the logical multiplication function, sometimes referred to as "logical conjunction." The block diagram symbol for the "and" operation is to the left of this figure. Fig. 3 illustrates a two-level diode "and-to-or" circuit. There are six inputs to this circuit, each consisting of dc levels. The expression describing this circuit in Boolean algebra notation is written at the far right of the figure. This expression may be read a and band c, or d and e and f or the product of a, band c, plus the product of d, e and f. According to the notation used, the output will be equal to 1 only when a and band c or d and e and fare equal to 1. The third logical operation used is the complement function, sometimes referred to as inversion or negation. A transistor inverter designed for the Lincoln TX-2 computer is illustrated in Fig. 4. A prime sign (') is used to indicate the" complement" or "not" function in the expressions. When flip-flops are used to provide the inputs to the networks, complemented as well as the uncomplemented values of the input variables are available. At a given time each input line to a logical network will contain a signal representative of either a binary 0 or 1. The fundamental characteristic of the logical net-

2 PROCEEDINGS OF THE WESTERN JOINT COMPUTER CONFERENCE -30 VOLTS +30v. :~z INPUT OUTPUT INPUT OUTPUT x y z x y z V-5V - 5V V+5V + 5V V-5V + 5V 4 i i +5V+5V + 5V Fig. i-the "or" circuit. a b c d e -30 v. a b c d e f Fig. 3-Two-level "and-or" circuit. abc + def +30 V +10V x y Z ~--<>Z X <>--II1II1--.. yo INPUTS OUTPUTS X Y z X -D-x ' X t---<>,x V -5V -5V o 1 0-5V+5V -5V V -5V -5V V +5V +5V Fig. 2-Diode "and" circuit. ~XI o X Xl -3V OV OV, -3V Fig. 4-Transistor inverter. work is that for each combination of input values there will be a unique output value, represented by signals on the output lines. Since the output from a logical network of this sort is determined by the inputs to the logical network, it is possible to construct a logical network that will perform any function having the characteristic that for each state which the inputs assume, there will be a unique output. It may be seen that this, does not limit the function performed to transcendental or straightforward mathematical relationships, but allows any input-to-output relationship. When a logical network contains several input and output lines, it is possible to simplify the design problem by considering only one output line at a time. The signal on this particular line is determined by the values of the inputs to the logical network at that time, and may be specified by means of a Boolean function of the input variables. This expression will be equal to 1 when the output from this particular line of the network is 1 and to 0 when the output is O. An expression that represents the operation of a single line of a logical network is called the transmission function for that line of the network. A fully developed transmission function, when written in the sum-of-products form, consists of a num- ber of terms, each of which is a product of all of the input variables, certain of which may be complemented. This type of expression is referred to as a canonical expansion for the circuit transmission. The first step in the design procedure for a network with several input and output lines consists of deriving the canonical expansion for each output line of the network. Table I shows the derivation of the canonical expansion for the transmission function for one output line bit of a small network which will yield the sine of x within the limits 0 to 90. The leftmost column of the table lists the angle x in degrees, starting with 0 and increasing by increments of 6 to 90. The next column contains the same set of angles coded as binary numbers, starting with 0000 and increasing to 1111 by steps of 0001, which increases the angle by 6 in each case. The values of sine x, expressed in binary form, are listed in the next column of the table. To the right of the column representing the sine values is a column listing the Boolean symbols for the input variables in productterm form. The variables are primed or unprimed depending on whether or not the respective input value is o or 1. The computer program generates the sine value for each input angle and then, examining one bit of the

3 Bartee: Automatic Design of Logical Networks los x (degrees) TABLE I CANONICAL EXPANSION FOR SIN X FROM 0 TO 90 x Sin x (binary form) (binary form) a b c d (1) (2) (3) (4) Product Terms a ' b' c' d ' a' b' c d ' a ' b' c d a ' b c' d' a ' b c' d a b c d - T(2) =a'b'cd+a'bc'd' +ab'c'd+ab'cd' +ab'cd+abc'd' +abc'd ( +abcd I +abcd The first step of the minimization procedure consists of matching each term of the canonical expansion with each of the other terms, and if the terms differ.in only one variable, eliminating that variable. T-his matching procedure actually consists of the repeated. application of the theorem (c/)(x+c/>a'=c/». Table II illustrates the first step of this matching procedure, using the product terms which comprise the expression developed in Table I. It is important that a given term be matched with all of the other terms and not dropped after the first match. For instance, abc'd' in Table II must be matched with both abc'd and abed'. After the first set of matches, the resulting terms will each have one yariable less than the original set of terms. Since, in Table I I, the first set of terms consists of four variables each, the next col- TABLE II DERIVATION OF PRIME IMPLICANTS Theorem ( a+ a' = ) a ' b ' c d - b' c d a' b c' d ' - b c' d ' a b' c ' d a b' - d a - - d a b' c d ' a - c' d a - c - a b' c d a b' c - a b - - a b c' d ' a - c d ' a b c' d a - c d a b c d ' a b c' - a b c.d a b - d ' a b - d a b c sine values at a time, develops and stores the canonical expansion for each output line of the logical network. In effect, the computer proceeds down a column of output values until it finds a 1. It then stores the input values which generated the 1 output in the output table. Table I illustrates the derivation of the product terms for the second bit of the four output bits. Each 1 in the second-output-bit column is underlined, as is the product term for this particular output. The complete canonical expansion for the output line representing the second least significant output bit of this particular table is illustrated at the bottom of the figure. An expression is therefore generated for each output line of the logical network. The minimization technique which has been programmed is based on work done by Quine1.2 of Harvard, and by McClusky 3 during the preparation of his doctoral dissertation at M.I.T. The input to this particular program is the canonical expansion developed by the preceding program, and the output is a minimized equivalent sum-of-products expression. 1 W. V. Quine, "The problem of simplifying truth functions," Amer. Math. Monthly, vol. 59, pp ; W. V. Quine, "A way to simplify truth functions," Amer. Math. Monthly, vol. 62, pp ; E. J. McCluskey, Jr., "Minimization of Boolean functions," Bell Sys. Tech. J., vol. 35, pp ; umn, containing the shortened terms, will consist of terms of three variables. In Table II the missing variables are indicated by dashes. If any term of the expression does not match with any other te~m, it is then a "prime implicant" term and will be a term of the final prime implicant expression. After the original terms have all been compared, a second set of terms., each one variable shorter than the original terms, will have been derived. These terms are then matched with each other, using the same theorem c/>a + c/>a' = c/>. If the remaining variables are maintained in their original positions in the terms, and the eliminated variables indicated by means of a dash, as in Table II, the matching process may be made somewhat simpler to perform. In this case the terms are matched on the following basis: first, the dashes indicating the missing variable or variables must be in the same position (that is, ab-d' and ab-d may be matched but there is no possibility of matching a-cd with ab-d) and second, the remaining variables must all be identical save one (that is, ab-d' can be matched with ab-d, yielding ab--). This process is continued until no further matches can be made. Third and further cycles of this process are continued, using the same rules, un til a single pass through a cycle yields no matches. The remaining terms plus all the

4 PROCEEDINGS OF THE WESTERN JOINT COMPUTER CONFERENCE terms that did not match during the process comprise the prime implicants. The right half of Table II illustrates how the above matching process is performed in the computer. The terms of the original expression are stored in binary form, using positional notation to maintain the identity of the variables. A 1 is used to indicate an unprimed variable and a 0 to indicate a primed variable, so that ab' cd is expressed as Since variables will be eliminated in this process, it is convenient to utilize another register of computer storage as a mask, and to alter the mask as variables are eliminated, while maintaining the variables in order. Each term is therefore represented by two registers, one containing the "values" of the variables and another the mask for the term. The mask is altered to indicate the eliminated variables. For instance, if two terms 1011 and 1010 and their masks are matched, the resulting term is 101- or ab' c. The first step in the matching process in the computer, therefore, is to compare the masks to see if they are identical. If the masks are identical, the terms are then matched and if they differ in only one variable, a new term is formed along with a new mask which indicates the missing variable or variables. In order to shorten the matching problem, McCluskey has shown that the terms may first be sorted according to the number of 1 's in each term. Table III illustrates the same set of terms after they have been sorted and arranged in tabular form. Each section of a column of the table contains terms with one more 1 than the terms in the preceding section of the table. I t is necessary to match only the terms from one section of the table with the terms in the preceding and following sections of the table, for two terms which differ by more than one 1 cannot match: 1011 cannot match with any term containing only one 1, for instance 1000, for the two terms must, of necessity, vary in more than one variable. Further, if the terms from one section of the table are matched with those of the next section, the resulting shortened terms can be matched only with shortened terms formed by matches in the preceding and following sections of the table. This technique significantly reduces the number of matches which must be made and also materially lessens the amount of fast-access memory that is required at a given time. The number of terms formed by the matching process tends to increase considerably for large problems before finally decreasing. By storing only the sections of the table which are being matched in high-speed memory, and storing the rest of the terms on tape or drums, large problems may be handled more easily. The set of terms derived in this manner, if collected in sum-of-products form, will form an expression equivalent to the original expression. An important characteristic of these terms is that none of them can be shortened by omitting a variable. Quine has shown that the shortest sum-of-products expression must consist of a subset of these terms. It may be shown that certain TABLE III ORDERED DERIVATION OF PRIME IMPLICANTS ' Prime Implicants= ( ) or (be'd' +b'ed+ad+ae+ab) b --M e' --i *~ d'-i+--' b'--! e--t f-t <> d ' a --t e a --i , d --i Fig. 5-Two-level diode circuit. be'd'+ b'ed + a e + ad of these terms are common to every possible minimal subset, while the remaining terms of each subset may be chosen, subject to a set of constraints. The computer program has been designed to print automatically those prime implicant terms common to every minimum expression. The computer then prints a table of the remaining prime implicant terms along with the necessary constraint information. Choice of the remaining terms in the final expression is made from the table. This final choice has been left separate from the computer programs to permit flexibility in the design of the circuitry. Fig. 5 illustrates a two-level diode circuit which performs the function developed in Table I. Fourteen diodes are required to construct this particular network. Since the original canonical expansion would have required 45 diodes, 31 diodes were saved by the minimization process. The entire process was programmed for the Whirlwind computer located at the Massachusetts Institute of Technology. 'This is a general-purpose, stored-program computer with a word length of 16 bits. The entire set

5 Kalman and Koepcke: Digital Computers in the Optimization of Chemical Reactions 107 of programs are slightly over 3000 orders in length. The program requires about 40 seconds to generate the canonical expansion for each output line of a 12 inputline by 14 output-line problem and from eight to ten minutes to minimize and print the final expression. About 25,000 registers are required to store partial results during the processing. As a result, drum storage is used during the minimization procedure. The procedure is now being programmed for an IBM 709 located at the laboratory, making possible the solution of larger problems and somewhat shortening the programs' running time due to the large core storage of the 709. The design procedure described here appears very flexible. It can be used to perform automatically the logical design of circuitry which will perform any function which has a unique value of the dependent variable for each value of the independent variable. To date, networks which yield sine, arc sine, and the square root of the input value have been constructed. The concept of programmed logic as an aid to computer design appears quite attractive for the design of future machines. ACKNOWLEDGMENT The computer programs described in this report were written by H. C. Peterson who has also contributed many helpful suggestions. The original problem of designing computer instructions which would yield transcendental operations arose during Lincoln Laboratories' ballistic missile early warning system studies and was suggested to the author by W. I. Wells. The author also wishes to thank V. A. Nedzel, R. W. Sittler, and J. F. Nolan for their helpful comments during the writing of this report. The Role of Digital Computers in the Dynamic Optimization of Chemical Reactions R. E. KALMANt AND R. W. KOEPCKEt I. INTRODUCTION ALONG with the increasing availability of high.fi speed, large-storage digital computers, there has been growing interest in their utilization for realtime control purposes. A typical problem in this connection and one of long-standing interest is the optimal static and dynamic operation of chemical reactors. 1,2 To our knowledge, no digital computer is being used for this purpose, chiefly because of the many difficulties encountered in utilizing real-time machine computation in reactor control. These difficulties range from the unavailability or inadequacy of hardware (i.e., transduoers, measuring instruments, low-level analog-to-digital converters, etc.) to the lack of a well-established body of fundamental theoretical principles. Although a great deal is known about the basic concepts governing control systems,3,4 present methods cannot be readily applied to designing a program for a real-time digital cont Res. Inst. for Advanced Study, Baltimore 12, Md. t IBM Res. Center, Yorktown Heights, N. Y. 1 T. J. Williams, "Chemical kinetics and the dynamics of chemical reactors," Control Engrg., pp ; July, R. Aris and N. R. Amundson, "An analysis of chemical reactor stability and control," Chem. Engrg. Sci., vol. 7, pp ; J. G. Trux;al, "Automatic Feedback Control System Synthesis," McGraw-Hill Book Co., Inc., New York, N. Y.; J. R. Ragazzini and G. Franklin, "Sampled-Data Systems," McGraw-Hill Book Co., Inc., New York, N. Y.; trol computer. This is because the existing design methods are applicable primarily to fairly small-scale systems, whereas the use of a digital computer (in fact the very attractiveness of computer control) arises primarily in connection with large-scale problems. The role of the digital computer in real-time control consists essentially of "digesting" large amounts of information obtained from the primary measuring instruments and then calculating, as rapidly as possible, the con trol action to be taken on the basis of these measurements. One purpose of this report is to provide a broad outline of a new approach to designing control systems for chemical processes which are to be built around a fast, general-purpose digital computer operating in real time. The specific engineering details of the computer will not be of any interest here; rather, we have concentrated on studying the types of computations the computer is to perform. To lend concreteness to the discussion, the chemical process under consideration will be a continuous-flow, stirred reactor. After the fundamental concepts have been established, the detailed analytic equations (in the linear case) leading to the dynamically optimal (and thus also statically optimal) design of the reaction control system are given in Section III. The equations of Section III represent a'special case of the new design theory of linear control systems formulated