Towards High-Level Specification & Synthesis of Dynamic Process Logic

Transcription

1 Towrds High-Level Specifiction & Synthesis of Dynmic Process Logic Oliver Diessel Usm Mlik Keith So George Milne School of Computer Science nd Engineering, The University of New South Wles, Austrli School of Computer Science & Softwre Engineering, The University of Western Austrli, Austrli

2 Overview Gols & chllenges of dynmic reconfigurtion Forml modelling of dynmic reconfigurtion A Circl primer FPGA implementtion of Circl An FPGA interpreter for Circl Ongoing work Conclusion

3 Architecturl reconfigurtion Definition:The bility of device or system rchitecture to chnge its structure over time Which structurl spects? Wht time scle? How controlled? NB: some structurl chnges my result in behviourl chnges

4 Dynmic reconfigurtion Aims to exploit rchitecturl reconfigurtion t run time in order to: Adpt to chnging lgorithmic needs s computtion progresses Improve ppliction/system performnce Reuse computtionl resources

5 Dynmic reconfigurtion Fcilittes nd supports Adptive processes Dynmic environments Hrdwre independence Multitsking

6 Reconfigurble computing chllenges How to design efficient, cost-effective rchitecturl mixes t device nd system level How to exploit operting niche How to support systems nd ppliction design Killer pps: finding ppel nd cceptnce

7 The design chllenge Designing with short led-times for short-lived, highlycustomized pplictions Skill bse needs to spn mny lyers nd dimensions of bstrction: from logic circuit to ppliction lyer E.g. conceiving high-performnce hrd-wired lgorithms Lck of integrted tools tht exploit hrdwre cpbilities

8 Forml modelling of dynmic reconfigurtion

9 Gol of project: Bsic lnguge reserch Discover semntic opertors needed to model sttic nd dynmic FPGA circuits Lern how to compile down to those opertors how much cn be utomted? Determine wht spects need to be expressed explicitly in the design lnguge in order to guide the compiler

10 Not nother lnguge The gol is NOT to design yet nother lnguge for reconfigurble computing. Rther, the gol is to identify the key requirements of such lnguge nd its compiler.

11 Our pproch Investigte the problem from forml modelling perspective we use process lgebr clled Circl to model circuits, their structure nd behviour

12 How cn Circl help? Circl provides mens of describing concurrent systems in n uncluttered, bstrct fshion Fcilittes discovery of fundmentl opertions, semntics, syntx Circl offers the possibility of producing circuits nd trnsltion schemes tht re verifibly correct (equivlent to their specifiction) Hope to mke use of forml methods literture

13 Circl bckground

14 Circl bckground Process lgebrs such s CCS, CSP, nd Circl (CIRcuit CALculus) ppered mid- to lte-1970s Mthemticl formlisms for describing & nlyzing the behviour of concurrent systems Allow behviourl specifiction, property checking, equivlence checking, forml verifiction

15 Allows us to reson bout processes tht hve stte, nd tht perform or respond to ctions Wht is Circl?

16 Wht is Circl? Allows us to reson bout processes tht hve stte, nd tht perform or respond to ctions For exmple, we might model chnge mchine using stte digrm Dollr CM 1 CM 2 CM 5 4Qtrs empty CM 3 CM 4

17 Modelling the user Dollr We my be interested to know: U 1 4Qtrs U 2 Wht is the composed behviour of the csh mchine nd the user? empty U 3 empty U 4 nger U 5 Will the user ever get ngry? PAs define the rules tht llow these nd other questions to be nswered

18 Circl bsics c P S b S U d c c Q P V b Q d d The Circl process lgebr supports hierrchicl, modulr, nd constructive description of intercting processes Processes re behviourl objects tht interct bsed on the occurrence of events b

19 Behviourl modelling in Circl Behviourl opertors

20 Behviourl modelling in Circl P 0 Behviourl opertors Process definition P P 0

21 Behviourl modelling in Circl P 0 Behviourl opertors Process definition Process termintion P P 0 P 0 Δ

22 Behviourl modelling in Circl P 0 P 1 Behviourl opertors Process definition Process termintion Process evolution P P 0 P 0 P 1

23 Behviourl modelling in Circl ( b) P 0 c P 1 Behviourl opertors Process definition Process termintion Process evolution Deterministic choice P P 0 P 0 P 1 + c P 1 + ( b) P 1 P 1 P 0

24 Structurl modelling in Circl ( b) c P 0 P 1 d Q 0 Q 1 b Structurl opertors Composition

25 Structurl modelling in Circl S P 0 Q 0 P 0 ( b) c P 1 Q 0 d b Q 1 Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0

26 Structurl modelling in Circl S P 0 Q 0 P 0 ( b) c P 1 Q 0 d b Q 1 Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 Q 0 c P 1 Q 0 P 0 xq 0 c P 1 xq 0

27 Structurl modelling in Circl S P 0 Q 0 P 0 ( b) c P 1 Q 0 d b Q 1 Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 Q 0 c P 1 Q 0 P 1 Q 0 P 0 Q 1 P 0 xq c 0 P 1 xq 0 P 0 xq 1

28 Structurl modelling in Circl ( b) P 0 c P 1 Q 0 d b Q 1 S P 0 Q 0 P 0 Q 0 c P 1 Q 0 P 1 Q 0 P 0 Q 1 P 0 Q 1 c P 1 Q 1 Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 P 1 xq 1 c P 0 xq 1 c P 1 xq 0

29 Structurl modelling in Circl c P 0 P 1 d Q 0 Q 1 b S P 0 Q 0 P 0 Q 0 c P 1 Q 0 + d P 0 Q 1 + P 1 Q 1 + (c d) P 1 Q 1 P 1 Q 0 P 0 Q 1 + d P 1 Q 1 P 0 Q 1 c P 1 Q 1 P 1 Q 1 Δ ( b) Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 d (c d) P 1 xq 1 c P 0 xq 1 c d P 1 xq 0

30 Structurl modelling in Circl c P 0 P 1 d Q 0 Q 1 b S P 0 Q 0 P 0 Q 0 c P 1 Q 0 + d P 0 Q 1 + P 1 Q 1 + (c d) P 1 Q 1 P 1 Q 0 P 0 Q 1 + d P 1 Q 1 P 0 Q 1 c P 1 Q 1 P 1 Q 1 Δ ( b) Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 d (c d) P 1 xq 1 c P 0 xq 1 c d P 1 xq 0

31 Structurl modelling in Circl c P 0 P 1 d Q 0 Q 1 b S P 0 Q 0 P 0 Q 0 c P 1 Q 0 + d P 0 Q 1 + P 1 Q 1 + (c d) P 1 Q 1 P 1 Q 0 P 0 Q 1 + d P 1 Q 1 P 0 Q 1 c P 1 Q 1 P 1 Q 1 Δ ( b) Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 d (c d) P 1 xq 1 c P 0 xq 1 c d P 1 xq 0

32 Structurl modelling in Circl c P 0 P 1 d Q 0 Q 1 b S P 0 Q 0 P 0 Q 0 c P 1 Q 0 + d P 0 Q 1 + P 1 Q 1 + (c d) P 1 Q 1 P 1 Q 0 P 0 Q 1 + d P 1 Q 1 P 0 Q 1 c P 1 Q 1 P 1 Q 1 Δ ( b) Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 d (c d) P 1 xq 1 c P 0 xq 1 c d P 1 xq 0

33 Structurl modelling in Circl c P 0 P 1 d Q 0 Q 1 b S P 0 Q 0 P 0 Q 0 c P 1 Q 0 + d P 0 Q 1 + P 1 Q 1 + (c d) P 1 Q 1 P 1 Q 0 P 0 Q 1 + d P 1 Q 1 ( b) Structurl opertors Composition Evolve on shred events only when ech is independently ble to P 0 xq 0 (c d) P 1 xq 1 c c d P 1 xq 0 P 0 Q 1 c P 1 Q 1 P 1 Q 1 Δ (DEADLOCK) d P 0 xq 1

34 Structurl modelling in Circl i Q o i Q o Structurl opertors Composition Relbelling Similr to prmeteriztion Supports reuse

35 Structurl modelling in Circl i Q o i Q o Structurl opertors Composition Relbelling Similr to prmeteriztion Supports reuse S Q [c/o] Q [c/i] i Q Q o c

36 Structurl modelling in Circl b c ( b) P 0 c P 1 P P 0 P 0 P 1 + c P 1 + ( b) P 1 P 1 P 0 Structurl opertors Composition Relbelling Abstrction Hides events from observer

37 Structurl modelling in Circl b c b P 0 c P 1 P P 0 P 0 P 1 & c P 1 & b P 1 P 1 P 0 Structurl opertors Composition Relbelling Abstrction Hides events from observer Introduces nondeterministic behviour Limited use in HW description

38 Wht Circl hs been used for Modelling & verifying digitl (CMOS) circuits nd synchronous (micropipeline) systems Verifying the timing, performnce, nd correctness of concurrent systems Describing complex systems such s trffic networks using CA frmework

39 Circl s specifiction lnguge Success with using Circl for digitl design & verifiction led us to wonder: Is Circl suitble s the bsis of specifiction lnguge for FPGAs?

40 Question hs led to work on Mpping Circl specifictions to RL Automtic support for virtulized circuit designs Modelling DRL using PA formlism Determining wht tht provides us with

41 FPGA implementtion of Circl

42 Mpping gols Quick nd esy instntition of circuits Distribute computtion for sclbility Speedup through concurrent execution Use dynmic reconfigurtion to overcome resource limittions Provide scope for implementing dynmic specifictions

43 Circuit reliztion of Circl events P Q Z Process logic blocks request signls r s synch signl At the system level, Circl specifiction is relized s n interconnection of independent, concurrently ctive process logic blocks nd synchronistion logic

44 Circuit reliztion of Circl (cont) event bus select stte trnsition enble stte trnsition process stte events in process sort request signl r synch signl s Ech process logic block implements the behviour specified by its process definitions Of course the Circl composition lw constrins process stte trnsitions to those tht re globlly cceptble stte feedbck

45 Circuit ctivtion event bus select stte trnsition events in process sort request signl r Processes respond to input events ech cycle Stte renewl consists of three phses: enble stte trnsition process stte synch signl s stte feedbck

46 Circuit ctivtion (cont) event bus select stte trnsition enble stte trnsition process stte events in process sort request signl r synch signl s Processes respond to input events ech cycle Stte renewl consists of three phses: 1. Ech process checks whether the event is cceptble to itself stte feedbck

47 Circuit ctivtion (cont) event bus select stte trnsition enble stte trnsition process stte events in process sort request signl r synch signl s Processes respond to input events ech cycle Stte renewl consists of three phses: 1. Ech process checks whether the event is cceptble to itself nd rises synchroniztion request signl if it is; stte feedbck

48 Circuit ctivtion (cont) event bus select stte trnsition enble stte trnsition process stte events in process sort request signl r synch signl s 3 phse stte renewl: 1. Check event cceptbility; 2. Synchroniztion logic sserts synchroniztion signl if ll processes find the event cceptble; nd stte feedbck

49 Circuit ctivtion (cont) event bus select stte trnsition enble stte trnsition process stte events in process sort request signl r synch signl s 3 phse stte renewl: 1. Check event cceptbility; 2. Synchroniztion signl sserted; nd 3. Ech process enbles the stte trnsition gurded by the input event if synchroniztion is sserted. stte feedbck

50 Circuit ctivtion (cont) event bus select stte trnsition enble stte trnsition process stte stte feedbck events in process sort request signl r synch signl s 3 phse stte renewl: 1. Check event cceptbility; 2. Synchroniztion signl sserted; nd 3. Ech process enbles the stte trnsition gurded by the input event if synchroniztion is sserted. Stte is updted t the next clock edge

51 Design exmple Consider P P 0 P1 + ( b) 1 P 0 P 1 + cp 1 nd Q Q 0 1 Q bq dq 1 P 0 P 1, ( b), c, d Q 0 Q 1 Applying the Circl composition lw we get b P P P P Q Q Q Q P1 Q P0 Q cp1 Q Δ dp 1 Q Q cp1 0 ( cd ) 1 + P 1 Q 1 + dp 0 Q 1

52 Stte renewl phse 1: Determining whether n event combintion is vlid Consider just the logic for process P: P P1 In stte P 0 the process responds to events in the set P 1 + ( b ) P 0 P 1 + cp { b c,bc,b c,b c}. 1 Hence process P in stte P 0 ccepts the boolen expression of events ( bc + bc + bc + bc). Similrly, in stte P 1, the process ccepts ( bc + bc). The synchroniztion request signl cn thus be expressed s... r P = ( bc + bc + bc + bc ). P0 + ( bc + bc ). P1.

53 Stte renewl phse 2: Checking globl cceptbility of n event Done by forming the globl conjunction of process synchroniztion request signls: s = i r i

54 Stte renewl phse 3: Allowing stte trnsitions Let DP 0 nd DP 1 denote the boolen input functions for the P 0 nd P 1 stte flip-flops Then from P P 0 P1 + ( b) 1 P 0 P 1 + cp 1 we cn derive D D P P 0 1 = s.( bc. P1 = s.([ bc + + bc. P0 ) + s. P0 bc + bc]. P + 0 bc. P 1 ) + s. P 1

55 Schemtic for P*Q

56 Automtic plce & route of flt design

57 Module Genertors 1. Environmentl Inputs: EI(tlc, tlr, ni, or, ob); - consists of input register nd wires to right nd bottom - specified by coords of top left corner, number of inputs, nd vector of wires to right & bottom

58 Module Genertors 2. Buses: B(tlc, tlr, wi, hi, or, w); - specified by coords of top left corner, width nd height, orienttion, nd vector of ctive wires

59 Module Genertors 3. Input Junctions: IJ(tlc, tlr, wi, or, ob); - llows nother process to be dded - specified by coords of top left corner, width, nd vector of outputs to right nd bottom

60 Module Genertors 4. Minterms: M(tlc, tlr, ni, mn); - computes minterm, psses input to right nd output to bottom - specified by coords of top left corner, number of inputs, nd minterm number

61 - specified by coords of top left corner, width, nd vectors of ctive inputs, inputs to be ORed, nd inputs to be output below Module Genertors 5. Gurds: G(tlc, tlr, wi, i, g, o); - forms OR of selected minterm wires with output to right

62 - specified top left corner, height, nd vectors of throughputs ( ), stte selectors ( ), nd requestors Module Genertors 6. Requestors: R(tlc, tlr, hi, tp, ss, r); - combine gurds with current stte nd pss signls through their body

63 - specified by coords of top left corner, height, ctive input vector, nd output direction flg Module Genertors 7. OR gte trees: OR(tlc, tlr, hi, i, of); - forms tree to right nd bottom, output to right, or both left nd right

64 Module Genertors 8. Synch logic: SL(tlc, tlr, hi, i); - forms AND tree of inputs nd distributes outputs to rows below inputs - specified by coords of top left corner, height, nd ctive input vector

65 Module Genertors 9. Stte registers: SR(tlc, tlr, tf); - implements initil or non-initil stte using selector from N nd enble from E - specified by coords of top left corner, height, nd stte type flg

66 Overview of compiler opertion

67 Drwbcks of compiltion pproch Compile-time prtitioning does not consider runtime need for resources Which processes need to be concurrently ctive? Sttic lloctions do not dpt to run-time vilbility of resources Distributed & multitsked environments Sttic circuits do not redily support dynmic circuit behviour or structure Power of reconfigurtion remins untpped

68 An FPGA interpreter for Circl

69 Interpreter concept We pre-process spec until the functionl prmeters of modules re known At run time, the interpreter looks fter loding modules on n s needs bsis Involves module plcement, bitstrem gen & config The mount of logic loded depends upon resource vilbility Currently lod logic for stte, but could dynmiclly lod frgment of new process hierrchy

70 Overview of interpreter opertion

71 The Circl interpreter Extends the design flow to run-time mngement & ongoing FPGA configurtion circuit design does not complete until execution hs finished Finlizes prtitioning, logicl, nd physicl mpping of circuits t run time Determines through feedbck which components to implement next Elbortes & lods prts of the circuit s they re needed

72 Interprettion exmple Consider the FSM for process P with 4 sttes This process hs the following Circl spec P1 b P3 ( c) ( b) P2 P4 c b P1 ( c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2

73 Sttic circuit implementtion (lsb) IJ b m0 m1 m2 m3 m4 m5 (msb) c mn = minterm n = AND Σ = OR P1 b P3 ( c) ( b) b P2 P4 c P1 ( c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2 m0 (P1 P1) m5 (P1 P2) m0 + m2 (P2 P2) m1 (P4 P2) m2 (P1 P3) m1 (P2 P3) m0 (P3 P3) m3 (P3 P4) m0 + m4 (P4 P4) P1 P2 P3 P4 Σ Σ Σ Σ Σ SL r s

74 Circuit modelling & prtitioning P1 b P3 ( c) b P2 ( b) P4 c Processes re modelled s stte trnsition grphs nd processes re prtitioned ccording to their definitions P1 (c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2

75 Circuit modelling & prtitioning P1 ( c) b P2 b P3 ( b) P4 c P1 (c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2 Processes re modelled s stte trnsition grphs nd processes re prtitioned ccording to their definitions Initilly, the interpreter implements sub-grph rooted t the initil stte

76 Circuit modelling & prtitioning P1 ( c) b P2 b P3 ( b) P4 c P1 (c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2 Processes re modelled s stte trnsition grphs nd processes re prtitioned ccording to their definitions Initilly, the interpreter implements sub-grph rooted t the initil stte Nodes re included bredth-first until it is not possible to fit the trnsition logic for the next stte

77 Circuit modelling & prtitioning P1 ( c) b P2 b P3 ( b) P4 c P1 (c) P2 + bp3 P2 bp2 + P3 P3 ( b) P4 P4 cp4 + P2 Processes re modelled s stte trnsition grphs nd processes re prtitioned ccording to their definitions Initilly, the interpreter implements sub-grph rooted t the initil stte Nodes re included bredth-first until it is not possible to fit the trnsition logic for the next stte

78 Exmple Suppose the rry re for process P cn only ccommodte the behviour for stte P1 To determine which trnsition occurred, boundry stte registers for P2 nd P3 re needed s well (lsb) IJ b m0 m2 m5 (msb) c mn = minterm n = AND Σ = OR m0 (P1 P1) Σ m5 (P1 P2) m2 (P1 P3) P1 P2 P3 Σ Σ Σ SL r s

79 Determining circuitry to lod next When the boundry of the implemented subgrph is reched, the interpreter builds new sub-grph rooted t the boundry stte tht hs become ctive We use quick estimte of the dditionl spce needed by stte nd its trnsition logic Estimtor bsed on number of trnsitions from stte

80 Constructing the new sub-grph P1 b P3 ( c) b P2 ( b) P4 c Suppose we cn support the logic for T=6 trnsitions in totl

81 Constructing the new sub-grph P1 b P3 ( c) b P2 ( b) P4 c Suppose we cn support the logic for T=6 trnsitions in totl P1, P2, & P3 cn be implemented with T=5, but the inclusion of P4 with t4=2 is deemed infesible

82 Constructing the new sub-grph P1 b P3 ( c) b P2 ( b) P4 c Suppose we cn support the logic for T=6 trnsitions in totl P1, P2, & P3 cn be implemented with T=5, but the inclusion of P4 with t4=2 is deemed infesible When P4 becomes ctive, P2, P3, & P4 form stble configurtion

83 Detecting the need for reconfigurtion We support two modes of opertion: 1. Observed mode: ll process sttes re polled ech cycle 2. Unobserved mode (such s in n embedded ppliction): some smll circuitry is dded to ech process in order to interrupt the VHM when boundry stte is reched

84 FPGA prtitioning FPGA re is stticlly prtitioned to simplify run-time reconfigurtion Initilly, spce to ccommodte the lrgest stte for ech process is llocted this is then expnded to provide more spce for dditionl sttes when possible

85 Experimentl ssessment Rndom process genertion Timing of sub-grph selection in front end with vried brnching fctors nd circuit widths Worst-cse timing mesurements for circuit initilistion nd updte in the bck end Used 500Mhz, 512MB PIII, Jv, JBits, nd Celoxic XCV1000 bord

86 Exploits fst crry chins nd minimizes number of reconfigurtion frmes Deploys routing frmework to reduce rerouting overheds Virtex lyout

87 Sub-grph selection time (ms) vs Process width (CLB cols)

88 Initil bitstrem genertion time (s) vs Process width (CLB cols)

89 Generting circuit updtes (ms) vs Process width (CLB cols)

90 Reconfigurtion time (ms) vs Process width(clb cols)

91 Anlysis High routing costs with JBits, even for highly structured circuits Constrins the designs tht cn be run-time reconfigured Cpble of reconfiguring within 100ms The current methodology is fine for control pplictions tht cn tolerte these delys Lower bound on implementtion delys in the order of 10ms More hrdwre required for pplictions tht cnnot tolerte this

92 Further interpreter work Performnce improvement Better router Cching loops Better prtitioning strtegies? Determining how to efficiently dpt to dynmic prtition sizes Incorporting dt flow into the Circl interpreter Tking user s performnce objectives into ccount

93 Ongoing work

94 Generlized processes Work done by Jérémie Detrey to implement hierrchy, bstrction nd process cretion Developed on Wildcrd XCV300 implementtion of compiler

95 Abstrct process interfce For the vriety of process blocks required, common process interfce hs been defined

96 FSM process As before, only llows choice nd gurding, but process cn be switched on/off nd provides for bstrcted (internl) events

97 Implementing event bstrction

98 Hierrchicl composition

99 Hybrid process FSM-like behviour Stte could be composition or bstrction For exmple, consider process P 0 defined s P P P P P 1 0 bp 0 + bp 2 + c( Q + c( S R) d) Q R c P0 P1 P2 S - d b b c

100 Implementing hybrid processes Determine the FSM prt, clled P FSM Determine the other composition nd bstrction processes, P 1,, P n Currently, ly them ll out stticlly

101 Hybrid process block lyout

102 Sttus Tested these ides by implementing (on the Wildcrd) Turing Mchine using Circl s the specifiction lnguge Involved use of hierrchy, composition, nd bstrction Stticlly prellocted tpe of given length, but ctivted tpe squres s hed moved over them

103 Future work Support generlized processes in the interpreter Replce the interpreter front end Define dynmic lyouts for generlized processes Develop concepts for dynmic lloction of hybrid processes

104 Conclusion

105 In summry We ve mde progress towrds describing nd implementing sttic nd utomticlly virtulized process logic from high-level The bility to describe & implement trditionl dtpth elements needs to be incorported The rel work in formlly describing nd implementing dynmic circuits is still to come

106 Modelling reconfigurble devices How cn dynmic process cretion/destruction be described in Circl? Need dditionl semntics Is Circl, indeed process lgebr best? Wht hrdwre relistion supports the semntics? Effort lso going into deriving low-level model of reconfigurtion using Circl So fr, we re focusing on the reconfigurtor Intend this model to ct s trget of compiler/interpreter My need dditionl high-level syntx to steer compiler