A Photovoltaic Detector Technology Based on. Plasma-induced p-to-n Type Conversion of. Long Wavelength Infrared HgCdTe. Thuyen Huu Manh Nguyen

Transcription

1 A Photovoltaic Detector Technology Based on Plasma-induced p-to-n Type Conversion of Long Wavelength Infrared HgCdTe by Thuyen Huu Manh Nguyen This thesis is presented for the degree of Doctor of Philosophy of The University of Western Australia School of Electrical, Electronic and Computer Engineering The University of Western Australia 2005 i

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3 1 Abstract HgCdTe is the leading semiconductor material for the fabrication of high performance infrared photon detectors, in particular, for detection of radiation beyond the near infrared. State-of-the-art infrared detection and imaging systems are currently based around high density focal plane arrays consisting of HgCdTe photodiodes as detector elements. Despite the high performance of HgCdTe infrared detectors, and the many benefits they can offer to industry and society, their utilisation remains limited due to the high cost of production. The chemical composition and narrow bandgap of the HgCdTe material used for infrared detection means that the material is inherently very susceptible to defect formation caused by the processing procedures required for device fabrication. Consequently, fabrication of HgCdTe photodiode arrays have traditionally been characterised by low yields and high costs for arrays that meet required operability specifications. In this thesis a new photodiode fabrication technology with the potential to improve device yields over traditional fabrication technologies is presented. This new fabrication technology is distinguished from others by the use of plasma-induced p-to-n type conversion of HgCdTe for junction formation. This allows great simplification of the fabrication process and avoids high temperature processing during and after junction formation, and keeps the junction protected from the atmosphere at all stages of fabrication. The development of the photodiode fabrication technology using plasma-induced junction formation has involved characterising the electrical transport properties of the type-converted layers, fabrication and characterisation of photodiodes, and photodiode dark current modelling. The electrical transport properties of the junction formed by plasma-induced type conversion were characterised for both vacancy-doped and gold-doped p-type HgCdTe material for both mid-wavelength infrared (MWIR) and long wavelength infrared (LWIR) HgCdTe detectors. In all cases, the temperature dependence of mobility and carrier concentration for both electrons and holes were obtained. The concentration depth profile was also accurately iii

4 obtained for gold-doped LWIR HgCdTe material. The results of this study indicate that the plasma induced junction formation process employed is conducive to high performance photodiode fabrication. By incorporating the plasma-induced junction formation technology, an n-on-p photodiode fabrication process was devised with as few as three photolithographic masking processes. The merits of this fabrication technology were investigated with fabrication of several device lots, each with differing variations of the basic process. The fabricated devices were subjected to various optical and electrical tests to assess performance, including currentvoltage measurements, spectral responsivity measurements and noise measurements. The experimental data obtained from device characterisation was analysed to identify factors limiting device performance and to refine and improve the fabrication process. A photodiode dark current model was extensively used for this task, and together with variablearea data analysis, a strong indication emerged that surface effects rather than inherent junction defects were limiting device performance. To investigate the effectiveness of the surface passivation and the effects of trapped charge in the passivation, a gated diode structure was employed, allowing the surface charge conditions to be modified. The technology required to fabricate LWIR HgCdTe photodiodes using plasma-induced junction formation has been developed to the point where it has been established that the junction formed by plasma-induced p-to-n type conversion has favourable properties for excellent photodiode performance, and the surface passivation has been identified as being by far the greatest factor limiting device performance. iv

5 2 Table of Contents 1 Abstract iii 2 Table of Contents v 3 Acknowledgements viii 4 List of Constants and Symbols ix 1 Introduction Thesis Layout Infrared Detection and Mercury Cadmium Telluride Thesis Aims and Objectives 10 2 Device Fabrication Technology Overview of the Photodiode Fabrication Procedure Summary of Fabricated Device Lots HgCdTe Wafer Processing Considerations Surface Passivation Considerations Junction Formation Technology Contact Formation Chapter Summary and Conclusions 43 3 Characterisation of the Carrier Transport Properties of Plasma-induced p-to-n Typeconverted Layers in HgCdTe The Hall Effect Van der Pauw Configuration Analysis of Multicarrier Systems Quantitative Mobility Spectrum Analysis Sample Preparation and Experimental Setup Results for LWIR Au Doped HgCdTe 58 v

6 3.7 Results for LWIR Vacancy Doped HgCdTe Results for MWIR Au Doped HgCdTe Results for MWIR Vacancy Doped HgCdTe Summary and Comparisons Between Type-converted Samples Surface Passivation Chapter Summary and Conclusions 89 4 LWIR Device Characterisation and Performance Evaluation Current-Voltage Characteristic Measurements Spectral Responsivity Measurements Noise Measurements Vacuum Baking Zero Bias Dynamic Resistance-Area Product Analysis of R 0 A Data The Effects of Vacuum Baking on Photodiode Performance Chapter Summary and Conclusions Dark Current Modelling The Photodiode Dark Current Model Diffusion Current Generation-recombination Current Band-to-band Tunnelling Current Trap-assisted Tunnelling Current Surface Dark Current Considerations HgCdTe Material Parameters Data Fitting and Analysis Analysis of the Temperature Dependence Chapter Summary and Conclusions Surface Effects on HgCdTe Photodiodes 149 vi 6.1 Fabrication and Characterisation of Gated Photodiodes Analysis of Results 151

7 6.3 Analysis Using Dark Current Models Temperature dependence Vacuum Bake Stability of Photodiodes Analysis of Vacuum Baked Devices with Consideration to Surface Effects Chapter Summary and Conclusions Noise Characteristics Photodiode Noise Mechanisms The Dependence of LWIR Photodiode Noise on Junction Bias The Dependence of Photodiode Noise on Temperature Noise and Variable Size Photodiodes Chapter Summary and Conclusions Conclusions Original Contributions and Achievements Recommendations for Future Work Conclusions Publications References vii

8 Acknowledgements I would like to give thanks and acknowledge the help of members of the Microelectronics Research Group (MRG) who I have had the opportunity to work with during my studies. I am also grateful for the scholarship given to me by the group. Special thanks go to my supervisors, Dr Charles Musca and Associate Professor John Dell; and to Professor Lorenzo Faraone, who also played a supervising role and assisted me greatly. And of course, there is always my family who are simply the best. viii

9 4 List of Constants and Symbols Symbol Description Units c Speed of light ms -1 h Planck's constant Js k Boltzmann constant J K -1 m o Free electron rest mass kg q Electronic charge C ε 0 Permittivity of free space Fcm -1 σ Stefan-Boltzman constant Wm -2 K -4 A Junction area of photodiode cm 2 P Perimeter of junction cm B Magnetic field T D* Specific detectivity cmhz 1/2 W -1 D e Electron diffusion coefficient cm 2 s -1 D h Hole diffusion coefficient cm 2 s -1 E Electric field Vcm -1 Ε Α Activation energy ev E c Energy of conduction band edge ev E f Fermi energy level ev E g Energy gap ev E i Intrinsic energy level ev E t Energy level of trap ev E v Energy of valence band edge ev G Generation rate cm -3 s -1 ix

10 Symbol Description Units I Current A J Current density Acm -2 L d Diffusion length µm M Transition matrix element between trap level and conduction band P Kane matrix element m e * Effective electron mass kg m h * Effective hole mass kg n Density of electrons cm -3 n Excess electron density cm -3 N A Acceptor density cm -3 N D Donor density cm -3 NEP Noise equivalent power WHz -1/2 n i Intrinsic carrier concentration cm -3 N t Trap density cm -3 p Density of holes cm -3 p Excess hole density cm -3 R 0 Dynamic zero bias resistance of diode Ω RA Dynamic resistance-area product Ω cm 2 R H Hall coefficient m 3 C -1 R o A Dynamic zero bias resistance by area product Ω cm 2 r s Series resistance Ω S(f) Noise spectral density A 2 Hz -1 s 0 Surface recombination velocity cm.s -1 x

11 Symbol Description Units T Absolute temperature K U Net generation-recombination rate cm -3 s -1 V Voltage V V bi Built-in junction voltage V V g Gate voltage V W d Width of the space-charge layer µm W s Depletion width at surface µm x ε r η Mole fraction of cadmium in HgCdTe (Hg 1-x Cd x Te) Relative permittivity Quantum efficiency f Bandwidth of measurement Hz Φ Photon flux cm -2 Φ B Background photon flux density cm -2 λ Wavelength µm λ co Cutoff wavelength µm µ Mobility cm 2 V -1 s -1 µ e Mobility of electrons cm 2 V -1 s -1 µ h Mobility of holes cm 2 V -1 s -1 ρ Resistivity Ωcm σ Conductivity Ω 1 cm -1 σ Conductivity tensor Ω 1 cm -1 σ xx, σ xy Components of conductivity tensor Ω 1 cm -1 τ Carrier lifetime s xi

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13 1 Introduction Chapter 1 Introduction The development and characterisation of a novel long wavelength infrared (LWIR: wavelengths between 8 and 14 µm) HgCdTe photodiode fabrication technology is the main motivation behind the work undertaken for this thesis. The salient feature which sets this photodiode fabrication technology apart from traditional methods is the use of plasma-induced p-to-n type conversion of HgCdTe to form the n-on-p junction. Traditional HgCdTe fabrication technologies generally suffer from low device yields and poor uniformity due to the chemical reactivity and intrinsically volatile nature of HgCdTe. Specifications for HgCdTe focal plane arrays (FPA) are often quite stringent, with a maximum pixel defect rate of less than 1% being common. A dated report from 1990 indicates that array yields are in the vicinity of only 4% for a pixel defect rate of 2%, and if the number of defective pixels are allowed to increase to 4%, the array yield increases to about 40% [1]. The great simplification to the overall fabrication technology, and resulting improvements in device yield and uniformity afforded by the plasmainduced junction formation process, give this technology a major advantage over traditional technologies if the fabricated devices are capable of high performance. The fabrication of midwavelength infrared (MWIR) photodiodes using the plasma-induced junction formation technology has previously been shown to produce devices with state-of-the-art performance. The aim of this thesis is to achieve the more difficult task of extending this junction formation technology to produce high-performing LWIR photodiodes. The work undertaken encompasses device fabrication, materials characterisation, device performance characterisation and evaluation, device modelling, and analysis of device characteristics. 1

14 Chapter 1 Introduction 1.1 Thesis Layout This thesis is divided into eight chapters. This chapter presents introductory and background information which will put the work undertaken and results obtained into context. The motivations behind the work and the aims of this thesis are outlined in this introductory chapter; however, at the beginning of each chapter a more detailed introduction is given which is more specific to the work presented. The second chapter describes in detail the processes used to fabricate LWIR HgCdTe photodiodes studied in this thesis. The chapter evaluates the various junction formation technologies available, including the plasma-induced p-to-n type conversion of HgCdTe. Other major issues associated with HgCdTe photodiode fabrication are also discussed. In Chapter 3 the results of the study on the plasma-induced p-to-n type conversion of HgCdTe are presented. Plasma-induced type conversion of HgCdTe is used for junction formation in the photodiode fabrication process of this thesis and hence it is important to characterise this process and the electrical characteristics of n-type material produced. The characterisation consisted of magnetic field dependent Hall effect and resistivity measurements, and the analysis of the resultant data using Quantitative Mobility Spectrum Analysis (QMSA). QMSA is critically important in analysing the data as it enables the properties of the type converted region and the underlying unconverted region to be evaluated simultaneously and independently. Chapter 4 details the experimental techniques used to characterise the fabricated photodiodes. These techniques include current-voltage measurements, spectral responsivity measurements and noise measurements. Multiple device lots were fabricated with varying process conditions and the performance of the fabricated photodiodes was evaluated, allowing comparisons to be made between the various device lots. Analysis of variable area data is extensively used for this purpose. A significant portion of this thesis involved the development of a photodiode dark current model to analyse the experimental I-V data, and this model is presented in Chapter 5. 2

15 Chapter 1 Introduction Photodiode dark current fundamentally limits device performance. Therefore, obtaining an accurate model of the dark current generation mechanisms is essential in enabling a greater understanding of the factors limiting device performance and identifying the areas requiring improvement. The dark current model presented in Chapter 5 is extensively used in subsequent chapters to analyse experimental results. The effect of the semiconductor surface on device performance, and the effectiveness of the semiconductor surface passivation process are explored in Chapter 6. This was achieved with the use of a gated diode structure which allows the surface charge conditions to be modified. Due to the narrow bandgap of LWIR HgCdTe, obtaining an ideally passivated surface becomes crucially important because even a small amount of surface band-bending can result in surface leakage currents dominating device performance. In this chapter the dramatic effect of surface passivation charge on the I-V characteristics of the photodiode is demonstrated. Experimental photodiode electrical noise measurements are presented in Chapter 7. The data include measurements of noise under varying temperature and diode bias conditions. The low-frequency 1/f noise region is examined in greatest detail. Chapter 8 provides a summary of the results and conclusions which have been able to be drawn from the work undertaken for this thesis. 1.2 Infrared Detection and Mercury Cadmium Telluride The Infrared Spectrum The infrared (IR) spectrum is considered to be the region of the electromagnetic spectrum which spans 1 µm to 100 µm in wavelength. This puts it above the microwave spectrum and below the visible spectrum in terms of photon energy. Within the IR spectrum there are regions of greater significance for imaging applications. Figure 1.1 shows the optical transmission of IR through the atmosphere and the main sources of absorption. The region from 1 µm to 3 µm is referred to as the short wavelength infrared (SWIR), the region from 3 µm to 5 µm is referred to as the mid-wavelength infrared (MWIR), and the region from 8 µm to 14 µm 3

16 Chapter 1 Introduction Fig. 1.1 The transmission of infrared radiation through the Earth s atmosphere over a 2 km horizontal path at sea level. is referred to as the long wavelength infrared (LWIR). Beyond the LWIR region, the very long wavelength infrared (VLWIR) region extends to 50 µm and the region from 50 µm to 100 µm is referred to as the far infrared (FIR). Beyond the FIR the infrared spectrum begins to overlap with the microwave spectrum. For imaging applications, there is obviously a strategic advantage to being able to detect radiation in the high transmission regions shown in Fig The LWIR region holds added significance since the peak emissions of blackbody objects at near room temperature (in the range 250 K to 350 K) occurs at wavelengths in this region. This makes LWIR detectors highly suited to thermal imaging of general objects, in addition to requiring no illumination sources. The same is true for the MWIR region except that the peak emission corresponds to hotter objects, with temperatures of hundreds of degrees Celsius. MWIR may also be used to image room temperature scenes but there are several differences between the characteristics of MWIR and LWIR radiation that will give advantage to one detector over the other for a given temperature. For example, LWIR will experience greater attenuation than MWIR, particularly in high humidity environments. However, there will be greater signal strength from a room temperature target in the LWIR and, if imaging during the day, there will be greater solar background noise in the MWIR. Therefore, the choice between LWIR and MWIR detectors is a 4

17 Chapter 1 Introduction complicated issue in general, and is strongly dependent on the specifics of the particular application. Classification of Infrared Detectors IR detectors can be broadly classified as thermal detectors or photon detectors. Thermal detectors rely on the absorption of radiation to heat a material and, as a consequence, induce a change in the electrical characteristics of the material. Photon detectors rely on the absorption of photons to directly generate charge carriers. Although all IR radiation consists of photons, and hence the name photon detector can equally apply to either detector type, the term photon detector in this context refers to the fundamental detection mechanism of individual photons directly generating charge carriers. Bolometers, thermopiles and pyroelectric detectors are the most common form of thermal detectors. There have been great advances in thermal detector technology recently, with micromachined bolometers and pyroelectric focal plane arrays becoming commercially available. In comparison to photon detectors, they are less sensitive and/or have a longer response time. These two critical detector characteristics are determined by the thermal mass of the thermal detector element and the rate of heat loss from the detector element. Advances achieved using micromachining have enabled miniaturisation of detector elements to reduce thermal mass, and improvements in reducing conduction loss. As a result, TV video frame rates are now achievable with uncooled detector arrays [2]. There are three broad categories of infrared photon detectors: intrinsic, extrinsic and quantum well/dot detectors. Intrinsic detectors rely on the absorption of photons to promote electrons from the valence band into the conduction band, thereby generating electron-hole pairs. On the other hand, extrinsic detectors rely on the absorption of photons by impurities to promote electrons into the conduction band or to create holes in the valence band by promoting electrons from the valence band into an impurity level. One of the main disadvantages of extrinsic detectors compared to intrinsic detectors is that, because photons can only be absorbed 5

18 Chapter 1 Introduction Fig. 1.2 The operating principles of a photoconductor and a photodiode. The description is given in the text. by impurity atoms, a large volume of material is required to collect a significant portion of the incident radiation. Extrinsic detectors also require much higher levels of cooling to suppress thermally generated carriers, which directly contribute to the internally generated noise. For example, extrinsically doped silicon LWIR detectors are typically operated below 20 K, while intrinsic LWIR HgCdTe detectors are typically operated at 60 K to 80 K [3]. Among the intrinsic detectors, the most common forms are the photoconductor and the photodiode. The photoconductor is essentially a photosensitive resistor, where the absorption of infrared radiation by the HgCdTe material generates electron-hole pairs, thereby increasing the conductivity of the semiconductor, as shown in Fig This change in conductivity is measured by supplying a constant bias current/voltage and measuring the voltage/current signal. Compared to photoconductors, photodiodes are capable of slightly higher performance and the biasing requirements are less stringent. Figure 1.2 shows that photons are detected by the photodiode when they are absorbed in the HgCdTe material and electron-hole pairs are generated. The generated minority carriers are free to diffuse and, upon reaching the junction depletion region, are swept across the junction by the built-in electric field giving rise to a charge imbalance in both the n- and p-regions. An external circuit can then be used to measure either the resulting voltage or the photon-generated current due to this charge imbalance. A 6

19 Chapter 1 Introduction notable difference between narrow bandgap photodiodes and those designed for detection in the NIR and visible spectrum is the region of absorption. NIR and visible photodiodes are designed to absorb the incident photon in the depletion region which is obtained by applying a large bias or by using a p-i-n configuration. By maximising the width of the depletion region relative to the neutral n- and p-type regions the speed and quantum efficiency of the device is improved. However, this scheme cannot be realised for narrow bandgap semiconductor devices because high electric fields in the depletion region cannot be supported due to the onset of tunnelling. Instead, photons are absorbed in the neutral regions and the generated minority carriers must diffuse to the depletion region to be detected. HgCdTe photodiodes can be operated unbiased which is an advantage over photoconductors since the constant current through a photoconductor produces a heat load that must be accommodated by the cryogenic cooling system. In addition, the absence of the biasing circuit components reduces the complexity of the readout circuit. These factors are of great significance when detectors need to be densely integrated in 2-D array applications. In cases where the zero-bias dynamic resistance is low, photodiodes need to be operated in reverse bias, increasing the dynamic resistance to improve the efficiency of carrier injection into the readout circuit. In these cases the heat generated by biasing is still much less than for photoconductors, and is usually negligible. Mercury Cadmium Telluride Infrared Detectors Mercury cadmium telluride (HgCdTe) is a II-VI compound semiconductor that has been intensively researched for infrared detector applications since By varying the ratio of CdTe to HgTe, the bandgap can be continuously tuned from -0.3 ev to 1.6 ev, allowing sensitivity to be optimised for any region of the IR spectrum. The material is often denoted as Hg 1-x Cd x Te where x is the ratio of CdTe to HgTe. Further, the material system has a nearly constant lattice parameter, making it possible to grow heterojunctions with low defect densities. The value of x (or composition) for MWIR material is approximately 0.3, and approximately 7

20 Chapter 1 Introduction Fig. 1.3 Wavelength response of several narrow bandgap semiconductor material systems. [4] 0.2 for LWIR material. In this thesis the shorter notation of HgCdTe will be used and the x-value stated where appropriate. The fundamental properties which make HgCdTe an ideal semiconductor material for IR detection arise due to it being a narrow bandgap semiconductor with a tuneable bandgap. HgCdTe possess a direct narrow bandgap and a high density of states, which results in a high absorption coefficient, and means that the material is efficient at converting incident photons into electron-hole pairs. The high electron mobility inherent in HgCdTe material also assists in converting the photon signal into electronic form. Another critical property of HgCdTe is its low permittivity which influences the speed of the device and results in low refractive index, making the design of anti-reflective coatings easier. Figure 1.3 compares the operating wavelengths possible for photodetectors fabricated from HgCdTe with other competing material systems [4]. As can be seen, HgCdTe is the only 8

21 Chapter 1 Introduction materials system that is able to encompass the entire IR spectrum. HgCdTe, like many of the competing narrow bandgap semiconductor materials, is an extremely difficult material to grow and process without causing damage to the material and, hence, adversely affecting the performance of the resultant devices. Processes involving heat, wet processing and plasma processing are all likely to induce defects unless quite stringent conditions are adhered to. The fragile nature of HgCdTe is due largely to the weak bonding of Hg in the crystal lattice and has resulted in extremely high cost for device quality material, and low device yield and uniformity for fabricated devices. Despite the difficulties involved in the growth and processing of HgCdTe, there continues to be a large research effort in the field of HgCdTe infrared detectors. Detector performance is the reason for this research effort. Figure 1.4 compares the theoretical maximum performance of HgCdTe photodiodes to other types of IR detectors in terms of the specific detectivity D*, a detector figure of merit, with and without a background photon flux Φ B. Specific detectivity, D*, is a measure of normalised signal to noise ratio for a detector [4]. Figure 1.4 also compares the detectivity of the different detector types with and without a background photon flux. It shows that the photon detector performance increases as temperature decreases, and that the maximum D* is limited by the noise associated with Φ B. The D* values of existing thermal detectors are of the order of 10 9 cmhz 1/2 W -1 [5]. In contrast, many photodiodes exhibit performance very close to the theoretical limit [6-9]. It can be seen that among the photon detectors, HgCdTe photodiodes are orders of magnitude more sensitive than the other detector types. Figure 1.4 uses a photodiode with a cutoff wavelength (the longest wavelength that can be detected by the detector) towards the end of the LWIR region for comparison purposes. The detectivity of a photodiode is expected to increase for shorter cutoff wavelength detectors and decrease for longer cutoff wavelength detectors. On the other hand, the detectivity of thermal detectors will remain constant at all wavelengths, making them the best choice among infrared detectors for the FIR and much of the VLWIR. The preference for thermal detectors is enhanced by the increasing difficulty in achieving near ideal photodiode 9

22 Chapter 1 Introduction Fig. 1.4 Theoretical performance limits of LWIR photon and thermal detectors as a function of temperature for a background photon flux of 0 and photons cm -2 s -1. [4] detectors as the cutoff wavelength increases. It should also be noted that detectivity is only one aspect of detector performance. Another important aspect is the detection speed of the device, and although thermal detectors may theoretically offer higher detectivity at very long wavelengths, the response will remain slow in comparison to HgCdTe photodiodes. 1.3 Thesis Aims and Objectives Presently, the application and utilisation of high performance HgCdTe detectors in industry and society is quite limited, with high cost being the major factor preventing large scale deployment. A major component of the cost, especially for 1-D and 2-D arrays, is due to difficulties in fabricating devices. Traditionally, device yields are extremely low for detector arrays due to individual device failure and non-uniformity in device performance. Considering the high cost of the starting HgCdTe material due to the technological difficulties in growing device quality HgCdTe wafers, the reason becomes apparent as to why the cost of HgCdTe 10

23 Chapter 1 Introduction detectors continues to restrict their use in spite of its many potential applications. This thesis presents the development of a new LWIR HgCdTe photodiode fabrication technology that has the potential to improve device yields by significantly simplifying the fabrication process without compromising performance. The thesis firstly aims to investigate the feasibility of LWIR HgCdTe photodiode fabrication using plasma-induced p-to-n type conversion for junction formation, and then to advance this fabrication technology towards obtaining highperformance devices. To achieve these aims, the first objective is to develop a photodiode fabrication process that is compatible with HgCdTe and utilises plasma-induced type conversion for junction formation. Other objectives are to devise and implement characterisation techniques to determine the electronic properties of the type-converted HgCdTe as well as the performance of the fabricated photodiodes. The experimental data will then be analysed and models formulated to gain an understanding of the factors limiting performance. An understanding of device behaviour and the identification of limiting factors will then enable further advancement of the fabrication technology. 11

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25 2 Device Fabrication Technology Chapter 2 Device Fabrication Technology Photodiodes are the preferred devices for use in high-performance, highly-integrated infrared detector arrays. However, the technology for HgCdTe photodiode fabrication is still not standardised. There are currently several competing and very different technologies employed in industry and under active development. Furthermore, all current technologies still suffer from high levels of non-uniformity in arrays, and low device yields in comparison to traditional fabrication technologies used for Si and GaAs. This is especially true for narrow bandgap materials used for long-wavelength infrared (LWIR) devices. Progress in device development has enabled high-performance detectors, but the low device yields and the associated high cost of production are major reasons for the technology remaining prohibitively costly for many industries. These low device yield problems are inherent to any HgCdTe technology owing to the material being a ternary compound semiconductor, possessing a narrow bandgap, and having a low damage threshold due to the weak bonding of Hg in the crystal lattice. These factors manifest themselves as problems at all stages of device fabrication, starting from the growth of the material. There is still much scope for improvement in uniformity and device yields if a device fabrication process can be developed that minimises processing-induced damage. Whilst improvements in device yields are important, any improved process must also achieve high performance in the fabricated detectors, which is the area where HgCdTe devices have the advantage over all other IR detection technologies. The photodiode fabrication technology developed at the University of Western Australia (UWA), which is the focus of this thesis, shows promise in increasing device yields through a simplified fabrication process. The key component of this technology is the use of plasma-induced p-to-n type conversion to form the n-on-p junction, allowing great simplification of the fabrication process. High temperature processing during and after plasmainduced junction formation is unnecessary, which also avoids thermally induced damage to the 13

26 Chapter 2 Device Fabrication Technology devices. This junction formation technology also produces planar devices, which is advantageous for downstream processing and integration of the detectors into the final IR detection system. Another key advantage of the process is that it protects the surface region intersecting the formed junction by avoiding exposure to atmosphere at all stages of fabrication an advantage for achieving high device performance. This chapter details the processing steps of the photodiode fabrication process developed at UWA along with the technical challenges which must be overcome to obtain high performance LWIR photovoltaic detectors. 2.1 Overview of the Photodiode Fabrication Procedure The photodiode fabrication process developed at UWA is schematically represented in Fig. 2.1, followed by a description of the fabrication process. The branching in the process accommodates the optional deposition of a ZnS overlayer. The simplicity of the process is apparent from the process flow of Fig. 2.1, requiring as little as three photolithography procedures and no high-temperature anneal. The reduced processing requirements is an advantage in the fabrication of HgCdTe devices since processing can, because of the low damage threshold of the material, easily induce damage that detrimentally affects uniformity and device yield. The fabrication process for LWIR photodiodes developed in this thesis is adapted from the fabrication process for MWIR photodiodes using plasma-induced junction formation which was also developed at UWA [9]. The promise of high performance and high uniformity from diodes fabricated using plasma junction formation have already been realised in MWIR devices [9]. Successful development of the process for LWIR devices presents a much greater challenge since the bandgap of LWIR HgCdTe is significantly narrower (E g ~120 mev) in comparison to MWIR HgCdTe (E g ~250 mev). 14

27 Chapter 2 Device Fabrication Technology Legend Wafer Cleaning and Thinning CdZnTe p-type HgCdTe n-type HgCdTe Surface Passivation Passivation ZnS Cr n-region Definition In Junction Formation ZnS Overlayer Deposition Etching of ZnS to Expose n-type Region n-contact Formation p-contact Formation Fig. 2.1 An overview of the HgCdTe photodiode fabrication process employed in this thesis. Two alternative surface passivation schemes are shown either with or without the ZnS overlayer. 15

28 Chapter 2 Device Fabrication Technology Wafer Cleaning and Thinning The device fabrication process begins with an epitaxial HgCdTe wafer. For this work most of the samples used were liquid phase epitaxy (LPE) grown HgCdTe on lattice matched CdZnTe substrates. The fabrication process requires the starting HgCdTe material to be p-type, with extrinsic gold doped and Hg vacancy doped samples examined for this thesis. However, the process should also be compatible with p-type material doped with other impurity atoms such as As [10]. In the initial processing step the sample is cleaned in consecutive baths of trichloroethylene, acetone and methanol, and the HgCdTe epilayer is optionally thinned. Thinning of the absorbing layer is one of the techniques used to obtain optimal device performance, since the epilayer thickness should be optimised to minimise thermally generated diffusion dark currents whilst still maintaining high quantum efficiency with high levels of photon absorption. For LWIR detectors this optimal thickness is approximately 10 µm. However, the as-grown thickness of the HgCdTe epilayers used in this thesis are typically 20 µm thick, and were not usually thinned since device concepts are still under development and other considerations need to be investigated. It is also likely that material parameters such as x-value closer to the substrate are different to those closer to the surface due to the LPE growth technique [11]. Wafer thinning, when attempted, was performed by etching in a 0.1% Br 2 -methanol solution. Surface Passivation The next step of the process is the passivation of the HgCdTe surface, which aims to render the surface of the material electrically inactive, since surface effects can be detrimental to performance. The success of this component of the fabrication process is crucial in determining device performance, and is particularly challenging for LWIR material due to the extremely narrow bandgap (E g ~120 mev for LWIR HgCdTe at 80 K). This subject is discussed in greater detail later in this chapter. For the fabricated devices, the surface was passivated by thermally evaporated CdTe, ZnS or a CdTe/ZnS double layer. In this thesis the term deposition is used to 16

29 Chapter 2 Device Fabrication Technology describe the formation of the passivation layer since the crystallinity of the layer is often unclear, and it is expected that most deposited layers will be in the polycrystalline to amorphous state. In contrast, the term growth is used to describe the formation of a layer with high crystallinity. The deposition conditions and passivation layer thickness were varied between sets of devices and are detailed later in this chapter in Table 2.1. Prior to deposition of the passivation layer, the HgCdTe is dip etched for several seconds in 0.01% Br 2 -methanol to expose a fresh surface. P-type HgCdTe surfaces which are exposed to atmosphere are observed to become n-type due to oxide formation [12-14]. By exposing a fresh HgCdTe surface and minimising the time it is exposed to the atmosphere, the possibility of formation of an n-type surface is minimised. Plasma-induced n-on-p Junction Formation Photolithographic pattern transfer techniques are used to define the HgCdTe regions that are to be type converted to n-type, which are then exposed by performing a wet chemical etch of the passivation layer. For CdTe passivated samples, the CdTe was etched with a Br 2 -HBr solution rather than the more commonly used Br 2 -methanol since methanol attacks the photoresist used in this work. For ZnS passivated samples HCl was used as the passivation layer etch. Approximate etch times were determined using previously established etch rates. After initial etching, the samples are inspected under a microscope to determine whether additional etching is required. Once the passivation layer has been etched to expose regions to be typeconverted, the photoresist is removed with acetone and the sample rinsed with methanol prior to being transferred to the RIE chamber for type conversion of the exposed HgCdTe regions. The plasma processing system used was a Plasma Technology RIE80 parallel plate reactor, and the plasma was formed using a H 2 :CH 4 gas ratio of 4:1 and an applied RF power of 90 W. The sample sits on a chuck that is at approximately 13 C and the entire sample surface is exposed to the plasma, with the passivation layer acting as a physical mask to the type conversion process. The sample is exposed to the plasma for two minutes before the power is reduced to zero in 17

30 Chapter 2 Device Fabrication Technology order to extinguish the plasma. The exposed HgCdTe regions are type converted from p-type to n-type, and the type conversion is expected to extend both vertically into the HgCdTe layer and also laterally [15], thus forming an n-on-p junction which is protected from atmosphere by the passivation layer at the surface. The CdTe or ZnS mask/passivation layer is not damaged by the plasma processing and can remain on the wafer and become part of the final device structure. The fact that the passivation layer can be retained, combined with the fact that no hightemperature anneal is required to activate dopants or to repair any damage to the underlying HgCdTe crystal, provides the potential for developing a high-yield, high-performance HgCdTe photovoltaic detector technology. Deposition of ZnS Overlayer In the completed device structure, indium bump bonding technology was not employed; therefore the metal contacts to the n-type region need to be electrically isolated from the p-type region. If the electrical insulating properties of the passivation layer are sufficient, it can act as the insulator between the overlapping portion of the n-contact and the underlaying p-type material. ZnS has excellent electrical insulating properties and for samples passivated with this material, the passivation layer will provide the required insulating properties. However, the insulating properties of CdTe are inferior to those of ZnS and, thus, the deposition of a second dielectric may be required to provide adequate insulating properties for devices passivated with thin layers of CdTe. Also, depending on the thickness of the CdTe passivation, the effect of the overlapping metal contact can be to invert or accumulate the surface. In these circumstances, ZnS is deposited as an overcoat second dielectric in order to minimise the effect of the overlapping contact. The same procedure used to deposit ZnS as a passivation layer can be used to deposit the ZnS overlayer, with a 0.3 µm deposited layer having been found to be adequate. The deposited ZnS layer will cover the entire surface of the sample, requiring further photolithography and HCl etch processes to expose the n-type region for the subsequent deposition of the metal contact. 18

31 Chapter 2 Device Fabrication Technology ZnS Edge n-type Region CdTe Edge n-type Contact Pad p-type Region p-type Contact Pad µm Fig. 2.2 Microscope photograph of some fabricated photodiodes identifying the main regions identified. Contact Metallisation Contacts to the devices were formed by the deposition of 200 Å of chromium (Cr) followed by 2000 Å of indium (In) for both p- and n-contacts. This metallisation procedure was carried out using thermal evaporation of the metals followed by a lift-off process, which involves using photolithography to mask off regions that are not to be covered by the metal. The sample is then placed in a vacuum chamber and the contact metals are evaporated onto the sample surface. Since In and Au are fast diffusers in HgCdTe, the purpose of the Cr layer is to act as a barrier to the in-diffusion of In or Au from the contact. For Au contacts, the Cr layer also promotes adhesion of the Au. The sample is then removed from the vacuum chamber and soaked in acetone to dissolve the masking photoresist. As the photoresist is dissolved, the overlaying metal lifts off while the metal deposited on the unmasked region remains. Gentle agitation and/or a gentle jet of acetone will assist the lift-off process. Individual contacts were formed to the n-type regions of each photodiode, and all photodiodes shared a common contact to the p-type region. A further mask/metallisation/lift-off procedure was employed to form the contact to the p-type region. Alternatively, a very large area of n-type material can be used as 19

32 Chapter 2 Device Fabrication Technology the p-type contact since the defect density of the material will almost certainly guarantee a low impedance conduction path through to the p-type region. Although this latter procedure is impractical for final production of devices, it proves more convenient when fabricating devices in the development phase since it requires one less photolithography step. Since the fabricated devices were for evaluation purposes only, the contact pads were made quite large in order to simplify the bonding methods used. Figure 2.2 shows a photograph of some completed devices prior to bonding, with the wafer viewed from above. In the photograph the light is able to penetrate through the metallic contact to reveal the underlying type converted region and the delineation of the ZnS overlapping the CdTe region. Bonding and Packaging The fabricated devices were mounted onto a ceramic chip carrier, and the individual devices were bonded out to the leads of the chip carrier using conductive silver epoxy and gold wire. This process was accomplished by manually applying conductive epoxy and gold wire onto the contact pads while viewing under a microscope. Figure 2.3 shows a photograph of a set of devices bonded out to a chip carrier. The process of bonding out individual devices by hand is not ideal and inadvertent damage to devices caused by human error should be expected. It is envisioned that when the fabrication technology is further developed and ready to be deployed to produce actual detector arrays, the devices will be flip-chip bonded onto either a readout circuit or a fan-out pattern using indium bumps. Figure 2.4 shows a diagram of a set of planar devices flip-chip bonded to a readout circuit. The detectors are back-side illuminated through the CdZnTe substrate which is transparent to IR radiation. 2.2 Summary of Fabricated Device Lots The details of each of the device lots fabricated as part of the work in this thesis are listed in Table

33 Chapter 2 Device Fabrication Technology Fig. 2.3 Photograph of a set of fabricated devices bonded out to a ceramic chip carrier. Transparent Substrate n-type HgCdTe (p-type) Indium Bump Silicon Readout Circuit Fig. 2.4 Flip-chip bonding of photodiodes onto a readout circuit using In bump bonding technology is required for devices fabricated in high density. 21

34 Chapter 2 Device Fabrication Technology Table 2.1 Details of fabricated device lots. Only HgCdTe photodiode device lots which were successfully completed are included. (Continues on the following pages) Process run ID Wafer ID p-type Wafer Details at 77 K (nominal) Surface Passivation Details Contact Metal TN Au doped: cm -3 λ co =9.9 µm, µ p =570 cm 2 V -1 s -1 t=20 µm thinned to 12 µm TN Vacancy doped: cm -3 λ co = 9.8 µm, µ p =550 cm 2 V -1 s -1 t=22 µm thinned to 15 µm TN Vacancy doped: cm -3 λ co =10.0µm, µ p =560 cm 2 V -1 s -1 t=15 µm thinned to 11 µm 0.3 µm ZnS (500 Å at Å/s, 2500 Å at Å/s) Sample deposition temperature (Start End) : 60º C 79º C 0.3 µm ZnS (500 Å at Å/s, 2500 Å at Å/s) Sample deposition temperature (Start End) : 60º C 79º C Sample heated to 200º C for 30 minutes then cooled to 60º C prior to deposition. 0.3 µm ZnS (500 Å at Å/s, 2600 Å at Å/s) Sample deposition temperature (Start End) : 60º C 85º C 100 Å Cr 2000 Å Au 100 Å Cr 2000 Å Au 130 Å Cr 2500 Å Au Table 2.1 continued 22

35 Chapter 2 Device Fabrication Technology Process run ID Wafer ID p-type Wafer Details at 77 K (nominal) Surface Passivation Details Contact Metal TN Vacancy doped: cm -3 λ co =9.9µm, µ p =560 cm 2 V -1 s -1 t=20 µm TN Au doped: cm -3 λ co =9.8 µm, µ p =560 cm 2 V -1 s -1 t=17 µm Sample heated to 180º C for 15 minutes prior to deposition. 0.1 µm CdTe deposited at sample temperature of 100º C 0.2 µm ZnS at 0.2 Å/s Sample deposition temperature (Start End) : 60º C 76º C Sample heated to 180º C for 15 minutes prior to deposition. 0.1 µm CdTe deposited at sample temperature of 100º C 0.2 µm ZnS at 0.2 Å/s Sample deposition temperature (Start End) : 60º C 76º C 100 Å Cr 2000 Å In 100 Å Cr 2000 Å In TN Au doped: cm -3 Sample heated to 180º C for 15 minutes prior to deposition. 100 Å Cr λ co =9.9 µm, µ p =560 cm 2 V -1 s -1 1 µm CdTe deposited at sample temperature of 100º C 2000 Å In t=20 µm 0.2 µm ZnS at 0.2 Å/s Sample deposition temperature (Start End) : 55º C 76º C Table 2.1 continued 23

36 Chapter 2 Device Fabrication Technology Process run ID Wafer ID p-type Wafer Details at 77 K (nominal) Surface Passivation Details Contact Metal TN Au doped: cm -3 Sample heated to 180º C for 15 minutes prior to deposition. 200 Å Cr λ co =9.9 µm, µ p =560 cm 2 V -1 s -1 1 µm CdTe deposited at sample temperature of 100º C 2000 Å In t=20 µm TN Au doped: cm -3 Sample heated to 180º C for 15 minutes prior to deposition. 200 Å Cr λ co =10 µm, µ p =540 cm 2 V -1 s -1 1 µm CdTe deposited at sample temperature of 100º C 2000 Å In t=18 µm TN Same as TN11 Sample heated to 100º C for 15 minutes prior to deposition. 1 µm CdTe deposited at sample temperature of 100º C 200 Å Cr 2000 Å In TN Same as TN11 1 µm CdTe deposited at sample temperature of 250º C 200 Å Cr 2000 Å In TN Same as TN11 1 µm CdTe deposited at sample temperature of 250º C with Hg flux in chamber 0.2 µm ZnS at 0.2 Å/s 200 Å Cr 2000 Å In 24

37 Chapter 2 Device Fabrication Technology 2.3 HgCdTe Wafer Processing Considerations For the fabrication of photodiodes, the basic device processing procedures such as photolithography for pattern transfer, wafer cleaning and material etching, must be tailored to suit the demanding and particular requirements of HgCdTe and the other materials involved. Techniques developed for processing more mature material systems such as Si and GaAs cannot be transferred directly to the processing of HgCdTe devices due, not only to the different chemistry involved, but also due to the fragile mechanical nature and maximum process temperature limits of HgCdTe, caused by the weak bonding and high mobility of Hg in the lattice. Consequently, defects are easily induced that can readily migrate to and from the surface and bulk. Such issues limit the processing temperature to a maximum of approximately 90 C and render other standard processes, such as RIE and plasma cleaning, difficult to use. HgCdTe wafers were cleaned to remove organic contaminants by immersion for 5 minutes each in consecutive baths of hot trichloroethylene, boiling acetone and, finally, boiling methanol. Following the methanol immersion, the samples were rinsed with methanol and dried with a jet of high purity nitrogen gas, in order to ensure that no condensation occurs on the samples. Etching of HgCdTe and CdTe was accomplished using bromine-based wet-chemical etching. In general, chemical etching of a semiconductor surface is based on oxidation or reduction of the surface atoms followed by a chemical reaction to form a soluble complex that allows these atoms to be removed from the surface. For wet-chemical etching, the solution contains both the oxidising and complexing agents. Common solutions used to etch HgCdTe and CdTe include bromine in either methanol, ethylene glycol or hydrobromic acid. For the work carried out as part of this thesis, bromine in methanol was the etching solution used for situations not involving photolithography, with bromine concentrations of either 0.01% or 0.1% by volume. The etch rate of the 0.1% solution was found to be dependent on the temperature and the elapsed time since the solution was first prepared. The bromine-methanol solutions were always prepared at an ambient temperature of C with etch rates ranging from 0.4 to 25

38 Chapter 2 Device Fabrication Technology 0.6 µm/minute. For occasions when photoresist was present, 0.1% or 1.0% bromine in hydrobromic acid was used, since methanol attacks the photoresist. The etch rates of the hydrobromic solutions for CdTe were found to be approximately 0.9 µm/minute and 3.5 µm/minute for 0.1% and 1.0% solutions, respectively. There is still a surprising lack of consensus on the exact effect of wet chemical etching on the surface morphology, stoichiometry and electronic properties of the HgCdTe surface. It is generally accepted that dilute bromine etchants such as bromine-methanol leave the surface enriched in both Te and Hg, and depleted in Cd. Consequently, a thin layer, approximately 20 Å thick, of TeO 2 forms when the surface is exposed to air [13]. The alternative to wet chemical etching is dry etching in the form of reactive ion etching (RIE), electron cyclotron resonance (ECR) plasma etching, inductively coupled plasma (ICP) etching, and ion milling. These etching techniques are used extensively in Si and III-V device processing since they offer distinct advantages over wet etching. These advantages include anisotropic etching, which is critical for dimensional control, greater uniformity, and reduced amounts of hazardous waste [16, 17]. The application of dry etching to HgCdTe device technology is still very limited due to the induced crystal damage and modifications of important material properties induced by these processes. The RIE plasma-induced type conversion process used for photodiode fabrication is an example of what is generally an inadvertent side-effect of dry etching on HgCdTe. The development of dry etching technology suitable for delineating structures in HgCdTe will become increasingly important for the integration of devices in higher-density arrays and more innovative device structures, such as multi-spectral sensors. As mentioned previously, HgCdTe is easily damaged by exposure to high temperatures due to weak bonding of Hg in the crystal lattice: hence, all processing steps used in this thesis were kept below 85 C, except for the CdTe passivation layer deposition, where the temperature of the sample during CdTe deposition and preheating treatments was well above 85 C in order to obtain improved surface passivation properties. Note that this is carried out under high 26

39 Chapter 2 Device Fabrication Technology vacuum conditions and prior to junction formation. HPR photoresist was used in all photolithography processes with modifications to the standard baking times and temperatures. The photoresist was spun onto the wafers at 4000 rpm, pre-baked at 85 C for 60 minutes in an oven before UV exposure and development, and post-baked at 85 C for 60 minutes. For lift off, the photoresist was spun on at 2000 rpm and baked at 85 C for 30 minutes before UV exposure and development. A post-bake was not incorporated in this case in order to facilitate lift-off. 2.4 Surface Passivation Considerations To a large extent, the operating principles of solid-state semiconductor devices are based on the control of the band structure and electronic states within the semiconducting material and at interfaces and boundaries between different materials. The semiconductor surface is one such important boundary, whose properties must be controlled to enable successful device operation. In the band structure formulation, even for a perfect semiconductor surface, the abrupt change due to the periodic crystal lattice termination results in a band structure at the surface which is different to the band structure within the material. This results in additional energy states at the surface which are at different energies to those in the bulk due to the incomplete or dangling bonds at the surface, and leads to surface band-bending. For the case of incomplete bonds at the surface, it needs to be noted that a clean surface is highly reactive and will react with impinging foreign atoms if not maintained in a vacuum. By providing a compatible dielectric layer over the surface of the semiconductor, the incomplete bonds can be satisfied, and the band-bending minimised [18]. However, impurity atoms at the surface or any other defects will further modify the state of the surface. In addition to the surface states, trapped charges in the dielectric used to passivate the surface will also contribute to band-bending. Since the bandgap of LWIR HgCdTe is extremely narrow (~0.12 ev at 80K), very little band-bending is required to invert or accumulate the surface, making it very sensitive to conditions at the passivation/semiconductor interface. For an operating photodiode, the surface states can act as generation-recombination centres which have an adverse effect on 27

40 Chapter 2 Device Fabrication Technology device performance through increased dark current generation and 1/f noise. The negative effects due to surface states can be further compounded when they are combined with the effect of band-bending from fixed charges at the interface and/or within the passivation layer. One of the main purposes of surface passivation is to minimise the formation of surface states and to control the band-bending in the region near the surface. Passivation of the HgCdTe surface, particularly for LWIR material, presents a particularly challenging technological problem. The passivation of a semiconductor surface is generally achieved by either the growth of a native dielectric layer or by the deposition of a dielectric film over the surface. More recently, in-situ epitaxial growth of CdTe passivation has been reported, showing high performance in fabricated devices [19, 20]. Along with controlling band-bending and achieving excellent interface properties, for practical devices, the ideal passivation layer must also possess a number of other properties. These properties include the following [19, 21]: Adhesion: deposited dielectrics must adhere well to the HgCdTe surface and be mechanically stable. Thermal stability: the passivation layer must be thermally stable during subsequent device processing, and packaged device out-gassing and storage. Chemical stability: the passivation layer should be chemically stable and compatible with subsequent processing and packaging procedures. Dielectric properties: the material should have a high specific resistivity, and for front-side illuminated device structures, the passivation layer needs to be transparent to the wavelengths to be detected. Insulating properties: the passivating layer should also possess excellent insulating properties to electrically isolate contacts, p-regions, n-regions and adjacent devices. A material with a wide bandgap would satisfy this requirement. Figure 2.5 illustrates a typical semiconductor passivation system, showing the possible charge centres in the passivating dielectric and at the interface. The notation is borrowed from 28

41 Chapter 2 Device Fabrication Technology Fig. 2.5 Possible charge centres for the semiconductor surface passivated with a dielectric and the resultant interface states and surface band-bending. the Si-SiO 2 material system, with Q representing the charge density (Ccm -2 ), N the density of state/traps (cm -2 ), and D the energy distribution of the states/traps (cm -2 ev -1 ). Ionized impurity charge centres may be mobile through the dielectric, which can cause instabilities and the electrical behaviour of devices to vary over time. Such charges can also gather preferentially in certain regions, causing non-uniformity in the characteristics of devices depending on their physical location. Sodium ions were the main mobile contaminant identified in the SiO 2 -Si system, which required a considerable research effort to overcome and, eventually, achieve successful passivation of the Si surface [22]. Trapped charges in the dielectric can be created by high-energy radiation such as x-rays or hot electron injection, and dielectric fixed charges are localised charge centres in the passivation layer. Typically, such traps cannot change their charge state by the exchange of mobile carriers with either the underlying semiconductor or any overlaying metal layer. Interface trap charges are localised charge centres at the passivation/semiconductor interface that can change their charge state by exchange of mobile carriers with the semiconductor material. The charge state is changed whenever its position is changed relative to the Fermi energy level. Both fixed charges and interface trapped charges are caused by defects related to the crystal structure of the interface and the passivating dielectric, 29

42 Chapter 2 Device Fabrication Technology Fig. 2.6 Band diagrams illustrating the possible semiconductor surface bandbending scenarios for a p-type semiconductor. and are very sensitive to processing techniques and conditions used to form the passivation layer. The impact of passivation layer charge on the underlying semiconductor is shown in Figs. 2.6 and 2.7, which illustrate the case for a p-type semiconductor. Figure 2.6 shows the band-bending associated with the various equilibrium conditions of flat-band, accumulation, depletion and inversion. Flatband conditions occur when the bands at the surface terminate at the same level as in the bulk (Fig. 2.6(a)). A termination of the crystal lattice at the surface/interface generally means that there must be some degree of band-bending. Therefore, obtaining flatband conditions requires a balance of charges from the other charge sources. When a net positive charge is present in the passivation layer, the semiconductor bands bend downwards, and the surface becomes depleted (negative space-charge) for a p-type semiconductor as shown in Fig. 2.7(c). If the level of negative charge induced in the semiconductor is high enough, the bands bend further and an inversion layer forms at the p-type semiconductor surface (see Fig. 2.7(d)). When the passivation is negatively charged the bands bend upwards and the surface becomes accumulated (positive space-charge) for a p-type semiconductor, as shown in Fig. 2.7(b). The above description applies for a p-type semiconductor, as illustrated in Fig For an n-type semiconductor, positive charge would deplete and eventually invert an n-type surface, and negative charge would accumulate the surface. 30

43 Chapter 2 Device Fabrication Technology Fig. 2.7 The effect of charge and semiconductor surface band-bending on a planar n-on-p junction. Although the junction in the bulk region is unaffected, the field induced junction at the surface varies markedly, depending on the polarity and density of the charge in the passivation and at the interface. The effect of interface and passivation layer charges on surface band-bending in relation to an n-on-p junction is illustrated in Fig Under flatband conditions there is no bandbending at the surface, and the junction depletion region terminates at the interface with the same cross-sectional area as in the bulk (see Fig. 2.7(a)). The surface area of the depletion region at the interface is important since it determines the level of surface generationrecombination (g-r) dark current in the photodiode due to interface states acting as g-r centres. The magnitude of the surface g-r dark current component is given by Eqns. 2.1 and 2.2, where, c p and c n are the capture coefficients of holes and electrons, respectively, A S is the area defined by the product of the depletion width of the junction where it intersects the surface, and the perimeter of the n-type/p-type region, and s 0 is the surface recombination velocity given by Eqn. 2.2, where N SS (E) is the density of surface states (cm -2 ev -1 ) [23]. I S = (2.1) qns i 0A s 31

44 Chapter 2 Device Fabrication Technology s 0 E C NSS ( E) = de (2.2) 1 E Ei 1 Ei E E V cp exp + cn exp kt kt Positive charge in the passivation can deplete the surface in the p-type region, increasing the surface g-r current through an increase in A s. A depletion region is also formed below the surface which increases the bulk g-r current component due to Shockley-Read-Hall centres in the depletion region. This dark current component is given by Eqn. 2.3 [23] where W C is the width of the depletion channel formed under the surface, A C is the channel area, and N t is the density of g-r trap centres in the bulk. I SC = 1 2 qn A W i C C ( cn) + ( cn) 1 1 p t n t (2.3) If there is sufficient positive charge in the passivation layer the HgCdTe surface becomes inverted and the formation of the n-type field-induced channel can short adjacent devices, as shown in Fig. 2.7(d). A negatively charged passivation layer causes accumulation of the p-type region of the HgCdTe surface and a narrowing of the depletion width at the surface as shown in Fig. 2.7(c). The high electric field where the depletion region narrows enhances tunnelling and other breakdown mechanisms. The surface region may also enter a state of deep depletion, whereby with increasing applied positive charge on an overlapping electrode (underlying p-type material is assumed), an electron inversion layer takes time to form or is prevented from forming by charge escaping through the leaky passivation layer to the electrode. If the generation rate is sufficiently low then the depletion will extend deeper with increasing charge on the electrode. As all tests in this work are undertaken at DC bias, temporal deep depletion is not an issue. While leakage induced deep depletion is possible, it essentially describes a defective device with a leaky passivation layer, and therefore will not be considered further. The effect of the configuration of the junction, passivation and overlapping metal contact for the fabricated photodiodes on the surface leakage currents can be readily compared 32

45 Chapter 2 Device Fabrication Technology Fig. 2.8 The comparative effect between a metal contact layer and a dielectrics layer on surface band-bending for a p-type HgCdTe surface passivated with CdTe [21]. to the currents induced in a gated diode. In a gated diode the potential at the surface is controlled by applying a bias on the gate. Because of the narrow bandgap of LWIR HgCdTe, the metal work function can have a dramatic effect on passivated surfaces over which a metal has been deposited. The passivation charges and difference in work function of the contact metal and the HgCdTe are often sufficient to induce accumulation or inversion of the surface. In fact, it has been theoretically demonstrated that a contact layer alone can invert a p-type HgCdTe material surface given a 0.2 µm CdTe passivation layer as shown in Fig. 2.8 [24]. The effect of the various charging/biasing conditions on the surface leakage current components is shown in Fig For this work, all HgCdTe surfaces were passivated with either thermally deposited ZnS or CdTe. For ZnS deposition, the temperature of the sample was raised to 60 C before deposition by thermal evaporation from a ZnS source at a rate of Å/s. The vacuum pressure was below 10-6 mbar before evaporation was commenced. Deposition of the CdTe was performed using thermally evaporated CdTe from a CdTe source. The pre-deposition heat treatments and deposition temperatures were varied in an attempt to optimise the conditions, which are summarised in Table

46 Chapter 2 Device Fabrication Technology Fig. 2.9 Photodiode dark current generated in the surface region as a function of p-type surface potential for an n-on-p device. The deposition of ZnS or CdTe for surface passivation has been proven to produce state-of-the-art MWIR devices [9, 25]: however, it is shown in this work that the same techniques when applied to LWIR material produce devices that are dominated by surface effects. ZnS was one of the earliest materials used to passivate HgCdTe surfaces. It has been reported that with appropriate surface pre-treatments, the surface can be passivated with slow trap densities below cm -2 and fixed interface trap density below cm -2, but interface trap density is still high at cm -2 ev -1 [26]. CdTe passivation is currently favoured by industry for photodiode fabrication, with the best results being reported for in-situ grown layers. The evaporation technique employed in this work is expected to form polycrystalline to amorphous CdTe layers. Growth of crystalline CdTe 34

47 Chapter 2 Device Fabrication Technology is expected to occur only for temperatures above approximately 250 C. Significant results reported on CdTe passivation include the following: Developments in molecular beam epitaxy (MBE) and metal-organic chemical vapour deposition (MOCVD) have enabled growth of CdTe epilayers on HgCdTe. The close lattice matching of the CdTe to HgCdTe should result in high quality interface and low surface recombination velocities. The CdTe should also minimize Hg segregation in HgCdTe solid solutions [27]. In-situ growth of CdTe also avoids contamination of the passivant/semiconductor interface. Work reported in Ref. [20] on MOCVD epitaxial growth of HgCdTe and CdTe indicates that 3000 Å is the optimal thickness of the CdTe layer, with thicker layers resulting in hillock defect formation. A surface recombination velocity of 5000 cm.s -1 at 77 K was obtained, lower than for ZnS passivated surfaces and two orders of magnitude lower than freshly etched surfaces. The calculations in Ref. [20] show that a cm -3 p-type doping of the CdTe can yield flatband conditions and is achievable for x=0.22 HgCdTe by heat treatment which enables vacancies in the HgCdTe to diffuse into the CdTe. It also concluded that continuous in-situ growth of the CdTe is essential as there is a strong thermodynamic driving force for segregation of Hg which moves to the surface, reducing the bandgap at the surface. Also, heat treatments performed on bare HgCdTe surfaces create an inversion layer originating from induced structural defects, and cannot be annealed out. In-situ grown CdTe and non-in-situ grown CdTe passivation was compared by Ref. [28] which concluded that although it is possible to obtain near flatband conditions for indirectly grown CdTe, there are greater numbers of slow interface traps for indirectly grown when compared to in-situ grown CdTe. A ZnS overcoat combined with CdTe passivation scheme may be beneficial as CdTe achieves better interface properties while the ZnS improves the flatband conditions by compensating for the band-bending from the CdTe [25]. 35

48 Chapter 2 Device Fabrication Technology For this thesis, a range of surface preparation and passivation techniques were implemented for the various device lots as indicated in Table 2.1. It can be seen that thermally deposited ZnS and CdTe are passivation materials used. The deposition conditions are also detailed because variations in these parameters can have a significant effect on final device performance due to the narrow bandgap of LWIR HgCdTe. The effectiveness of the various techniques is evaluated in Chapter 4. The rationale for implementing the variations in passivation deposition conditions are as follows: Using the available facilities for ZnS deposition, the temperature of the sample unavoidably increases as the deposition progresses. Therefore, to minimise the range of deposition temperature, ZnS passivated samples are preheated to 60 C prior to deposition. The high substrate temperature also aids in the adhesion of ZnS to the HgCdTe surface. There is trade-off between preheated substrate temperature and the need to keep processing temperatures low to minimise possible defect formation. CdTe passivated samples were preheated to 180 C and maintained for 15 minutes in the deposition chamber. The deposition of the CdTe is subsequently performed at a controlled substrate temperature of 100 C for device lots TN6 TN13. Etching of the HgCdTe with Br 2 -methanol is thought to leave the surface rich in Te. Heating the sample at 180 C for 15 minutes is designed to allow the excess Te to separate into its metallic form and leave the surface. For device lots TN14 and TN15, the CdTe deposition is performed at 250 C as opposed to the other device lots which had CdTe deposited at 100 C. The 250 C deposition is designed to produce a CdTe layer with higher crystallinity. The CdTe deposition for device lot TN15 was performed with a Hg flux in the chamber in an attempt to improve the CdTe/HgCdTe interface and crystallinity of the passivation layer. The exposure of the freshly etched HgCdTe surface to the atmosphere is further minimised for device lots TN11, TN13 and TN15. Following the short etch-back of 36

49 Chapter 2 Device Fabrication Technology the surface using a dilute (0.01%) Br 2 -methanol solution, these wafers were left soaking in deionized water for approximately one hour before being immediately transferred to the N 2 filled load lock of the CdTe deposition chamber and dried with N 2. Previously, after the surface etch-back, device lots were left exposed to the atmosphere for up to two hours before being placed under vacuum in the deposition chamber. 2.5 Junction Formation Technology The junction formation technology employed in any photodiode fabrication process has a major influence on the required downstream processing and final device structure. In-situ grown n-p junctions generally require mesa delineation to isolate devices, a step which exposes the junction edge and potentially lead to increased leakage currents in the final device. The planar device is perhaps the simplest structure to fabricate. It requires the formation of junctions by type converting regions in the HgCdTe epilayer from p-type to n-type or vice versa. There have been numerous techniques developed to type convert HgCdTe, including the RIE plasmainduced type conversion process used to fabricate the photodiodes in this thesis. The various other type conversion technologies include [23, 29-35]: Ion implantation Ion beam milling Diffused dopants Electron irradiation Pulsed laser radiation Detailed knowledge of the type conversion processes in HgCdTe is still not completely understood but the role of the weakly bonded Hg atoms in the crystal lattice is believed to play an important role in all the p-to-n type conversion technologies. Hg vacancies act as acceptors and p-type material can be grown by incorporating Hg vacancies forming so-called vacancy doped material. Processes such as ion implantation, ion beam milling and RIE plasma 37

50 Chapter 2 Device Fabrication Technology processing readily liberate Hg at the surface which can then diffuse into the material to annihilate the vacancies and reveal any background n-type doping. The role of Hg interstitials is believed to be unimportant as donors. Dislocation damage may also act to annihilate vacancies. [23] Presently, the most common junction formation technologies for commercial photodiode array fabrication use ion implantation or ion-beam-milling-induced type conversion. Ion implantation is able to produce both n-on-p and p-on-n devices with acceptor implant species typically being P, As, or Au; and donor implant species being Al, In, B or Cl. In the ion implantation process, the role of the implanted species, as well as the liberated Hg in-diffusing from the surface, induced lattice damage and dislocations must all be considered. The process also requires a high-temperature anneal to activate the dopants and repair any induced crystal damage. Type conversion of p-type vacancy doped HgCdTe using ion beam milling has been used for commercial array fabrication since the late 1970s [23]. The model used to describe the ion beam milling induced type conversion process states that the ion milling of the surface liberates Hg atoms which move into the material to neutralise any Hg vacancies, leaving a background doping which is usually n-type. The exact mechanism for RIE plasma-induced type conversion is presently unclear. A model based on the ion beam milling model is inadequate as it has been shown that the RIE plasma process can type convert HgCdTe doped with extrinsic impurities such as Au and As [10]. RIE Plasma-induced Type Conversion Conceptually, an RIE system consists of two parallel plate electrodes, one of which is powered by an RF source while the other is grounded. Between the plates a gas mixture flows and a plasma is initiated when the RF power is sufficient to ionise the gas molecules. A typical RIE configuration is shown in Fig. 2.10, where the electrodes form a chamber that confines the plasma. The powered electrode is smaller than the ground electrode and also acts as a sample 38

51 Chapter 2 Device Fabrication Technology Gas Flow Control Sheath region Ground Electrode Plasma Sample Powered Electrode RF Fig A typical configuration for a RIE system. stage. The following description of the plasma is taken from Ref. [36]. A plasma can generally be described as a collection of charged particles where the long-range electromagnetic fields set up collectively by the charged particles have an important effect on the particles behaviour. In the case of RIE, the plasma consists of the partially ionised gas mixture under the influence of electric fields. The electric field is created because the electrons are able to move faster than the positive ions allowing them to better respond to the RF signal from the electrodes. The fast moving electrons will reach the chamber walls/electrodes before the ions, charging them negatively. The negatively charged walls will repel further electrons while simultaneously attracting positive ions. As electrons are repelled from the walls, the region close to the wall will be depleted of electrons. This positively charged region is referred to as the sheath. The electric fields in the sheath are very strong and any ions which reach this region are accelerated towards the walls or sample surface. The strong acceleration ensures that the ions are incident on the sample almost normal to the surface. For a given RF power and gas flow, an equilibrium state will be reached where the sheath maintains a DC bias voltage and the electrons and positive ions reach the walls at the same rate. The uniform direction (normal to the surface) of the incoming ions and the high velocity of the incoming species driving the chemical and sputtering process are the primary reason why plasma processes are used in the semiconductor industry. These plasma properties create 39

52 Chapter 2 Device Fabrication Technology conditions which are not encountered under equilibrium conditions. Other processes which may occur when a plasma is incident on the sample include induced damage to the crystal lattice, heating of the surface, the ion being implanted in the material, and the formation of polymers on the surface. Etching of the semiconductor by RIE proceeds through both sputtering of material from the surface and chemical reactions involving the plasma ion species and the material surface. There is a trade-off between chemical and physical etching mechanisms, which can be varied by varying the plasma generation conditions. The normal incidence of the impacting ions enable steep trenches to be etched since the direction of the ions dictates that it is much more likely to hit the bottom of the trench than the side walls. The directional etching is termed anisotropic, as opposed to isotropic etching encountered in most wet chemical etching processes (there are exceptions where a wet chemical etch will preferentially etch along a particular crystal plane). For this work the goal of RIE plasma processing is not to etch HgCdTe but to type convert selected p-type regions to n-type in a controlled manner, so as to form an n-on-p junction. To achieve this, an appropriate set of parameter settings must be determined to produce a type converted region with the desired properties. For all devices fabricated as part of this thesis the plasma type conversion processing conditions were kept constant. These conditions were determined based on results from work on MWIR HgCdTe devices previously performed within the group at UWA [9, 10, 15, 37], which was initially based on Ref. [38]. Further studies on the plasma-induced type conversion produced by these conditions using magnetic field dependent Hall effect and resistivity measurements have also been carried out, and the results are presented in the next chapter. The conditions of the RIE plasma type conversion processing are: The RIE system used was a Plasma Technology RIE80 system. CH 4 -H 2 gas chemistry. H 2 :CH 4 gas ratio of approximately 4:1. Gas flow rate of 54 sccm for H 2 and 15 sccm for CH 4. 40

53 Chapter 2 Device Fabrication Technology 90W RF power at MHz. Sample stage temperature was C. Plasma process time was 2 minutes. The CH 4 -H 2 gas chemistry has been shown to etch HgCdTe, producing atomic hydrogen, organic radicals and ions which react with the HgCdTe surface to produce volatile methyl and hydride compounds [39]. The etch rate for HgCdTe for the above conditions is approximately 0.12 µm/min. The by-products which have been detected coming from a HgCdTe sample during etching are elemental Hg, TeH 2, Te(CH 3 ) 2 and Cd(CH 3 ) 2 [40]. There is also an advantage in using a CH 4 -H 2 gas chemistry as the products involved are less toxic and less corrosive compared to halogen based chemistries [17]. The gas composition, or ratio of H 2 to CH 4, is important since the concentration of methyl radicals in the plasma determines the formation of hydrocarbon polymers which deposit on the sample and walls of the chamber. The formation of the polymer can mask the surface from the etching/type conversion action of the plasma. One method of suppressing the formation of polymer is to increase the ratio of H 2 since CH 2 and CH are precursors of the polymers. The RF power is an important parameter in RIE because it can control the energy of the accelerated ions impacting on the sample surface. The induced DC bias of the sheath region determines the energy imparted to the ions which is dependent on the density of the ionised species in the plasma. Hence, for a given process pressure, the RF power will determine the ionisation rate and therefore the DC bias. Generally, a lower process pressure requires a larger RF power to maintain the plasma, which increases the energy of ions incident on the sample surface. This fact gives importance to the flow rates of the gases which contribute to the total process pressure. Considering the previous points together, it can be seen that obtaining the correct process pressure, RF power and gas ratio is vital because it determines the proportion of chemical and physical bombardment mechanisms, and also controls the formation of polymers. 41

54 Chapter 2 Device Fabrication Technology These factors influence the type conversion mechanisms, the depth of type conversion, the level of induced damage, and whether the sample will be left contaminated with polymer deposits. As previously mentioned, the type conversion mechanisms involved with RIE plasma processing are still not well understood. In Refs. [23, 41] it is proposed that the mechanisms involved in the type conversion of p-type HgCdTe by RIE, ion beam milling, and ion implantation without an anneal, are all the same. That is, the in-diffusion of Hg liberated from the surface during etching acts to annihilate vacancies. Dislocations may also play a part in annihilating vacancies, and an impurity sweep-out effect occurs in the converted volume induced by the ion beam. Reference [42] proposes that hydrogen may also play a role in the type conversion process based on experimental SIMS profiling results. This model proposes that hydrogen is incorporated as three species, one associated with the lattice damage/hg interstitials, another associated with the neutralisation of acceptors, and a fast diffusing but inactive hydrogen species. Strong evidence confirming one or other of the various models of RIE induced type conversion are yet to appear in the open literature. 2.6 Contact Formation Obtaining ohmic contacts is important to the performance of individual devices, and as part of a focal plane array, because non-ohmic contacts can mask the junction behaviour and also result in poor noise performance. Ohmic metal contacts are easily obtained on n-type HgCdTe material but contacts to p-type material tend to be rectifying. The processes for creating contacts to p-type material are a commercial secret with most manufacturers [43]. The n-on-p device structure of diodes produced by the fabrication technology presented here requires only one common p-contact, making the formation of an ohmic contact much easier. The technique used to achieve an ohmic p-contact was to make the contact area large and also to physically damage the surface under the contact to enhance tunnelling and other leakage currents. A double layer of thermally deposited Cr/In or Cr/Au was used to form both n-type and p-type contacts for the photodiodes fabricated in this thesis. 42

55 Chapter 2 Device Fabrication Technology 2.7 Chapter Summary and Conclusions Fabrication of HgCdTe photodiodes using plasma-induced p-to-n type conversion has inherent advantages over the traditional methods of ion implantation and ion beam milling. This technology neither detrimentally damages the HgCdTe crystal structure nor the semiconductor surface passivation layer, hence a high-temperature anneal to activate dopants and repair crystal damage is avoided, and the need for removal and re-application of the surface passivation is also avoided. Due to the low damage threshold and narrow bandgap of HgCdTe, particularly LWIR HgCdTe, high-temperature processing and exposure of the junction to ambient conditions can potentially lead to defect formation and negatively impact on device performance. While junction formation using the plasma induced p-to-n type conversion technology can avoid significant downstream processing limitations, the nature of HgCdTe still mandates strict processing requirements at all other stages of device fabrication to enable a highperformance and high-yield LWIR HgCdTe fabrication technology. In the realisation of the advantages and simplifications afforded by the plasma-induced junction formation technology when applied to narrow bandgap of LWIR HgCdTe, the passivation of the surface becomes the most critical fabrication step and also the most challenging. This factor will be elaborated upon and be shown to be the case in the chapters to follow. 43

56

57 3 Characterisation of the Carrier Transport Chapter 3 Properties of Plasma-induced p-to-n Typeconverted Layers in HgCdTe Characterisation of the Carrier Transport Properties of Plasma induced p to n Type converted Layers in HgCdTe Characterisation of the carrier transport properties in semiconductor materials is important in many phases of device development since it provides essential information for refinement of the fabrication processes and for modelling of device performance. RIE plasmainduced p-to-n type-conversion of HgCdTe shows great potential as a junction formation technique in the fabrication of HgCdTe photodiodes, and the virtues of this junction formation technique were presented in detail previously in Chapter 2. Although photodiodes with state of the art performance and fabricated using plasma-induced junction formation have been reported [9, 25, 44], very little detail has been reported in the open literature on the effect of this typeconversion process on HgCdTe epilayers and the properties of the type-converted material. This chapter aims to add to the knowledge in this area by examining the transport properties of p-to-n type-converted HgCdTe epilayers resulting from RIE plasma processing. Reports on the transport properties of p-type HgCdTe are also quite rare since p-type samples invariably show mixed conduction from both electrons and holes. This deficiency in HgCdTe transport data is also addressed by analysis of variable magnetic field resistivity and Hall effect measurements. The transport properties of a semiconductor material are characterised by the carrier type, the carrier concentrations, and their associated mobilities. These properties are usually determined via resistivity and Hall effect measurements. However, when multiple carrier species are present in a sample, magnetic field dependent Hall effect and resistivity data is required in order to identify and distinguish between all the carriers present. For this thesis, variable magnetic field resistivity and Hall effect data were collected and analysed using the Quantitative Mobility Spectrum Analysis (QMSA) [45-48] technique, which allows the transport properties of the individual carrier species present in a sample to be determined. 45

58 Chapter 3 Characterisation of the Carrier Transport Properties 3.1 The Hall Effect The Hall effect is explained with reference to Fig Under the influence of the applied electric field along the x direction (E x ), positive charge carriers (holes in semiconductors) will flow in the x direction. The application of a uniform magnetic field (B z ) in the z direction results in a force acting on the moving charge carriers which is perpendicular to B z and the drift velocity (v x ). This force is termed the Lorentz force (F B ) and is given by Eqn. 3.1, where q is the electronic charge: FB = qbz vx (3.1) The deflection of the positive charge to one edge of the sample by F B sets up an electric field in the y direction which will oppose further deflection of charges by the Lorentz force. In the case of negatively charged electrons, electrons will deflect in the opposite direction to that indicated for holes in Fig Under steady-state conditions, the Lorentz force and the electrostatic force will balance and result in zero current in the y direction (J y = 0) and a constant Hall voltage (V y ) which can be measured with a suitable voltmeter. The balancing of the two forces under steady-state conditions is expressed in Eqn qbz vx q y = E (3.2) where E y is the electric field along the y direction. Using J x = qpvx where p is the hole carrier density, Eqn. 3.2 can be rewritten as Eqn. 3.3 where R H is called the Hall coefficient. For electrons as carriers, p can be substituted with n, the electron carrier density. E = R JB (3.3) y H x z Substituting Eqn. 3.2 into Eqn. 3.3 leads to Eqn. 3.4, which indicates that the Hall coefficient can be experimentally determined since E y, B z and J x can all be directly measured. Therefore, obtaining the Hall coefficient through measurement of E y, B z and J x allows the carrier density (p) to be determined from: R H Ey vx 1 = = = B J J qp z x x (3.4) 46

59 Chapter 3 Characterisation of the Carrier Transport Properties B z y x + F B F E V y v x - z + I x J x E x Fig. 3.1 The Hall effect as illustrated for a bar sample. The direction of the various vector quantities are indicated by the arrows and a description is given in the text. The induced voltage assumes positively charged carriers. The resistivity (ρ) of the bar sample can be determined by measuring the current density (J x ) and the electric field (E x ), as indicated by Eqn. 3.5, where σ is the conductivity. σ = qpµ σ = qnµ 1 J x σ ρ = = E x for holes, where p is the hole density for electrons, where n is the electron density (3.5) (3.6) Since conductivity is proportional to the carrier density-mobility product as given by Eqn. 3.6, Eqns. 3.4 and 3.5 can be used together to determine both the carrier density and the mobility. The sign of the Hall coefficient will distinguish between whether the carriers are holes or electrons, with a negative R H resulting from electrons and a positive R H resulting from holes. 3.2 Van der Pauw Configuration For illustrating the Hall effect and resistivity measurements, the bar sample configuration of Fig. 3.1 is most convenient, but in reality the van der Pauw measurement technique is most often used due to easier sample preparation. Preparation of bar-shaped 47

60 Chapter 3 Characterisation of the Carrier Transport Properties C D A B Fig. 3.2 The van der Pauw configuration for Hall effect and resistivity measurements can be achieved by placing four edge contacts, A to D, on an arbitrary shaped sample. Although the shape of the sample and the position of the contacts can be arbitrary, particular shapes and contact configurations can help reduce measurement errors. w samples, particularly for Hall measurements, requires geometric precision of contact positions to ensure accurate measurements. The van der Pauw method is based on the theorem published in 1958 by van der Pauw [49] whereby, for a plane lamina of arbitrary shape, containing no holes and of uniform thickness with four line contacts as in Fig. 3.2, the resistivity can be determined as follows. Resistance values are defined as in Eqn. 3.7, where the first two letters in subscripts indicate the contacts between which the voltage is measured (AB in this case) and the second pair of letters in the subscript indicate the contacts through which the current is passed (CD in this case). Van der Pauw showed that Eqn. 3.8 holds for the lamina, and that the resistivity can be obtained by Eqn R ABCD V I AB = (3.7) CD πrabcdw πrbcdaw exp + exp = 1 ρ ρ (3.8) 48

61 Chapter 3 Characterisation of the Carrier Transport Properties f Q Fig. 3.3 A plot of f as a function of Q from Eqn πw RABDC + RBCDA ρ = f Q ln 2 2 RABCD where Q = R BCDA ( ) (3.9) Q 1 f( Q) 1 1 ln2 = cosh exp Q+ 1 ln2 2 f( Q) (3.10) f(q) is defined by Eqn 3.10, which is plotted in Fig Evaluation of the resistivity can be simplified by ensuring that f( Q) 1. This is easily achieved by preparing a symmetric sample which will give Q 1. Referring back to Fig. 3.2, the resistivity is determined by passing current through adjacent contacts and measuring the voltage between the remaining contacts. For example, current is forced between CD and voltage is measure between AB in Fig This method of determining the resistivity should exclude the effect of contact resistance because in the determination of the intermediate R αβγδ values, the forcing current is not passed through the same contacts used to measure the voltage. Hall voltages are measured by applying a current through diametrically opposite contacts (AC, for example) and measuring the voltage between the two remaining contacts (BD). Again, the effect of contact resistance is excluded because the 49

62 Chapter 3 Characterisation of the Carrier Transport Properties forcing current is not passed through the contacts used to measure the voltage. The Hall coefficient is then determined by Eqn. 3.11, with R BDAC determined as in Eqn W VBD RH = RBDAC, where RBDAC = B I x AC (3.11) The van der Pauw method calls for the use of line edge contacts which may not be achievable in practice, especially for epitaxial film samples. The result is that there will be errors in the value of resistivity obtained. The magnitude of the errors is strongly dependent on the geometry of the sample but accuracy to within 1% can easily be attained [50]. 3.3 Analysis of Multicarrier Systems The analysis of carrier transport properties from Hall effect and resistivity data using the relations for R H and ρ given above assumes that a single carrier species is responsible for conduction in the material. Carriers with differing mobility will have different drift velocities; hence, under a given magnetic field, the different carriers will experience a different deflection force. The result for samples with multiple carrier species is that measurement of R H and ρ will vary depending on the applied magnetic field. Simply using Eqn. 3.9 and Eqn will yield a single value for mobility and carrier density which, at best, represents an average over all carrier species present, with the values of mobility and carrier density dependent on the value of magnetic field chosen. With Hall effect and resistivity measurements taken at multiple magnetic field points, it is possible to differentiate between the various carrier species and to extract their individual mobilities and densities. To characterise type-converted HgCdTe samples, the ability to identify and differentiate between multiple carrier species is essential since it is expected that a RIE plasma-induced type-converted HgCdTe sample will have p-type conduction within the remaining unconverted regions and n-type conduction from multiple electron carrier species in the type-converted regions. For multicarrier analysis it is more useful to reformulate the relations, R H and ρ, in terms of the conductivity tensor, since it is more amenable to numerically extracting the carrier 50

63 Chapter 3 Characterisation of the Carrier Transport Properties density and mobility of the individual carrier species. In a given sample, the current density (J) is related to the electric field (E) via the conductivity tensor (σ) as given by Eqn. 3.12: J = σe (3.12) For a sample arranged as in Fig. 3.1, flat and isotropic in the x-y plane, the conductivity tensor can be simplified to Eqn in the x-y Cartesian coordinates. That is, the current density components in the plane of the sample can be related to the electric field in the plane of the sample by the two unique components, σ xx and σ xy, of the conductivity tensor, and there is zero current density and zero electric field in the z direction. σxx σ = σ xy σ σ xy xx (3.13) The resistivity and Hall coefficients are related to the components of the conductivity tensor by Eqn and Eqn. 3.15: σ xx ρ( ) B = 2 2 σ xx + σ xy (3.14) R H ( B) = 1 σ B σ xy 2 2 xx + σ xy (3.15) Eqn and Eqn can be inverted to obtain expressions for the conductivity tensor components, given in Eqn and Eqn 3.17: 1 σ xx ( B) = H ρ( B) 1+ σ xy ( B) = ρ R 2 R ( B) B ρ ( B) ( B) B H 2 2 R H ( B) B ( B) 1 + ρ ( B) (3.16) (3.17) 51

64 Chapter 3 Characterisation of the Carrier Transport Properties 3.4 Quantitative Mobility Spectrum Analysis Analysis of the magnetic field dependent resistivity and Hall effect data was accomplished using Quantitative Mobility Spectrum Analysis (QMSA) [45-47]. The QMSA procedure uses numerical fitting algorithms to transform the experimental data, in the form of the conductivity tensor, into an electron mobility spectrum and a hole mobility spectrum. A mobility spectrum gives the conductivity density as a function of mobility. The QMSA procedure used for this work was implemented in the form of a computer program. The numerical nature of the procedure produces a conductivity density function (mobility spectrum) of discrete mobility values. An example of a set of mobility spectra obtained using QMSA with synthetic data is shown in Fig. 3.4 [48]. In this case, the sample is interpreted as having two carrier species present, a hole species with peak mobility at cm 2 V -1 s -1 and an electron species with peak mobility at cm 2 V -1 s -1. QMSA is able to show the distributed nature of the carrier mobilities, but it is sometimes useful to summarise the results via a single value for carrier mobility and a single value for carrier density. To achieve this, some interpretation is required to determine which region of the mobility spectrum belongs to which carrier species. In the case of Fig. 3.4 it is obvious that conductivity components between cm 2 V -1 s -1 to cm 2 V -1 s -1 belong to a single hole carrier species, and the other carrier species consists of an electron conductivity component between cm 2 V -1 s -1 and cm 2 V -1 s -1. To assign a representative value for mobility, a weighted average approach was taken. The mobility at each point in the spectrum was weighted with the conductivity value for that point and the average taken for all values belonging to each carrier species. Representative values of carrier density are calculated using Eqn. 3.18, in which σ i is the conductivity of the ith point in the mobility spectrum and µ i is the associated mobility. The sum is taken over all points belonging to that carrier species. n i = (3.18) i σ qµ i 52

65 Chapter 3 Characterisation of the Carrier Transport Properties conductivity (1/(ohm cm)) Holes Electron mobility (cm^2/vs) Fig. 3.4 An example of the mobility spectrum produced by QMSA from synthetic data showing an electron species at cm 2 V -1 s -1 and hole species at cm 2 V -1 s -1. [43] 3.5 Sample Preparation and Experimental Setup The study of the carrier transport properties of RIE plasma induced p-to-n typeconverted layers in HgCdTe used liquid phase epitaxy (LPE) HgCdTe grown by Fermionics Corporation on lattice matched CdZnTe substrates as the starting material. The initially p-type material was either extrinsically doped with Au or vacancy doped. Both LWIR and MWIR material compositions were examined. The details of the samples are summarised in Table 3.1. All samples were prepared by first cleaving a square piece of material with dimensions of approximately 5mm 5mm. The LW-Au3 sample was characterised prior to RIE plasma induced type-conversion to establish the carrier transport properties of the material before RIE plasma processing. The LW-Au3 sample was dip-etched in a dilute solution of brominemethanol (0.01% by volume) for 10s to remove possible surface contaminants. Indium was then pressed at the corners of the sample to form contacts. Au wire was then pressed into the indium contacts to connect the sample to the sample holder, which is then connected to the external instruments. The standard set of magnetic field dependant Hall effect and resistivity measurements were then conducted, the details of which are given later in this chapter. After the initial set of measurements, the LW-Au3 sample was removed from the sample holder, the contacts removed from the sample, and the sample cleaned in consecutive baths of hot 53

66 Chapter 3 Characterisation of the Carrier Transport Properties Table 3.1: Starting HgCdTe material parameters. Figures are specified by the manufacturer. Sample Epilayer Thickness (µm) x p-type Dopant p-type Doping Density (cm -3 ) LW-Au Au LW-Au Au LW-Au Au LW-Vac vacancy MW-Au Au MW-Vac vacancy mm Contact Area 0.80mm 0.40mm Fig 3.5 The design of the van der Pauw structure used for Hall and resistivity measurements. These were fabricated by mesa etching the HgCdTe epilayer down to the substrate. trichloroethylene, acetone and methanol. The LW-Au3 sample was then processed in the same manner as the other samples. All samples were firstly dip-etched in a dilute Br 2 -methanol (0.01%) solution to clean the surface which may have become non-stoichiometric or contaminated due to exposure to the atmosphere. The samples were then RIE plasma processed to induce the p-to-n type-conversion. The entire surface of the sample was exposed to the plasma under the same condition as used in the photodiode fabrication process: H 2 :CH 4 gas ratio of 4:1, RF power of 90 W, and processed for 2 minutes. 54

67 Chapter 3 Characterisation of the Carrier Transport Properties Following the plasma processing, photolithography was used to define a van der Pauw structure on the HgCdTe sample. A 1% Br 2 -HBr solution was used to mesa etch the HgCdTe epilayer down to the substrate. The van der Pauw structure defined was a cross as shown in Fig The cross structure was used because the errors introduced by non-ideal contact geometries can be kept very low. Ideally, the van der Pauw procedure calls for the use of line edge contacts, and departure from this condition will result in some errors. It has been calculated [50] that the error for the cross structure is given by Eqn. 3.19, where λ is the ratio between contact length (0.4 mm in Fig. 3.5) and total perimeter of the cross (8.0 mm in Fig.3.5). Using Eqn errors obtained for the structure of Fig. 3.5 are theoretically less than 0.001%. π Error = exp( ) (3.19) Thermal evaporation was used to deposit Au or In onto the contact areas to aid in obtaining and maintaining an ohmic contact to the sample, even with removal and reapplication of the connecting wires. Both Au and In gave similar electrical properties but In has better adhesion to the HgCdTe wafer. Bonding was completed by pressing indium onto the contact areas and attaching Au wires. To probe the conversion depth and doping profile of the type converted samples, differential Hall measurements were also conducted, using discrete etching steps. To obtain the differential Hall data, after each set of measurements a thin layer of material is required to be removed from the surface and measurements repeated for the new depth. This surface layer removal (etch back) was achieved by etching the sample in a 0.1% Br 2 /methanol solution. This concentration gives an etch rate of 0.6µm per minute at room temperature. The etch-back steps used were one or two minutes, with the longer etching time used when the change in the mobility spectra from previous etch back steps was small. λ 55

68 Chapter 3 Characterisation of the Carrier Transport Properties Keithley 220 Current Source LHe Supply Temperature Controller Cryostat Keithley 705 Scanner Keithley 706 DMM Sample Oxford Instruments 12T Superconducting Magnet Magnetic Field Supply Computer Control and Data Aquisition (a) Computer Controlled Scanner Sample (b) Current Source V DMM Fig. 3.6 Experimental setup for the variable magnetic field Hall effect and resistivity measurements. (a) shows how the instruments are connected and how the computer is used to control the magnetic field settings and coordinate the measurement procedure. The sample is connected to the Keithley 705 scanner equipped with a 7065 Hall effect card as shown in (b) and the appropriate measurement configuration is achieved by closing the appropriate cross-points. 56

69 Chapter 3 Characterisation of the Carrier Transport Properties The Hall effect and resistivity measurements were conducted using the setup shown in Fig The magnetic field is produced by an Oxford Instruments superconducting magnet capable of producing fields ranging from 0 to 12 T and a switching circuit to reverse the polarity of the magnetic field. The helium cooled cryostat can control the temperature of the sample from 300 K down to 15 K. The sample is connected to the digital multimeter (DMM) and current source via the scanner equipped with a Keithley Model 7065 Hall Effect Card. The measurement process is controlled by a computer which also sets the magnetic field and records the data. The field was set to range from -12 T to +12 T. The use of the scanner allows both resistivity and Hall effect measurements to be taken by reconfiguring the connection of the sample contacts to the external instruments as shown in Fig. 3.6(b). By selectively opening and closing the appropriate crosspoints, the current can be applied through any pair of contacts, in both the forward and reverse direction. The remaining pair of contacts can be connected to the DMM to measure the corresponding voltage. Resistivity measurements are taken by forcing current through every possible combination of adjacent contacts, in both the forward and reverse directions, and measuring the voltage across the remaining contacts for each configuration. To determine the resistivity, eight voltage measurements in total were taken at each field point. With every set of two voltage measurements the resistivity can be calculated from Eqn. 3.9, and the final value for resistivity can be obtained by finding the average value. By averaging multiple measurements, errors may be reduced. The Hall effect measurements are accomplished by applying the current through every possible combination of opposing contacts in both forward and reverse direction, and measuring the voltage across the remaining contacts. A total of four Hall voltages are measured at each magnetic field point. The Hall coefficient can be calculated from each voltage measurement using Eqn and a final Hall coefficient value can be obtained by averaging the calculated value. 57

70 Chapter 3 Characterisation of the Carrier Transport Properties Having obtained the resistivity and Hall coefficient data, the conductivity tensor components, σ xx and σ xy, were calculated using Eqn and Eqn These data were then analysed using the QMSA procedure to obtain the mobility spectra. 3.6 Results for LWIR Au Doped HgCdTe To confirm that the experimental results were repeatable, characterisation of three LWIR Au doped samples were completed. Two samples, LW-Au1 and LW-Au2, were prepared from the same wafer; whereas the final sample, LW-Au3, was prepared from a different wafer with similar doping density and x-value (refer to Table 3.1). The results from all three sets of measurements were consistent with each other but the LW-Au3 sample was characterised in greatest detail and is the one from which most of the presented results were obtained. The magnetic field dependent components of the conductivity tensor for the as-grown LW-Au3 sample at 67 K are shown in Fig The corresponding mobility spectra obtained from QMSA are shown in Fig Figure 3.7 shows that σ xy has both negative and positive values, indicating that there is conduction in the epilayer from both holes and electrons. This is confirmed by QMSA results as shown in the electron and hole mobility spectra of Fig 3.8. The notable features of the mobility spectra are that there is a significant electron conduction contribution just above cm 2 V -1 s -1 and a significant hole contribution at approximately 500 cm 2 V -1 s -1, these are interpreted as two separate carrier species. The small contribution at 1000 cm 2 V -1 s -1 is included as part of the hole carrier with peak conductivity at 500 cm 2 V -1 s -1. Another point to notice from the spectra is that carriers below approximately 1000 cm 2 V -1 s -1 are represented by only a single point rather than a distribution. This is due to the particular implementation of QMSA used. Since information about low mobility carriers is only distinguishable at high magnetic fields, data up to 12 T can only reliably distinguish carriers down to about 1000 cm 2 V -1 s -1. To include carriers below this point requires some form of extrapolation of the experimental data. With the particular implementation of QMSA used in this study, all carriers below the point where the available data can provide reliable information 58

71 Chapter 3 Characterisation of the Carrier Transport Properties 3.5x10-3 σ xx Sheet Conductivity (Ω -1 ) 2.5x x x10-4 σ xy -5.0x Magnetic Field (T) Fig. 3.7 Magnetic field dependent components of the conductivity tensor for a p-type Au-doped LWIR HgCdTe sample (LW-Au3) at 80 K. 1.5x10-3 Sheet Conductivity (Ω -1 ) 1.2x x x x10-4 p n Mobility (cm 2 V -1 s -1 ) Fig. 3.8 The mobility spectrum produced by QMSA from the data of Fig are lumped into one conductivity-mobility point. There is also a noticeable hole contribution appearing under the identified electron carrier species (at 10 4 cm 2 V -1 s -1 ), an electron component under the hole components at 1000 cm 2 V -1 s -1, and an extremely low mobility electron component at 200 cm 2 V -1 s -1. These are interpreted as artefacts from the QMSA procedure, introduced by errors in the experimental data. The occurrence of smaller peaks directly under main peaks in the mobility spectrum are quite common from QMSA due to non-ideal data, and 59

72 Chapter 3 Characterisation of the Carrier Transport Properties are often referred to as ghost peaks [48]. In this case the ghost peaks are easily identified as errors since, for HgCdTe, a hole mobility of cm 2 V -1 s -1 is too high to be realistic and an electron mobility of 200 cm 2 V -1 s -1 is too low to be considered real. Since the sample is Au-doped the observed p-type carrier species is expected. The existence of the conducting electrons could be due to the formation of an n-type surface inversion layer due to exposure of the surface to the atmosphere. This is a commonly observed phenomenon and has been reported previously [12, 14, 26]. Further evidence for this is seen in the temperature dependence of the identified carrier species, which is discussed next. Temperature dependent resistivity and Hall effect measurements were performed on the as-grown LW-Au3 sample, with temperatures ranging from 25 K to 300 K. This involved obtaining a set of magnetic field dependent measurements at each temperature point, and then applying QMSA to obtain the mobility spectrum. From the mobility spectra the low mobility hole carrier species and the higher mobility electron carrier species were identified, and values for mobility and carrier density extracted. The extracted carrier densities are plotted as a function of temperature in Fig For the experimental hole density data, two main regions can be identified and are fitted by the two red line segments in Fig For temperatures below approximately 67 K (1000/T = 15 K -1 ) carrier density is fitted to Eqn [51], the expression for carrier concentration in a semiconductor in thermal equilibrium, where n is the density of generated carriers, n 0 is a temperature independent parameter, E A is the activation energy and T is the temperature. The activation energy of holes for the LW-Au3 sample, obtained from the fit in Fig. 3.9, was 5 mev: n EA 0 exp 2 kt 3/2 = n T (3.20) For temperatures above 67K the density of holes is nearly constant and is fitted by the red horizontal line in Fig A constant hole density is consistent with the situation where, for temperatures above 67 K, the dopants are fully ionized and the hole density remains constant with further increases in temperature (for temperatures below the level where intrinsically 60

73 Chapter 3 Characterisation of the Carrier Transport Properties Sheet Carrier Density (cm -2 ) NA =1.18x1016 cm E g =0.17 ev n - Experimental n - Theoretical p - Experimental p - Theoretical E A =5meV E A =5meV /T (K -1 ) Fig. 3.9 The temperature dependence of conduction electrons and holes for the asgrown LW-Au3 sample. The line segments indicate fits for activation energy and the bandgap energy. generated holes are significant). Assuming that the sample is uniformly doped throughout the 17µm epilayer, the hole carrier density when acceptor dopants are fully ionized is approximately cm -3 which is in good agreement with the value for doping density specified by the manufacturer of cm -3. Considering the density of the electron carrier species in Fig. 3.9, an activation energy can also be observed at low temperatures. Eqn was used to fit a line through these points using an activation energy of 5 mev. As will be noted later, these electrons have a comparatively low, temperature-independent mobility and are associated with a degenerate surface inversion layer. In the high temperature regime there is a rapid increase in electron density with increasing temperature, which is interpreted as arising from the thermal generation of intrinsic carriers in the bulk region of the epilayer. Using Eqn and an E A value of 0.17 ev, a curve is fitted to the high temperature data points. This activation energy value corresponds to the expected bandgap energy for the material in that temperature range. The temperature dependence of the hole and electron mobilities obtained from QMSA are plotted in Figs and 3.11, respectively. A definite temperature dependence for hole mobility can be observed for temperatures up to 200 K. The data points at 250 K and 300 K are 61

74 Chapter 3 Characterisation of the Carrier Transport Properties µ T Mobility (cm 2 V -1 s -1 ) Temperatrure (K) Fig Hole mobility as a function of temperature for the as-grown LW-Au3 sample. (Note the logarithmic scales for both temperature and mobility) considered outliers due to large errors in the measurement when the sample becomes intrinsic at these high temperatures. Since electron mobility is two orders of magnitude greater than hole mobility for HgCdTe, conduction at 250 K and 300 K for x=0.23 material will be strongly dominated by electrons which can act to mask the effect of the relatively small contribution from holes. This results in large errors for hole data extracted at temperatures above 200K. The mobility versus temperature plot for electrons in the as-grown LW-Au3 sample of Fig has two line segments fitted to the data to indicate the two distinct carrier species with their distinctive temperature dependences in the high- and low-temperature regimes. In the lowtemperature regime the low mobility electrons have a mobility that is independent of temperature, being approximately cm 2 V -1 s -1. On the other hand, for the range 165 K to 300 K the intrinsically generated bulk electrons have a mobility that is strongly dependent on temperature, with mobility decreasing with increasing temperature. Comparing with the corresponding data points in Fig. 3.9, it is clearly evident that these high mobility electrons are intrinsically generated and dominate conduction in the high temperature regime. Based on the above discussion, it can be concluded that two distinct electron carrier species are observed, originating from different regions of the sample. At low temperatures, at which the intrinsically 62

75 Chapter 3 Characterisation of the Carrier Transport Properties x Intrinsic electrons µ T -3/2 Mobility (cm 2 V -1 s -1 ) Inversion Layer Electrons Experimental data Fit to low temperature data Fit to high temperature data Temperature (K) Fig Temperature dependence of electron mobility for the as-grown LWIR Au3 sample. generated electron concentration is negligible, the electron spectrum is dominated by relatively low mobility, temperature independent electrons, which is consistent with a surface inversion layer which may be degenerate and where Coulomb scattering is important. In the higher temperature range the electron spectrum is dominated by intrinsically generated carriers in the bulk p-type region. These electrons are characterised by a higher mobility which is consistent with what would be expected for the high crystalline quality bulk region. At high temperatures, the mobility of these intrinsic electrons is limited by lattice scattering mechanisms which are strongly temperature dependent and approximated by a T -3/2 dependence. Following the characterisation of the as-grown LW-Au3 sample, the sample was RIE plasma processed and prepared as described previously. Again, temperature dependent measurements were conducted and analysed using the QMSA procedure. The results of the QMSA analysis procedure clearly indicate that RIE plasma processing results in p-to-n typeconversion in HgCdTe. This is illustrated in the mobility spectrum of Fig which shows that the total conduction is dominated by two electron species with a small contribution due to the low mobility bulk holes from the underlying p-type material. The interpretation of the mobility spectrum is illustrated in Fig where the low mobility peak in the hole spectrum is attributed to the underlying original p-type material which 63

76 Chapter 3 Characterisation of the Carrier Transport Properties p-type bulk n-type surface n-type bulk Sheet Conductivity (Ω -1 ) 1.0x x x x x10-4 LW-Au RIE0 80K n p Mobility (cm 2 V -1 s -1 ) Fig Mobility spectrum of the type converted LW-Au3 with the identified carrier species indicated. As can be seen, the conductivity is dominated by electrons but the effect of the hole carrier is still discernable. n-type surface n-type bulk p-type bulk CdZnTe Substrate Fig A graphical illustration of the plasma processed HgCdTe sample, where the process partially type converts the bulk region from p-type to n-type. The surface is also converted to n-type but is characterised by low mobility carriers. remained unconverted. Above the p-type region lies the p-to-n type-converted region. The material between the p-type region and the damaged surface layer is designated as the n-type bulk of the type-converted material within which the electrons have a high mobility, corresponding to the electrons labelled bulk in Figs and The low mobility electrons, labelled as surface electrons, are attributed to the damaged and/or high concentration surface layer created by the RIE process. The low mobility and high concentration associated 64

77 Chapter 3 Characterisation of the Carrier Transport Properties 1.0x x K LW-Au3 Sheet Conductivity (Ω -1 ) 6.0x x x Mobility (cm 2 V -1 s -1 ) Fig The electron mobility spectrum for the type converted LW-Au3 sample after etching back the surface layer. Note that the low mobility electrons in the range to cm 2 V -1 s -1 which were present before the surface was etched back (see Fig.3.13) have almost been removed by the 0.6 µm etch-back. with these carriers is consistent with a degenerate n-type surface. The large range of mobility from cm 2 V -1 s -1 to cm 2 V -1 s -1 for surface electrons is perhaps indicative of a grading in the crystalline quality of the material from the surface to the bulk n-type region. The unambiguous indication that the surface and bulk electrons lie in their respective layers is clearly evidenced by their contrasting temperature dependence, and also from etch-back results. For example, Fig shows that after the first etch-back step (1 minute wet etch) had removed 0.6µm of HgCdTe, the lower mobility electrons were almost non-existent, whereas there were almost the same number of bulk high mobility electrons present. The electron mobility spectra obtained at each temperature point are plotted together and rendered in Fig. 3.15, which is a useful way of showing the evolution of carrier mobility and density with temperature. Fig clearly shows the large difference between the temperature dependence of the surface and bulk electron carrier species. The properties of 2-D surface electrons are generally independent of temperature, whereas bulk electrons show a strong dependence on temperature, both in terms of the mobility and sheet concentration. The mobility of the bulk electrons can be seen to be limited by a temperature dependent scattering 65

78 Chapter 3 Characterisation of the Carrier Transport Properties Fig The electron mobility spectra of the type converted LW-Au3 sample as a function of temperature. mechanism which becomes dominant above 67 K (1000/T = 15 K -1 ). At high temperatures the intrinsically generated electrons in the bulk region can be observed as the sharp increase in the conductivity peak in the spectrum. The representative mobility and sheet concentration values for surface and bulk electrons were calculated as described in Section 3.4 at each temperature, and the results are plotted in Fig. 3.16, which shows that the bulk electrons have a peak mobility approaching cm 2 V -1 s -1 for temperatures up to 50 K, whereas the surface electrons have a relatively constant and moderate mobility of approximately cm 2 V -1 s -1 throughout the temperature range of K. For the temperature range K the mobility of bulk electrons is strongly temperature dependent with a classical dependence for lattice scattering that is proportional to 3 T 2 [51]. Below 67 K the bulk electron mobility remains fairly constant with a slight decrease for the lowest temperatures, indicating that lattice scattering is no longer the dominant scattering mechanism at these lower temperatures. The combined effect of the lattice scattering, which decreases with decreasing temperature, and ionised impurity scattering, which 66

79 Chapter 3 Characterisation of the Carrier Transport Properties 10 5 T -3/2 Mobility (cm 2 V -1 s -1 ) 10 4 Surface Electrons Bulk Electrons T (K) Fig Mobility as a function of temperature for the surface and bulk electrons calculated from the mobility spectra obtained for the type converted LW-Au3 sample Sheet Concentration (cm -2 ) E A =170meV Extrinsic Electrons E A ~ 0eV Surface Electrons Bulk Electrons /T (K -1 ) Fig Carrier concentration as a function of temperature for the surface and bulk electrons calculated from the mobility spectra. The indicated bandgap energy ( 170 mev) is extracted from the activation of thermally generated intrinsic bulk electrons. In the low temperature range, the near constant sheet concentration is due to fully ionised donors in the type converted layer. 67

80 Chapter 3 Characterisation of the Carrier Transport Properties increases with decreasing temperature, could explain the peaking of the mobility curve at approximately 35 K in Fig From the concentration versus inverse temperature plot of Fig. 3.17, it is evident that the surface electron sheet concentration remains within the range of cm -2. For the bulk electrons two distinct activation energies can be identified. The higher value (E A = 0.17 ev) represents the intrinsic electron bandgap energy for x=0.23 at T=200 K, while the smaller activation energy (very close to 0 ev) is either associated with a very small extrinsic donor level which cannot be accurately resolved from the experimental data, or the approximately constant concentration level of cm -2 is associated with the donor dopants being fully ionised. As will be noted later, the junction depth is approximately 4 µm; thus, the average concentration in the n-converted layer is approximately cm -3. Differential Hall measurements were conducted to firstly confirm that the identified surface and bulk electron species did in fact originate from their respective regions, and also to obtain the depth profile of the p-to-n type-converted region. From the differential Hall results for the type-converted LW-Au1 sample, the electron mobility spectra at 80K obtained from QMSA are plotted as a function of etch depth and rendered in Fig. 3.18, where (a) and (b) are different perspectives of the same plot. These results illustrate that the lower mobility electron species does exist only in the surface layer. It can also be seen that the sheet conductivity decreases with increasing etch depth as expected. However, past 5µm the rate of decrease in sheet conductivity is not consistent with the rate of removal of the material, and in some cases there is an increase in sheet conductivity from successive etch-back steps. An increase in the conductivity from successive etch-back is physically impossible unless the properties of the sample have changed or there is an increase in experimental error. The inconsistent results are attributed to the formation of surface conducting layers, degrading contacts, induced changes to the material properties from the multiple etch-back processes, and/or due to removal and reapplication of indium contacts to the sample. This is another example of the delicate and problematic nature of HgCdTe. Such inconsistent results were not observed in the LW-Au3 sample since much greater care was taken in processing the sample. 68

81 Chapter 3 Characterisation of the Carrier Transport Properties (a) (b) Fig Electron mobility spectra at 80 K of the type converted LW-Au1 sample as a function of etch depth. (a) and (b) are different perspectives of the same data. 69

82 Chapter 3 Characterisation of the Carrier Transport Properties To obtain accurate resistivity and Hall effect measurements it is absolutely essential to have good ohmic contacts to the sample. This can be easily achieved with the first application of the pressed indium onto the contact area which is a bare HgCdTe surface. Subsequent mechanical removal of the indium and chemical etch-back leaves the surface visibly dirty since all traces of the indium cannot be removed. As a result, the reapplied pressed indium contacts tend to become non-ohmic, with the effect being observed as an asymmetry in the Hall effect and resistivity measurements with reversed current directions and reversed magnetic fields. The degrading contact effects can be partially remedied by thermally evaporating indium or gold onto the contact area, or by baking the sample, with indium contacts applied, at 80 C. Both techniques were employed on LW-Au1. It is believed that errors introduced by degrading contacts and processing-induced changes to the material from steps taken to improve the condition of the degraded contact area, are the reasons for the anomalous results observed at larger etch depths in Fig For LW-Au2 and LW-Au3, gold was evaporated onto the contact area before the application of the pressed indium contacts. Care was taken not to remove all the gold in the etch-back process, which proved to be successful in maintaining good ohmic contacts. What is also apparent from Fig. 3.18(b) is that there is a shift of the mobility spectrum towards lower mobility as the etch depth approaches the HgCdTe/CdZnTe interface. This is consistent with the effect of changing composition of the material an increase in the x value as we approach the substrate interface, which has previously been reported in [11]. An increase in x value generally corresponds to lower mobility, as observed in this case. Using differential Hall measurements for the LW-Au3 sample listed in Table 3.1, the bulk electron carrier density at 80K was extracted and plotted in Fig as a function of epilayer depth. It also indicates the bulk hole concentration, assuming the holes are uniformly distributed throughout the remainder of the p-type epilayer. The experimental data points of bulk electron concentration versus depth have been fitted to both the complementary error function (erfc) and a Gaussian distribution. If it is assumed that the concentration of n-type 70

83 Chapter 3 Characterisation of the Carrier Transport Properties Concentration (cm -3 ) Electrons Holes erfc fit Gaussian fit Depth (µm) Fig Concentration depth profile for bulk electrons and bulk holes for the LW- Au3 HgCdTe sample at 80 K. extrinsic dopants is equal to the electron concentration at 80K, then the concentration profile shown in Fig indicates that the n-type dopants are introduced into the HgCdTe epilayer via a diffusion process. A fit to the erfc distribution indicates diffusion from a constant concentration or gaseous deposition source at the surface of the sample. In this case, the concentration profile is given by Eqn. 3.21, where l is the distance into the sample measured from the surface, t is the time the sample is exposed to the plasma, C s the dopant concentration at the surface, and D is the diffusivity of the n-type dopant: l Clt (,) = Cerfc s 2 Dt (3.21) From the fit shown in Fig. 3.19, values of D = 1.41x10-10 cm 2 s -1 and C s =5.50x10 15 cm -3 can be extracted. A fit of the experimental data to a Gaussian distribution would indicate that the diffusion process results from a source having a constant number of diffusing dopants. Eqn gives the resulting Gaussian concentration distribution with the same parameters as defined for Eqn. 3.21: 71

84 Chapter 3 Characterisation of the Carrier Transport Properties 2 l Clt (,) = Cs exp 2 Dt (3.22) From the fit to the data, the parameters for the Gaussian distribution are D = 1.55x10-10 cm 2 s -1 and C s = 4.69x10 15 cm -3. Given the available data points and accounting for experimental error, it is not possible to determine whether the erfc or Gaussian distribution is a better fit to the experimental data. The experimental results presented in Fig raise some important issues related to the RIE plasma induced p-to-n type-conversion process. Firstly, the shape of the electron concentration profile would indicate that the type-conversion process is associated with the diffusion from the surface of some extrinsic n-type dopant species. Secondly, the electron concentration in the near-surface region is in the low-mid cm -3 range. This is much greater than any residual background donor concentration, which has generally been found experimentally to be in the low cm -3 range for such materials. This also suggests the presence of an extrinsic n-type dopant species rather than simply a p-type dopant neutralisation process. The third point is based on the fact that the electron concentration is always lower than the hole concentration in the substrate (~10 16 cm -3 ), which indicates that the p-to-n type converted region is not only a result of extrinsic n-type doping, compensating the background p-type doping but, in fact, also involves some form of neutralisation of the p-type dopants. 3.7 Results for LWIR Vacancy Doped HgCdTe Characterisation of the type-converted LW-Vac sample, along with the other samples of Table 3.1 followed the same procedure as for the LW-Au type-converted samples described previously. However, a depth profile of carrier properties could not be obtained for samples other than the LW-Au sample since after the first etch-back step, the entire type converted region was removed in the 1 minute etch-back process. From previous studies on Br 2 -methanol etching of non-type-converted HgCdTe, the etch rate was found to vary from 0.4 to 0.6 µm/minute for the etching conditions used in this experiment. Therefore, it can be conservatively concluded that the type conversion extends less than 1 µm in the LW-Vac, 72

85 Chapter 3 Characterisation of the Carrier Transport Properties Fig The mobility spectra of the type converted LW-Vac sample as a function of temperature. MW-Au and MW-Vac samples. The rendered mobility spectra as a function of temperature shown in Fig has the main features of the corresponding plot of Fig for the LW-Au sample, indicating the distinct temperature dependence of the bulk and surface electrons. The extracted carrier density versus inverse temperature of Fig indicates that for the LW-Vac sample, the bandgap energy corresponding to intrinsic electron activation is once again approximately 0.17 ev. The electron carrier density at lower temperatures (1000/T > 10 K -1 ) remains almost constant, indicating that the dopants are fully ionized in this region, or that the activation energy is very close to zero. It is noted that the bulk electron mobility in this vacancy-doped sample ( cm 2 V -1 s -1 at 40 K) is significantly lower than for the gold-doped sample ( cm 2 V -1 s -1 at 40K; see Fig. 3.17). The temperature dependence of the electron mobility approaches the classical 3 T 2 dependence at high temperatures as shown in Fig As found previously, the mobility and sheet concentration of surface layer electrons are found to be independent of temperature in the range K with values of cm 2 V -1 s -1 and cm -2, respectively. 73

86 Chapter 3 Characterisation of the Carrier Transport Properties Sheet Concentration (cm -2 ) E g =170meV E A ~ 0eV Surface Electrons Bulk Electrons /T (K -1 ) Fig Carrier concentration as a function of temperature for the surface and bulk electrons from the type converted LW-Vac sample, calculated from the mobility spectra. The constant concentration due to extrinsic electrons and bandgap energy (E g 170 mev) giving rise to thermally generated intrinsic electrons are indicated T -3/2 Mobility (cm 2 V -1 s -1 ) 10 4 Surface Electrons Bulk Electrons T (K) Fig Mobility as a function of temperature for the surface and bulk electrons calculated from the mobility spectra obtained for the type converted LW-Vac sample. 74

87 Chapter 3 Characterisation of the Carrier Transport Properties The hole mobility and density was determined for the sample from measurements taken after the first etch-back step when all of the type-converted region had been removed. Fig shows the hole mobility versus temperature with a T α relationship fitted to the data, where α = A T α relationship is a strong indication of a lattice scattering mechanism being the dominant mechanism, since lattice vibrations increase with increasing temperature. This leads to greater scattering probability and hence lower mobility with increasing temperature. Figure 3.24 gives the extracted sheet carrier density for the LW-Vac sample. 3.8 Results for MWIR Au Doped HgCdTe The mobility spectra results for the MW-Au sample indicates that MWIR HgCdTe shares the same main features as the LWIR material in that the RIE plasma process typeconverts the p-type material to n-type, and the type-converted bulk region consists of high mobility electrons with a damaged n-type surface characterised by low mobility electrons. The mobility spectra obtained in the temperature range K are plotted together and rendered in Fig Comparing Fig with the corresponding plots for the LWIR samples, a few notable differences can be observed. Firstly, the peak mobility of the bulk electrons is lower in the MW-Au sample. This is expected since the higher x value for MWIR material (x ~ 0.3) results in the electrons having a higher effective mass, leading to lower mobility. Also, the rapid increase in conductivity at high temperature due to intrinsic thermal generation of electron-hole pairs is not observed in the MW-Au sample. This can be explained by the higher bandgap energy of MWIR material approximately 0.3 ev for MWIR material compared to 0.17 ev for LWIR material at 200 K. The higher bandgap energy means significant amounts of intrinsic generation will not occur until a higher temperature is reached for the MWIR material, typically above 300 K. 75

88 Chapter 3 Characterisation of the Carrier Transport Properties µ T Mobility (cm 2 V -1 s -1 ) Temperature (K) Fig Mobility as a function of temperature for holes from the underlying p-type bulk region, calculated from the mobility spectra obtained for the type converted LW-Vac sample. Sheet Carrier Density (cm -2 ) /T (K -1 ) Fig Carrier concentration as a function of temperature for holes from the underlying p-type bulk region of the type converted LW-Vac sample, calculated from the mobility spectra. 76

89 Chapter 3 Characterisation of the Carrier Transport Properties Fig The mobility spectra of the type converted MW-Au sample as a function of temperature. The extracted electron sheet density and mobility are plotted in Fig and Fig. 3.27, respectively. From Fig. 3.26, an activation energy of 2.1 mev is observed for bulk electrons which can be attributed to the extrinsic donor level. For the given temperature range, the contribution from intrinsic carriers is not significant for MWIR material, hence the activation energy corresponding to the bandgap is not observed. Bulk electrons have a peak mobility of approximately cm 2 V -1 s -1 at K and show a 3 T 2 temperature dependence at high temperatures. Unlike the LWIR samples, the surface electron mobility in MW-Au shows a weak temperature dependence, being proportional to T -0.14, although the mobility remains in the range of cm 2 V -1 s -1. The surface electron density remains relatively constant at 6 8x10 12 cm -2 over the entire temperature range. 77

90 Chapter 3 Characterisation of the Carrier Transport Properties Sheet Concentration (cm -2 ) Surface Electrons Bulk Electrons E a =2.1meV /T (K -1 ) Fig Carrier concentration as a function of temperature for the surface and bulk electrons from the type converted MW-Au sample, calculated from the mobility spectra. The activation energy of 2.1 mev for the bulk electron is also included Surface Electrons Bulk Electron T -3/2 Mobility (cm 2 V -1 s -1 ) 10 4 T T (K) Fig Mobility as a function of temperature for the surface and bulk electrons calculated from the mobility spectra obtained for the type converted MW-Au sample. 78

91 Chapter 3 Characterisation of the Carrier Transport Properties µ T Mobility (cm 2 V -1 s -1 ) Temperatrure (K) Fig Mobility as a function of temperature for holes from the underlying p-type bulk region, calculated from the mobility spectra obtained for the type converted MW-Au sample Sheet Hole Density (cm -2 ) /T (K -1 ) Fig Carrier concentration as a function of temperature for holes from the underlying p-type bulk region of the type converted MW-Au sample, calculated from the mobility spectra. 79

92 Chapter 3 Characterisation of the Carrier Transport Properties Hole mobility and density data of the unconverted p-type bulk region was obtained by resistivity and Hall effect measurements after all of the type-converted n-layer had been etched away in a bromine-methanol wet etch. The extracted mobility and density values are plotted in Fig and Fig. 3.29, respectively. Also included in Fig is a fit of the temperature dependence for bulk hole mobility to the expression: data between 50 K 300 K. µ T α, with α = The fit includes 3.9 Results for MWIR Vacancy Doped HgCdTe The mobility spectra for sample MW-vac obtained in the temperature range K are plotted together and rendered in Fig The main features of the corresponding plot for the MW-Au sample (Fig. 3.25) are also observed for this MWIR vacancy doped sample. The peak mobility of the bulk electron carrier species is approximately cm 2 V -1 s -1 at low temperatures, which decreases with increasing temperatures. The temperature invariance of the surface electron carrier species can also be clearly observed, with the mobility being approximately cm 2 V -1 s -1 throughout the temperature range. From figure 3.31, the extrinsic donor level for the bulk electron activation in the MW-Vac sample is either too low to be accurately determined, or the dopants are fully ionised in the temperature range shown. As was the case for the MW-Au sample, the effect of intrinsic thermal carrier generation is not observed in the measured temperature range. The mobility of bulk electrons tends towards a 3 T 2 temperature dependence for high temperatures as shown in Fig The peak mobility of cm 2 V -1 s -1 for bulk electrons occurs at 40 K. The mobility of surface electrons has a weak temperature dependence of T for the whole temperature range of K with values of approximately cm 2 V -1 s -1. In addition, the surface electron concentration remains constant at approximately cm -2. Hole mobility and density data of the unconverted p-type bulk region were obtained by resistivity and Hall effect measurements after all of the type-converted n-layer had been etched away in a bromine-methanol wet etch. The extracted mobility and density values are plotted in 80

93 Chapter 3 Characterisation of the Carrier Transport Properties Fig The mobility spectra of the type converted MW-Vac sample as a function of temperature. Figs and 3.34, respectively. With consideration given to the temperature dependence of hole mobility for the other samples which all show a similar dependence, a the data for the MW-Vac sample in Fig T 0.60 is fitted to 81

94 Chapter 3 Characterisation of the Carrier Transport Properties Sheet Concentration (cm -2 ) Surface Electrons Bulk Electrons E a ~ 0eV /T (K -1 ) Fig Carrier concentration as a function of temperature for the surface and bulk electrons from the type converted MW-Vac sample, calculated from the mobility spectra. The activation energy of 0 mev for the bulk electron is also included Surface Electrons Bulk Electrons T -3/2 Mobility (cm 2 V -1 s -1 ) 10 4 T T (K) Fig Mobility as a function of temperature for the surface and bulk electrons calculated from the mobility spectra obtained for the type converted MW-Vac sample. 82

95 Chapter 3 Characterisation of the Carrier Transport Properties Mobility (cm 2 V -1 s -1 ) µ T Temperatrure (K) Fig Mobility as a function of temperature for holes from the underlying p-type bulk region, calculated from the mobility spectra obtained for the type converted MW-Vac sample Sheet Hole Density (cm -2 ) /T (K -1 ) Fig Carrier concentration as a function of temperature for holes from the underlying p-type bulk region of the type converted MW-Vac sample, calculated from the mobility spectra. 83

96 Chapter 3 Characterisation of the Carrier Transport Properties 3.10 Summary and Comparisons Between Type-converted Samples This chapter has examined and presented results on the transport properties of LPE grown p-type HgCdTe epitaxial layers both before and after p-to-n type-conversion by RIE plasma processing. Both LWIR and MWIR materials, as well as both gold-doped and vacancydoped samples, were examined. In all cases, the n-type converted layers have been found to consist of a thin surface region with a temperature independent electron sheet concentration of approximately cm -2 and a temperature independent mobility of approximately cm 2 V -1 s -1. Beneath the surface lies high quality n-type material characterised by high electron mobility that is typical of device-grade HgCdTe. The depth of this type-converted n-type region was found to be approximately 4 µm for the LW-Au samples but less than 0.5 µm for the LW-Vac, MW-Au and MW-Vac samples. The carrier transport properties at 80K are summarised in Table 3.2. In order to facilitate comparison between the different samples, the mobility versus temperature plots for bulk electrons in all samples is combined in Fig As expected, the mobility of bulk electrons for LWIR material is generally greater than for MWIR samples due to the smaller effective mass of electrons in LWIR material. The temperature dependence of mobility is determined by phonon scattering at elevated temperatures which results in decreasing mobility with increasing temperature, and impurity scattering at low temperatures which results in decreasing mobility with decreasing temperature. Theoretically, in the high temperature regime where phonon scattering is the dominant scattering mechanism, the mobility should have a 3 T 2 dependence where T is the temperature [52]. A line with a slope of 3 T 2 is included in Fig for comparison. It can be seen that all samples are approaching the T 3 2 relationship with increasing temperature, and that at high temperatures the two LWIR samples merge together, as do the two MWIR samples. This is to be expected since for a given x-value material at high temperatures phonon scattering should dominate and render the bulk electron mobility independent of doping type. Ignoring the offset between LWIR and MWIR material, it is interesting to note that the results in Fig clearly indicate that the shape of the curves for 84

97 Table 3.2: Carrier transport properties at 80K Sample Bulk Hole Mobility (cm 2 V -1 s -1 ) Chapter 3 Characterisation of the Carrier Transport Properties Bulk Electron Mobility ( 10 4 cm 2 V -1 s -1 ) Surface Electron Mobility ( 10 4 cm 2 V -1 s -1 ) Bulk Electron Sheet Concentration ( cm -2 ) Surface Electron Sheet Concentration ( cm -2 ) LW-Au LW-Vac MW-Au MW-Vac Bulk Electron Mobility (cm 2 V -1 s -1 ) LW-Au LW-Vac MW-Au MW-Vac T -3/ Temperature (K) Fig Temperature dependence of bulk electron mobility for the type converted HgCdTe samples. gold-doped material are similar to each other while the curves for vacancy-doped samples are also similar to each other. In particular, as temperature is reduced the mobility of vacancy-doped samples tends to reach a maximum value at a higher temperature than the gold-doped samples. In contrast, for gold-doped samples the mobility continues to increase for decreasing temperature, reaching a higher maximum value at temperatures of approximately K. This tends to suggest that certain impurity-based scattering mechanisms are more effective in vacancy doped material in comparison to the gold doped samples. Fig shows that the mobility of surface electrons from all samples studied share many characteristics. The mobility remains at approximately cm 2 V -1 s -1 throughout 85

98 Chapter 3 Characterisation of the Carrier Transport Properties the temperature range. Only a very slight decrease in mobility with increasing temperature can be discerned. Comparing the electron mobility data between the various samples, it was found that the mobility of bulk electrons is dependent on both material composition and dopant species, while the surface electron mobilities are largely independent of material composition, dopant species, and temperature. The dominant scattering mechanism for the bulk electrons are impurity-based at low temperatures and lattice-based at higher temperatures. Electrons at the surface are characterised by low mobility that is mainly independent of temperature, suggesting surface scattering and/or poor crystal quality, due to damage of the surface caused by the plasma process, is the limiting scattering mechanism. This behaviour is similar to that found for inversion layer electrons on p-type material [12]. Surface electron mobility for the as-grown LW-Au3 sample is approximately cm 2 V -1 s -1 while surface electrons for the sample after RIE plasma processing is lower at approximately cm 2 V -1 s -1, indicating additional surface damage caused by the RIE plasma processing. Fig compares the hole mobility between the different samples. The results indicate that they all share a similar temperature dependence which can be approximated by µ T The difference in the mobility between samples is quite small, but a comparison between dopant species clearly indicates that vacancy doped samples generally have higher hole mobilities than Au-doped samples; that is, the LW-Vac sample has higher mobility than the LW-Au sample and the MW-Vac sample has higher mobility than the MW-Au sample. 86

99 Chapter 3 Characterisation of the Carrier Transport Properties Mobility (cm 2 V -1 s -1 ) LW-Au LW-V MW-Au MW-V Temperature (K) Fig Temperature dependence of surface electron mobility for the type converted HgCdTe samples Mobility (cm 2 V -1 s -1 ) LW-Au LW-Vac MW-Au MW-Vac T Temperatrure (K) Fig Temperature dependence of bulk hole mobility for the type converted HgCdTe samples. 87

100 Chapter 3 Characterisation of the Carrier Transport Properties Hole Density (cm -3 ) E A = 5meV LW-Au LW-Vac MW-Au MW-Vac Eqn /T (K -1 ) Fig Hole concentration as a function of temperature for the type converted HgCdTe samples Surface Passivation Previously in this chapter, in Fig. 3.8, it was shown that the sheet conductivity of a Au-doped LWIR sample consisted of the expected p-type component and also a significant n-type component which was attributed to the inversion of the unpassivated surface. Figure 3.39 shows the n-type and p-type mobility spectrum for a Au-doped sample passivated with thermally deposited CdTe, and in comparison to Fig. 3.8 it is clearly evident that the n-type surface conduction is no longer significant and only a single p-type species is observed, as expected. The n-type spectrum shows an extremely low mobility carrier species, approximately 100 cm 2 V -1 s -1, that can be attributed to experimental error and disregarded because information at such lower mobility has a high level of error for measurements with magnetic fields limited to a maximum of 12 T. These results show that the CdTe surface passivation has been successful in quenching many of the effects of semiconductor surface, and the surface is no longer inverted. However, no additional information can be inferred about the condition of the semiconductor surface. 88

101 Chapter 3 Characterisation of the Carrier Transport Properties Sheet Conductivity (Ω -1 ) 1.0x x x x x µm CdTe passivated 80K n p Mobility (cm 2 V -1 s -1 ) Fig The mobility spectrum for electrons and holes at 80K obtained from a LWIR Au doped HgCdTe sample with the surface passivated with thermally deposited CdTe Chapter Summary and Conclusions This chapter has presented results of a study on transport properties of p-to-n type converted HgCdTe layers formed by reactive ion etching, as used in the junction formation process for fabrication of HgCdTe photodiodes. The study considered both LWIR and MWIR materials as well as both gold-doped and vacancy-doped samples. In all cases, the n-type layers formed by plasma-induced type conversion have been found to consist of a thin surface region with a temperature independent electron sheet concentration in the range of cm -2 and a temperature independent mobility in the range of cm 2 V -1 s -1. This is a rather surprising result given that HgCdTe bulk transport properties are a strong function of x-value and dopant type. These results tend to suggest that the thin surface layer is degenerately doped and of moderate carrier mobility due to RIE induced surface damage. Underlying the above-described surface region is a moderately doped n-type layer which displays the classical carrier transport properties of high quality bulk HgCdTe. An important point to note is that for both LWIR and MWIR material the gold-doped samples consistently gave higher values of mobility in comparison to vacancy-doped materials. The 89

102 Chapter 3 Characterisation of the Carrier Transport Properties temperature dependence of the bulk electron mobility was consistent with phonon dominated scattering at high temperatures. The results indicate that p-to-n type converted, vacancy doped material displays a higher level of impurity scattering when compared to p-to-n type converted Au-doped samples. These results provide further evidence that RIE type conversion in HgCdTe is a viable process for the formation of n-on-p photovoltaic detectors in large format focal plane arrays for infrared sensing. The electron concentration profile determined via differential Hall measurements strongly suggests that the p-to-n type conversion process occurs as a result of p- type dopant neutralisation and diffusion of n-type dopants from the HgCdTe surface. The transport properties of p-type HgCdTe, including the temperature dependence, have also been characterised. This has previously been a difficult task to achieve with traditional characterisation techniques due to the presence of the n-type inversion layer which invariably forms on the surface of the p-type material. These multiple layers can now be differentiated using QMSA which can separate the effects of the two different carriers. Using QMSA, it was also possible to obtain the hole mobility and concentration for LWIR samples at high temperature. This task would not have been achievable previously due to the presence of thermally generated intrinsic n-type carriers which dominate the conduction process and mask the p-type behaviour. The study of the transport properties of the type-converted HgCdTe sample made extensive use of QMSA and a secondary conclusion can be made regarding the suitability of the QMSA technique for this task. Variable magnetic field Hall and resistivity measurements and analysis of the results using QMSA is a valuable technique for analysing the carrier transport properties of multicarrier systems. From accurate measurements, it can determine the number and type of carriers present, their mobility and their relative contribution to the total conductivity of the sample. These properties make this technique particularly suited to characterising the transport properties of p-to-n type converted HgCdTe layers formed by the reactive ion etching, as used in the junction formation process. 90

103 4 LWIR Device Characterisation and Chapter 4 Performance Evaluation LWIR Device Characterisation and Performance Evaluation In order to advance the development of the LWIR photodiode fabrication process, it is necessary that the key performance indicators and properties of the fabricated devices be characterised and analysed. Characterisation of the fabricated photodiodes involved a number of different measurements including current-voltage (I-V) characteristics, spectral responsivity and noise-associated dark currents. The collected data will not only give an indication of the relative merits of a particular fabrication process, but it will also provide invaluable information that will enable identification of the short-comings of the particular process; information that will assist in the further development and refinement of the process. This chapter presents the experimental setup and techniques used in the characterisation of the fabricated devices, along with the experimental data. The results obtained from the various device lots will enable a comparison to be made between different processes, and will allow an evaluation of the relative success or otherwise of each fabricated device lot. In this chapter the zero-bias dynamic resistance-area product (R 0 A) figure, which is extracted from I-V measurements, is used as the key indicator for evaluating the performance of fabricated photodiodes. More detailed analysis of the experimental data is presented in the chapters that follow. 4.1 Current-Voltage Characteristic Measurements Current-voltage measurements are perhaps the most utilised characterisation procedure for photodiodes because much of the optical performance characteristics of the device in its intended application can be evaluated by studying the electrical characteristics. The currentvoltage (I-V) characteristic of the photodiode is obtained by measuring the DC diode current as a function of the applied bias voltage, and for this work such measurements were performed 91

104 Chapter 4 LWIR Device Characterisation and Performance Evaluation LN 2 /LHe N 2 /He Exhaust Cold Finger Temperature Controller To Vacuum Pump HP4156A Semiconductor Parameter Analyzer Sample Mount Cold Shield Cold Shield Cover Transparent IR Window Fig. 4.1 Experimental setup used to obtain temperature dependent I-V characteristics for the fabricated photodiodes. The cold shield covers are installed for dark measurements and removed for illuminated measurements. using a HP4156A semiconductor parameter analyser. Packaged devices were installed into a temperature controlled cryostat system as shown in Fig To perform dark current measurements the cold shield cover was closed so that the temperature of the shield and the cover is approximately the same as that of the device. With the cover open, measurements of the illuminated photodiode can also be conducted under temperature controlled conditions. Using liquid nitrogen as the coolant, the sample temperature is able to be controlled from room temperature down to 80 K. For lower temperatures, down to 20 K, liquid helium was used as the coolant. The temperature range for I-V measurements was 25 K to 200 K, since above this range the thermal generation of intrinsic carriers across the bandgap dominates for LWIR HgCdTe. 92

105 Chapter 4 LWIR Device Characterisation and Performance Evaluation Dynamic Resistance (Ω) Diode Current (µa) Diode Bias (V) -50 Fig. 4.2 An example of an experimentally obtained I-V characteristic and the corresponding R-V characteristic for a fabricated LWIR photodiode. An example of an I-V measurement is shown in Fig. 4.2, along with the corresponding dynamic resistance-voltage (R-V) characteristic. The R-V characteristic is derived from the I-V characteristic, and is calculated by: R d di = dv 1 (4.1) That is, the dynamic resistance is the inverse of the derivative of the I-V characteristic. Note that the R-V characteristic is plotted on a logarithmic scale to encompass the large dynamic range of this parameter. The R-V plot is very useful for graphical analysis of the data since it is more sensitive to changes in the various dark current components. From Fig. 4.2 it can be seen that in the high forward bias range the dynamic resistance is not an ideal characteristic corresponding to the dominant diffusion current, but instead saturates to an almost constant value. This region corresponds to a constant slope of the I-V characteristic and is due to the series resistance of the device combined with the electrical connections to the device. That is, series resistance effects dominate the characteristic at high forward bias. Ideally, if it is assumed that diffusion or g-r dark current dominates in the high bias regime, then an exponential increase in the current is expected. Usually, the dark current generation mechanisms of the photodiode are studied by determining the R-V characteristic. In 93

106 Chapter 4 LWIR Device Characterisation and Performance Evaluation + I r S + V T V d - - Fig. 4.3 Circuit model of the photodiode under test. The diode symbol represents the ideal p-n junction and r s is the parasitic resistance associated with the actual device and electrical connections. these situations it is advantageous to remove the effect of the parasitic series resistance, which can act to mask the photodiode R-V characteristic that results from the dark current mechanisms. The equivalent circuit is represented in Fig. 4.3; thus, to obtain the true I-V characteristic of the photodiode without the series resistance, circuit analysis can be used to give: Vd VT Ir S = (4.2) In this case, V d and I give the ideal I-V characteristics, and the series resistance, r S, can be determined following the procedure presented in Ref. [53]. If it is assumed that diffusion or g-r current dominates in the forward bias regime, then I qv ( + Ir) I exp 1 (4.3) ηkt d S = 0 where η is an ideality factor indicating the relative contributions of g-r and diffusion current to the total current. Hence a plot of I(dV T /di) versus I should give a linear plot with a gradient equal to r S. Once the value of r S has been obtained by data fitting, then Eqn. 4.2 can be used to obtain the actual photodiode I-V characteristic that is corrected for the effect of series resistance. Figure 4.4 shows an example of an R-V characteristic before and after being corrected for the effect of series resistance. It is evident that the difference can be significant when the series resistance is of the order of the dynamic resistance, and although a -0.4 V to 0.15 V 94

107 Chapter 4 LWIR Device Characterisation and Performance Evaluation 10 4 Data corrected for r s Raw Data Dynamic Resistance (Ω) Diode bias (V) Fig. 4.4 A comparison between the R-V characteristic obtained from raw experimental data and after the data has been corrected for the effect of r s. The value of r s in this case was 256 Ω. external bias range was applied in the measurement, the effective junction bias voltage is significantly less. 4.2 Spectral Responsivity Measurements Responsivity measurements were obtained using the setup illustrated in Fig Phase coherent detection using an optical chopper and lock-in amplifier is employed to suppress background noise. To package the devices so that they are suitable for mounting in the dewar, the devices needed to be frontside illuminated. Therefore, to obtain the responsivity the device structure needed to be modified slightly. Whereas regular photodiodes are backside illuminated and have the n-metal contact fully overlapping the underlying junction, all devices for responsivity characterisation are frontside illuminated and have half of the junction area covered by the n-metal contact, as shown in Fig. 4.6, in order to allow the IR transmission into the other half. 95

108 Chapter 4 LWIR Device Characterisation and Performance Evaluation Optical Chopper Spectrometer IR Glowbar Computer Control and Data Acquisition D.U.T. Temperature Controlled Cryostat Lock-in Amplifier Transimpedance Amplifier Fig. 4.5 Experimental setup for spectral responsivity measurements. An example of a spectral responsivity measurement is shown in Fig Spectral responsivity measurements undertaken as part of this thesis were primarily used to confirm the cut-off wavelength of fabricated devices and, hence, the x-value of the Hg 1-x C x dte material. While responsivity is a critical detector specification for selection of devices for a system, it is essentially fixed by fundamental material parameters (bandgap, refractive index, etc) and by device type (photodiode or photoconductor). As such, it is not a good measure of device performance. The cutoff wavelength of the detector is the upper wavelength value where the responsivity decreases to half of the maximum responsivity. Aside from the cutoff wavelength figure, in order to extract any other useful information from spectral responsivity measurements would require the optical collection area to be determined to a high degree of accuracy. 96

109 Chapter 4 LWIR Device Characterisation and Performance Evaluation µm Fig. 4.6 Photograph of frontside illuminated photodiodes fabricated for optical characterisation. 140 Responsivity (x10-6 AW -1 cm 2 ) λco TN Wavelength (nm) Fig. 4.7 An example of a spectral responsivity measurement taken on a device from device lot TN7. It indicates a cutoff wavelength of approximately 9.5 µm. 97

110 Chapter 4 LWIR Device Characterisation and Performance Evaluation 4.3 Noise Measurements The electrical noise characteristics of the fabricated photodiodes were obtained using the measurement setup shown in Fig The current noise from the photodiode is amplified and converted to a voltage signal by the Stanford Research Systems SR570 transimpedance amplifier. This amplifier is capable of a gain of 10 6 VA -1 with a AHz -1/2 noise floor over a 1 khz bandwidth. The voltage signal from the amplifier was then analysed with a HP 35665A Dynamic Signal Analyzer. During measurement, the devices were mounted in the dark (cold shield in place) within a temperature controlled cryostat to allow temperature dependent measurements. Note that the transimpedance amplifier enables measurements to be taken while the photodiode is biased. An example of a measured noise spectrum is shown in Fig. 4.9(a). Background noise is clearly evident in this figure, and consists mainly of a 50 Hz component from the mains supply and its associated harmonics. By removing these data points, as shown in Fig. 4.9(b), the noise response of the photodiode can more clearly be distinguished. Note that this noise spectrum exhibits a large 1/f noise component due to the fact that it is reverse biased at -50 mv. 4.4 Vacuum Baking LWIR photodiodes require to be cooled to cryogenic temperatures in order to achieve optimum performance, and devices are usually operated at or below liquid nitrogen temperatures. To make this possible, the fabricated devices need to be packaged in vacuum dewars. Prior to sealing of the dewars, in order to ensure that the vacuum in the dewars is maintained, the dewer and the device assembly are baked at an elevated temperature under vacuum for an extended period of time to allow contaminants to outgas. For these devices, typical bake-out times range from a few days to a week at temperatures between 80 and 100 C, well above any temperatures encountered during operation or long-term storage. This vacuum bake-out process is essential to maintain vacuum integrity of the package, although it may also alter device characteristics. For example, the stability of the junction and/or the formation of 98

111 Chapter 4 LWIR Device Characterisation and Performance Evaluation Dynamic Signal Analyser HP35665A Transimpedance Amplifier with Bias Control SR570 Temperature Controlled Cryostat D.U.T. Fig. 4.8 Experimental setup used to obtain photodiode noise measurements Current Noise (AHz -1/2 ) TN8 T=80K V bias =-50mV Current Noise (AHz -1/2 ) TN8 T=80K V bias =-50mV Frequency (Hz) Frequency (Hz) Fig. 4.9 An example of a low frequency noise spectrum obtained for a photodiode from device lot TN8 under reverse bias. (a) is the spectrum as obtained from the dynamic signal analyser and it clearly shows a strong 50Hz component and the associated harmonic components from the mains supply. (b) shows the spectrum with the 50 Hz, and the associated harmonic components, removed from the data. defects may be exacerbated due to the inherently unstable nature of HgCdTe material. This bake-out process may be problematical for device performance, even for relatively low bakeout temperatures, since LWIR HgCdTe material is particularly sensitive to heat induced changes as a result of its very narrow bandgap. Therefore, the effect of the vacuum baking on device performance was characterised for this work, using a baking temperature of 80 C. 99

112 Chapter 4 LWIR Device Characterisation and Performance Evaluation 4.5 Zero Bias Dynamic Resistance-Area Product An often quoted figure of merit for infrared photodiodes is the specific detectivity, D*, which is a measure of the signal-to-noise ratio, or sensitivity, of the device. When applied to photodetectors, sensitivity refers to the effectiveness of the detector in converting incident photons to electron-hole pairs compared to how much noise it generates in the process. D* is defined in Eqn. 4.4, where A is the area of the detector, f is the noise bandwidth, and NEP is the noise equivalent power [4]. ( ) 1 2 A f D* = (4.4) NEP The NEP is the incident radiation power required to produce a signal equal to the noise: that is, to produce a signal-to-noise ratio of one. Using NEP to measure sensitivity means that the higher the sensitivity, the lower the value of the NEP figure. Generally it is preferable to have a figure for sensitivity that increases with increasing signal to noise ratio: hence, the detectivity (D), which is the inverse of the NEP, is used [3]. Since the NEP also depends on the detector size and sampling rate, D*, which is the inverse of the NEP normalised to the detector area (A) and bandwidth ( f), is used in place of D. D* as a figure of merit, like almost any figure of merit, must be considered together with the measurement technique used to obtain it. It is often useless to compare detector performance using D* figures without knowledge of the measurement details or the detector type. Since the spectral response of the detector is not constant, the spectrum of the incident radiation needs to be considered. Measurements of D* may use a specific bandpass of light, monochromatic light, or the spectrum from a black body at a specific temperature. The noise considerations can also be problematical in D* calculations. For example, one needs to know whether readout noise of the electronics is included, and whether or not 1/f noise considerations are important. Furthermore, the field of view of the detector is also an important consideration. 100

113 Chapter 4 LWIR Device Characterisation and Performance Evaluation If we consider the noise generated by diffusion and drift dark currents of a photodiode, then D* can be calculated by Eqn. 4.5, where η is the quantum efficiency and λ is the wavelength of the radiation [4]. D* ηλ R A hc 4kT 0 = 1 2 (4.5) From a device and technology development viewpoint, R 0 A in the dark is the most useful and unambiguous figure of merit for evaluating the success or otherwise of the particular fabrication process employed. The quantum efficiency is not greatly affected by the specific fabrication process, but is more a function of any anti-reflection coatings and other device design factors such as geometry and structure. On the other hand, R 0 A in the dark is determined by the dark current generation mechanisms which are strongly dependent on specific process conditions, and can be routinely extracted from dark I-V measurements. For the above reasons, R 0 A is the primary figure of merit used to compare the performance of the various device lots fabricated as part of this thesis. A D* value can also be defined for particular applications where the noise of the background can be specified. A value of specific detectivity can be calculated for a given random background flux and is called D* BLIP and is given by Eqn. 4.6 for a photodiode [4], where Φ Β is the background flux incident on the detector, and is dependent on the field of view (FOV) and the temperature of the background. D* BLIP λ η = qhc 2ΦB 1 2 (4.6) BLIP stands for background limited infrared photodetector and D* BLIP represents the value of D* required by the photodetector such that the noise produced by the detector is not greater than the background noise associated with a particular application. If we consider blackbody radiation as the background source, then the background photon flux incident on the detector that is detected, Φ B, can be calculated by [54]: 101

114 Chapter 4 LWIR Device Characterisation and Performance Evaluation λco 3 2 φb = E( λ, T) dλ = f( λc, T) σ q T sin θ (4.7) 0 where λ CO is the cutoff wavelength; T is the blackbody temperature; σ = cm s q is the photon equivalent of the Stefan-Boltzmann constant; E(λ,T) is the blackbody irradiance; f(λco,t) is the fraction of blackbody radiation photons in the range [0, λ CO ]; and θ is the half-angle subtended at the detector by the background which defines the FOV, as shown in Fig f(λ CO,T) can be approximated to an analytic form provided λ T 5000 µ m.k : hc 2 81 hc 1 hc λkt 4 π λkt 2 λkt f( λ, T) = exp 1+ + (4.8) By equating Eqn. 4.5 with Eqn. 4.6, a minimum value of R 0 A can be determined such that the thermal noise generated by the photodiode is not greater than the background noise of the scene. That is, the required R 0 A is given by: 4kT RA= (4.9) 0 2 2q ηφb Equation 4.9 is plotted as a function of field of view, θ, in Fig for several background temperatures and an assumed quantum efficiency of η = 0.7. A 10 µm cutoff wavelength was also chosen for comparison with the devices fabricated in this thesis. 102

115 Chapter 4 LWIR Device Characterisation and Performance Evaluation R 0 A (Ωcm 2 ) Background Temperature 150 K 300 K 200 K 350 K 250 K 400 K FOV 10 0 Detector θ (degrees) Fig Minimum R 0 A required for BLIP operation as a function of θ, where θ defines the FOV as shown, and for quantum efficiency = Analysis of R 0 A Data Detailed analysis of R 0 A data to extract the various current components (diffusion, g-r, tunnelling, etc) is described in Chapter 5. An alternative approach to analysis of R 0 A data is to consider the variation of R 0 A as a function of the perimeter to area ratio (P/A), and is often used to assess photodiode performance and to separate out the relative influence of surface- and bulkgenerated dark currents on limiting device performance. The experimental data is obtained by fabricating a number of experimental device lots, and measuring the zero bias dynamic resistance for each of the many photodiodes of various sizes. Although it is an accepted characterisation procedure to collect variable area R 0 A data in order to perform R 0 A versus P/A analysis, there is some disagreement as to the interpretation of the resultant data. [55-57] Analysis of R 0 A versus P/A to identify and separate the limiting dark current components is possible because, as the size of the photodiode varies, the P/A ratio also varies. Conceptually, the perimeter dimension defines the region where the junction intersects with the surface, whereas the junction in the bulk region is given by the dimensions of the p-to-n type 103

116 Chapter 4 LWIR Device Characterisation and Performance Evaluation R 0 A (Ωcm 2 ) P/A (cm -1 ) Fig Experimental R 0 A vs Perimeter/Area ratio (P/A) for gold doped LWIR devices from TN7 at 80K. converted area. Thus, a plot of 1/ R 0 A versus P/A will be able to differentiate between whether the limiting dark current component originates from the junction at the surface or in the bulk. The R 0 A versus P/A plot for devices from device lot TN7 at 80 K is shown in Fig. 4.11, where it is noted that the data have been grouped into two shaded bands to indicate the two distinct groupings of devices that can clearly be identified. The higher performing devices are separated from the defective devices by approximately two orders of magnitude difference in R 0 A value. The performance of devices was also found to have a spatial dependence, with defective devices being clustered close to each other on the wafer, and with higher performing devices also being located close to each other on the wafer. It is also worth noting that both groups have approximately the same rate of decrease of R 0 A with increasing P/A. The fact that R 0 A decreases with increasing P/A ratio is a clear indication that dark current mechanisms arising from junction regions at the HgCdTe surface are dominant over those originating from 104

117 Chapter 4 LWIR Device Characterisation and Performance Evaluation R S +R Sgr x x x x x R B n x x x x R B p R B R I x x x x x x x x x x x x x x x x x x x x Fig Illustration of the location of the various dark current components. junction regions in the bulk. These results point to a non-ideal interface between the HgCdTe surface and the ZnS/CdTe passivation layer limiting device performance. Analysis of dynamic resistance data for variable area photodiodes commonly consists of deriving an expression for the inverse of the dynamic resistance area product (1/RA) in terms of the perimeter to area ratio (P/A). A plot of 1/RA versus P/A takes the form of a quadratic and data fitting is then used to extract relevant parameters about the contributions of dark current from the bulk and surface regions of the device. Following the reasoning presented in Ref. [55], the dynamic resistance associated with the dark current mechanisms in the device can be expressed by Eqn. 4.10, which considers that the total measured dynamic resistance (R) is composed of various components including a component due to surface band-bending where the junction terminates at the surface (R S ), a component due to surface g-r (R Sgr ), a component due to enhanced recombination at the interfaces of the HgCdTe epilayer (R I ), and a component due to the dark current generated in the bulk region (R B ). The various dark current components considered, and the regions over which they are effective, are represented in Fig = (4.10) R RB RS RSgr RI To obtain a relationship between the dynamic resistance and the P/A ratio, consideration must be given to the various regions over which each component is significant. Figure

118 Chapter 4 LWIR Device Characterisation and Performance Evaluation illustrates the regions for a homojunction planar device in which each of the components apply and the relevant dimensions for a circular shaped device are shown in Fig Using Eqn 4.10, an expression in terms of the dynamic resistance area product can be written: = (4.11) RA RB AB RS AS RSgr ASgr RI AI The relevant areas are related to the dimensions of the device by the following equations where A is the idealised 1-D junction area (defined by the mask dimensions plus the lateral typeconversion), P is the perimeter of the junction, j is the junction depth, L d is the minority carrier diffusion length and W S is the depletion width at the surface. A graphical depiction of the dimensions of the planar device structure is given in Fig AB = A+ Pj (4.12) 2 Ld P AS = + PL d (4.13) 4 A A Sgr = PW (4.14) S A = A+ A (4.15) I S Substituting the above expressions for area into Eqn. 4.11, the following expression for 1/RA versus P/A ratio can be arrived at [55]: 2 1 L d 1 1 P = + RA 4 RSAS RIAI A 1 1 j W S P + Ld RS AS RI AI RB AB RSgr ASgr A RA B B RA I I 2 (4.16) The above equation indicates that extracting the various surface and bulk components is not trivial, since the term R I appears in all three coefficients to the quadratic equation. Additionally, the diffusion length, L d, is required to be determined, which would involve an independent measurement of spatially resolved photocurrent for the device [57]. 106

119 Chapter 4 LWIR Device Characterisation and Performance Evaluation A P W S j Fig.4.13 Definition of the dimensions of a planar photodiode. The set of graphs in Fig.4.14 gives the 1/R 0 A versus P/A plots for the various LWIR device lots. The graphs also include a fit of a quadratic function (Eqn. 4.16) to the data points of the highest performing devices. Note that the results for TN3 could not be fitted to Eqn due to the high degree of scatter in the data. Devices TN8A and TN8B were fabricated on the same wafer and as one process, whereby the HgCdTe epilayer was initially passivated with a 1 µm layer of CdTe followed by a 0.2 µm layer of ZnS. TN8A devices then had the ZnS layer removed using a HCl etch, whereas the ZnS layer was retained for TN8B devices. 107

120 Chapter 4 LWIR Device Characterisation and Performance Evaluation TN1 80K, Experimental Best Devices Fit 5 T= 80K TN /R 0 A (Ω -1 cm -2 ) 3 2 1/R 0 A (Ω -1 cm -2 ) (a) P/A (cm -1 ) TN4 80K, Experimental Best Devices Fit (b) P/A (cm -1 ) TN6 80K Experimental Fit 1/R 0 A (Ω -1 cm -2 ) /R 0 A (Ω -1 cm -2 ) (c) P/A (cm -1 ) P/A (cm -1 ) 1.0 (d) 0.8 TN7 80K, Experimental Best Devices Fit 0.8 TN8A 80K, Experimental Best Devices Fit 1/R 0 A (Ω -1 cm -2 ) /R 0 A (Ω -1 cm -2 ) P/A (cm -1 ) (e) P/A (cm -1 ) (f) Fig /R 0 A versus P/A data at 80 K for the fabricated device lots. The theoretical fit to the best devices for each device lot is also included. The figure continues on the next page. 108

121 Chapter 4 LWIR Device Characterisation and Performance Evaluation TN9 80K, Experimental Best Devices Fit 1/R 0 A (Ω -1 cm -2 ) /R 0 A (Ω -1 cm -2 ) TN8B 80K, Experimental Best Devices Fit P/A (cm -1 ) 3.0 (g) (h) P/A (cm -1 ) TN13 80K, Experimental Best Devices Fit 1/R 0 A (Ω -1 cm -2 ) /R 0 A (Ω -1 cm -2 ) TN11 80K, Experimental Best Devices Fit (i) P/A (cm -1 ) P/A (cm -1 ) (j) /R 0 A (Ω -1 cm -2 ) TN15 80K, Experimental Best Devices Fit (k) P/A (cm -1 ) Fig (continued) 109

122 Chapter 4 LWIR Device Characterisation and Performance Evaluation The 1/R 0 A versus P/A plots in Fig generally have a high degree of scatter. This scatter is consistent with the presence of a high density of localised defects, sometimes called killer defects. If these defects happen to be located in the vicinity of the p-n junction, then a dramatic decrease in diode performance can be expected. Damage to devices due to handling and the wire bonding process is another factor contributing to the large scatter observed. Because of this factor, no conclusions relating to the primary fabrication process can be drawn by comparing the degree of scatter between the different device lots. By considering only the highest performing devices when fitting to Eqn. 4.16, it is assumed that the effect of localised defects and damaged devices caused by handling can be minimised. Without additional information such as the minority carrier diffusion length, and because of the large scatter in the data even when considering only the best devices, it is difficult to obtain quantitative information and make firm conclusions by using Eqn to fit the data plotted in Fig Although the data is not consistent enough in order to fully utilise Eqn to separate the impact of surface and bulk effects on the fabricated photodiodes, general trends, or lack thereof, can be distinguished between the devices. Comparing the theoretical fit to the best devices in Fig. 4.14, and noting the quadratic form of Eqn it can be deduced that the influence of the surface related components varies greatly between the sets of devices since there is a large variation in the slope of the curves. The slope and how the slope varies with P/A is determined by the coefficients to the (P/A) 2 and P/A terms in Eqn. 4.16, which are both determined by surface related effects. The 1/R 0 A intercept of the fit to the 1/R 0 A versus P/A data in Fig also shows a large variation between sets of devices. This is evident from the data presented in Table 4.1, where the intercept values have been inverted to obtain the theoretical R 0 A for an infinite area photodiode. According to Eqn the intercept term is composed of a combination of two components: the bulk component, R B, and the component due to recombination at non-ideal interfaces outside the junction, R I. However, the bulk component, R B, should be reasonably constant across all device lots since (i) all starting wafers have very similar x values, (ii) the plasma induced junction formation process was kept constant 110

123 Table 4.1 Summary of R 0 A data for fabricated device lots. Chapter 4 LWIR Device Characterisation and Performance Evaluation Device Infinite Area R 0 A Infinite Area R 0 A Surface Starting p-type Lot (Ωcm 2 ) 80K (Ωcm 2 ) 100K Passivation material TN µm ZnS Au TN (Device with highest R 0 A) µm ZnS Vac TN µm ZnS Vac TN TN µm ZnS 0.1 µm CdTe 0.2 µm ZnS 0.1 µm CdTe Vac Au TN8A µm CdTe Au TN8B µm ZnS 0.1 µm CdTe Au TN µm CdTe Au TN µm CdTe Au TN µm CdTe Au TN µm ZnS 1 µm CdTe Au throughout, and (iii) there is no obvious trend differentiating vacancy-doped from Au-doped material. Thus it can be concluded that the large variation in infinite area R 0 A at 80 K can be attributed to large variations in the R I component. Since it is also reasonable to assume that the CdZnTe/HgCdTe interface for all device lots are similar, then it can be concluded that the quality of the HgCdTe/passivation layer interface is the main contributor to the R I component, and that variations in the quality of this interface between device lots gives rise to the large variations in infinite area R 0 A. Comparing the ZnS passivated devices of TN1, TN3 and TN4 to the CdTe passivated devices of TN6, TN7, TN8 and TN9, there is approximately an order of magnitude improvement for CdTe passivated devices at 80 K (see Table 4.1). This indicates that the 111

124 Chapter 4 LWIR Device Characterisation and Performance Evaluation TN8 80K TN8A TN8B 1/R 0 A (Ω -1 cm -2 ) P/A (cm -1 ) Fig Theoretical fit of 1/R 0 A versus P/A for the best devices from TN8A and TN8B at 80 K. process used to deposit ZnS for the purpose of passivating the HgCdTe surface should be abandoned in preference to using CdTe as the passivant. Devices from sample TN8A and TN8B are identical with the exception of an additional ZnS layer deposited on both sets of devices, but not subsequently removed on TN8B. These samples were part of a single wafer and processed simultaneously and therefore a direct comparison is valid. The theoretical fit to 1/R 0 A versus P/A for the best devices from TN8A and TN8B are shown in Fig and it indicates that the additional ZnS layer adversely affects the junction at the surface with the 1/R 0 A increasing more rapidly with P/A. Also notable is that the intercept values are approximately equal which is what is expected since the junction in the bulk region and the HgCdTe/CdZnTe interface are the same in both cases. However, because TN8B lacks data for smaller devices, this data should be treated with caution. Devices from lots TN11, TN13 and TN15 exhibit lower performance at 80 K in comparison to the other CdTe passivated devices from lots TN6, TN7, TN8 and TN9. The difference in characteristics of the area dependence for these devices is clearly evident from Fig A difference in the processing that can be identified between these two batches of devices is that following the short etch-back of the surface using a dilute (0.01%) Br 2 -methanol solution, the device lots TN11, TN13 and TN15 were left soaking in deionized water for 112

125 Chapter 4 LWIR Device Characterisation and Performance Evaluation 0.5 1/R 0 A (Ω -1 cm -2 ) T =80K TN6 TN7 TN9 TN11 TN13 TN P/A (cm -1 ) Fig Theoretical fit of 1/R 0 A versus P/A for the best devices from CdTe passivated device lots at 80 K. approximately one hour before being dried and transferred to the CdTe deposition chamber. In all other device lots, after the Br 2 -methanol etch-bake the samples were immediately rinsed with methanol and dried with N 2. Another common factor among the TN11, TN13 and TN15 devices is that they were fabricated from the same starting wafer. However, the large variation in the infinite area R 0 A at 80 K and the large variation in the slope of the 1/R 0 A vs P/A dependence is not consistent with a hypothesis that suggests that the starting wafer was from a particularly bad batch. If this were the case, then the bulk properties of the fabricated devices would be expected to be more consistent. A study of the R-V characteristic for these devices strongly suggests that surface related effects are dominating the characteristics. In Chapter 6 a study of a gated photodiode fabricated as part of TN15 provides strong evidence that this is the case. As the temperature is increased above 80 K, the influence of surface band-bending on the total dark current is reduced due to widening of the bandgap and, furthermore, the diffusion and g-r current components in the bulk region increase exponentially with temperature. Thus, the bulk dark current components are more dominant at 100 K compared to 80 K, indicating that the 100 K data will be less sensitive to surface effects. Comparing the results for various device lots at 100 K in Fig it is evident that the characteristics of the P/A data are much more uniform at 100 K, which suggests that the bulk properties of the n-on-p junctions formed by the 113

126 Chapter 4 LWIR Device Characterisation and Performance Evaluation 2.0 1/R 0 A (Ω 1 cm -1 ) T = 100 K TN4 TN6 TN7 TN8A TN8B P/A (cm -1 ) Fig.4.17 Theoretical fit of 1/R 0 A versus P/A for the best devices at 100 K. plasma induced type conversion process are fairly consistent between vacancy and gold doped material. 4.7 The Effects of Vacuum Baking on Photodiode Performance As noted in Section 4.4, vacuum baking is an important process in the packaging of cryogenically cooled detectors. Thus, in order to assess the stability of the fabrication process, devices from lot TN9 where characterised before baking and at several stages during the vacuum baking process. TN9 was a device lot fabricated on Au-doped HgCdTe passivated with CdTe and, as processed, showed generally lower R 0 A figures than the earlier device lots passivated with CdTe (TN8, TN7, and TN6). The experimental results indicate that there are significant changes to device performance after vacuum baking at 80 C for periods of the order of a few days. In general, the device performance is observed to improve after a period of vacuum baking. This is clearly evident in Fig and Fig which show that after a 24 hour baking process there is a significant reduction in dark current in the reverse bias regime and a corresponding increase in the dynamic resistance. 114

127 Chapter 4 LWIR Device Characterisation and Performance Evaluation After 24 hour bake at 80 0 C and 72 hour bake at 80 0 C Current (µa) As-processed Diode Bias (V) Fig.4.18 Dark current I-V characteristics at 80 K for an as-processed device from TN9 and after several stages of vacuum baking. Dynamic Resistance (Ω) Pre-bake: Post-Bake: After 80 O C After 80 O C Diode Bias (V) Fig.4.19 R-V characteristics at 80 K for an as-processed device from TN9 and after several stages of vacuum baking. 115

128 Chapter 4 LWIR Device Characterisation and Performance Evaluation 10 6 TN9 T=80K Maximum R (Ω) Vacuum Bake Time (Hours) Fig Maximum dynamic resistance, R, at 80 K for the TN9 device of Fig after various stages of vacuum baking at 80 C. It is immediately apparent from Fig that there is a vast improvement in the R-V characteristics after the first vacuum bake of 24 hours. Further baking for an additional 48 hours results in only a small additional change in the characteristics. It is noted that the forward bias characteristic remains essentially unchanged throughout the vacuum baking process; however, there is approximately an order of magnitude increase in the dynamic resistance in the reverse bias regime. The forward bias characteristic is dominated by diffusion and g-r current, whereas in reverse bias it is the tunnelling current that dominates, which is strongly dependant on the electric field across the depletion region. The strength of the junction breakdown components can be gauged from the maximum dynamic resistance value because it is the point where the tunnelling is equal to the diffusion and g-r components. A plot of maximum dynamic resistance versus baking time is shown in Fig The strong influence of the junction breakdown mechanisms for the as-processed device and the observed increase in dynamic resistance after vacuum baking may be indicative of an improved CdTe/HgCdTe interface since surface band-bending is the major cause of tunnelling currents. Therefore, a reasonable explanation for the observed improvement in characteristics after the initial vacuum baking period is that the extended exposure to high temperatures either removes/getters/annihilates localised defects which induce high localised electric fields and/or 116

129 Chapter 4 LWIR Device Characterisation and Performance Evaluation λ co = 9.7µm Responsivity (A/W) Pre-bake After 80 0 C After 80 0 C Wavelength (µm) Fig.4.21 Spectral responsivity at 80 K of a TN9 device after various stages of vacuum baking at 80 C. the vacuum bake serves as an anneal that improves the surface passivation properties resulting in a reduction of surface band-bending and hence high electric fields at the surface. Figures 4.19 and 4.20 also show that after the initial improvement in R 0 A, there is only a marginal change after extended bakes longer than 24 hours. This is indicative of the fact that the plasma induced type conversion process forms a stable p-n junction since there is no significant evidence of any long-term instability. This is similar to previous conclusions on RIE induced junctions on MWIR photodiodes [44]. The spectral responsivity at 80 K of the as-fabricated and vacuum baked photodiode is shown in Fig. 4.21, which indicates that there is also an improvement in the responsivity of the photodiodes with vacuum baking, and is consistent with the improved R-V characteristics. Although there is an increase in the overall responsivity with vacuum baking, the cut-off wavelength remains unchanged at 9.7 µm. These measurements were performed by frontside illumination of the device, which means that the majority of incident photons will be absorbed 117

130 Chapter 4 LWIR Device Characterisation and Performance Evaluation in the region near the HgCdTe surface. The increase in responsivity may therefore indicate that the surface properties have been improved by the baking process, since trapping of carriers at the HgCdTe surface will decrease the photogenerated carrier lifetime. This decrease in trapping due to extended baking may result from the thermal annealing of traps at the CdTe/HgCdTe interface and/or charge de-trapping within the passivation layer. 4.8 Chapter Summary and Conclusions It is essential to characterise the performance of the fabricated photodiodes in order to ascertain the success or otherwise of the fabrication process, and also to gain an understanding of the mechanisms limiting device performance through analysis of experimental data and comparison to theoretical models. Different characterisation techniques are required to probe the various aspects of photodiode performance and the main characterisation techniques employed in this thesis include measurement of the I-V/R-V characteristic, spectral responsivity, and noise. To obtain a more complete understanding of the fabricated devices, the measurements were conducted as a function of temperature and diode bias. Devices were also fabricated in varying sizes to aid analysis. To compare the performance of devices from the various device lots the zero-bias dynamic resistance-area product (R 0 A) figure of merit, which is obtained from I-V measurements, was used. Using this criterion, it was found that Au-doped material passivated with CdTe produced the best devices. However, at this early stage of device development, there is a lot of variation in performance between device lots, even among the CdTe passivated Audoped device lots. Evidence points to surface effects dominating device performance and the strong likelihood that the variation observed between device lots is due to modifications applied to the surface passivation process for each device lot. Even subtle differences in surface passivation processes can have a substantial effect on the completed devices. In contrast, there is 118

131 Chapter 4 LWIR Device Characterisation and Performance Evaluation evidence that suggests that the properties of the junction in the bulk regions are uniform between device lots. The effect of vacuum baking on device performance was also examined in this chapter. It was found that for devices from device lot TN9, the vacuum baking process results in an increase in overall device performance, evident in an improvement of the R-V characteristic and spectral responsivity. The improvement in performance was attributed to an improvement of the CdTe/HgCdTe interface induced by the baking process. 119

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133 5 Dark Current Modelling Chapter 5 Dark Current Modelling Modelling of device phenomena and fitting of the model to experimental data can provide valuable information that assists in understanding device behaviour and limitations. This is especially true when the models are based on physical phenomena. As part of this thesis, analytical models were developed for the fabricated LWIR photodiodes to analyse the measured I-V characteristics. Since the dark current models are based on semiconductor device physics, they are extremely useful for identifying and evaluating factors which are limiting device performance, and can give an indication of steps that need to be taken to improve the fabrication process and eliminate those factors. To a close approximation, the I-V characteristic of a photodiode is determined by two independent components, as given in Eqn. 5.1 [23]: IV (, Φ ) = I ( V) I ( Φ ) (5.1) The total current I(V,Φ) through an illuminated diode is a function of voltage, V, and photon flux, Φ, and is equal to the current through the non-illuminated diode, I d (V), minus the photocurrent generated by the photon flux, I ph (Φ). The current through a non-illuminated diode is a function of the applied voltage only and is referred to as the dark current. It is this component which ultimately determines the signal-to-noise ratio, and therefore the performance of the diode as a photodetector. The photodiode dark current model is composed of several components that can be considered independently, but are summed together to obtain the total dark current. Only the total dark current can be directly compared to the experimental data. However, the temperature and bias dependence of components can allow isolation of the effects of the individual dark current components, from which valuable information can be obtained about the device. d ph 121

134 Chapter 5 Dark Current Modelling The model is expressed in terms of current densities but analysis of the experimental data using the model are performed using the dynamic resistance-area product which is the value obtained by differentiating the current density expressions. The application of the model in analysing the experimental data is also presented in the following chapters. This chapter describes each of the dark current components and how they are modelled. Illustrations of the voltage and temperature dependencies that can be expected are also included. 5.1 The Photodiode Dark Current Model The current mechanisms which determine the I-V characteristics of a p-n junction photodiode can be grouped into three broad categories: (i) drift currents arising from the force exerted on charge carriers under the influence of an electric field; (ii) currents arising from generation and recombination processes; and (iii) currents arising from the breakdown of the junction. The drift current mechanism results in the familiar Ohm s law relationship and is expressed in Eqn. 5.2, where E is the electric field, n is the carrier density and µ is the carrier mobility. J drift = qµ E n (5.2) In semiconductors, conduction electrons and holes can be generated thermally or by optical generation due to absorption of incident photons with energy greater than the bandgap energy. The mobile charge carriers can also recombine through various processes. These various generation and recombination processes may vary between different regions, forming spatial variations in carrier density and carrier energy, and generating current via the diffusion process. The current mechanisms in a semiconductor device due to the drift and diffusion mechanisms are described by the following equations: J = qµ ne + qd n (5.3) n n e J = qµ pe + qd p p p h (5.4) Jc = Jn + J p (5.5) 122

135 Chapter 5 Dark Current Modelling where J n and J p are the current densities due to the drift and diffusion of electrons and holes, respectively, n and p are the density of electrons and holes, and µ n and µ p are their respective mobilities. The total current density, J c, is obtained by summing the electron and hole components. The generation and recombination processes can be incorporated by the continuity equations, where G opt is the optical generation rate, U is the net generation rate, and D e and D h are the diffusivity of electrons and holes, respectively: n 1 = Gopt, n Un + J n (5.6) t q p 1 = Gopt, p Up + J p (5.7) t q Applying the drift and diffusion considerations to a p-n junction, it can be established that at thermal equilibrium a space charge region will form around the metallurgical junction such that there is a zero net current across the junction. Since there is a large difference in electron concentration and hole concentration from the n-side to the p-side, electrons will diffuse from the n-side to the p-side and holes will diffuse from the p-side to the n-side. This migration of carriers leads to a charge imbalance and, in turn, the imbalance in charge generates an electric field that opposes the further movement of carriers across the junction due to the diffusion process. The result is that at thermal equilibrium there is zero current flow. In fact, at equilibrium J n = J p = 0 and there exists a space charge region on either side of the metallurgical junction, referred to as the depletion region, which supports a voltage referred to as the built-in potential of the junction. This situation is illustrated in Fig. 5.1, which assumes an abrupt junction. The depletion region, depletion width, built-in potential, charge density and electric field are also indicated. The depletion region is so called because it is depleted of mobile carriers. The charge density is also high in this region and, consequently, it may also be referred to as the space charge region. The properties of the junction such as electric field, charge density and potential can be obtained using Maxwell s equations, in particular Poisson s equation, which, for the 1-D, case is given by: 123

136 Chapter 5 Dark Current Modelling E 2 dv d q = = 2 p n + N D N A dz dz εε s 0 ( ) (5.8) Using the abrupt-junction approximation for non-degenerate semiconductors, the builtin potential voltage for non-degenerate semiconductors is given by Eqn. 5.9, where n n0 is the electron concentration in the n-type region, p p0 is the hole concentration in the p-type region, and n i is the intrinsic carrier concentration: V bi kt n p kt N N = ln q n q n n0 p0 D A ln 2 2 i i (5.9) The width of the depletion region for non-degenerate semiconductors is given by [52]: W = 2 εε s 0( NA+ ND)( Vbi V) qn N A D (5.10) Under thermal equilibrium conditions the net current is zero by virtue of the fact that drift currents balance the other current mechanisms. However, when equilibrium conditions are disturbed the various currents can be measured. The currents resulting from majority carriers generated in their respective n-type or p-type regions diffusing across the depletion region and recombining in the opposite region as minority carriers, will be referred to as the diffusion current in this thesis. Diode current resulting from generation and recombination processes within the depletion region is referred to as generation-recombination (g-r) currents. The final class of diode current considered in this thesis is the junction breakdown currents. These mechanisms result in increased current in reverse bias and can include band-toband tunnelling, trap-assisted tunnelling and avalanche multiplication. Avalanche multiplication will not be considered since it has an insignificant effect in comparison to the other components for the diode biasing range examined in this thesis, which covers most practical situations. The dark current models presented in this chapter are expressed in terms of current densities (Acm -2 ), however, the dynamic resistance characteristic is more suitable for data analysis. To obtain the R-V characteristic from the current density it is necessary to integrate the 124

137 Chapter 5 Dark Current Modelling current density over the junction area for which the dark current component is effective. Equation 4.1 can then be applied to obtain the R-V characteristic. That is, and I = JdA = AJ (5.11) A 1 1 di 1 dj RV ( ) = = dv A dv (5.12) For a 1-D model of a photodiode, A is simply the junction area and is well defined. For a 2-D or 3-D model of a photodiode where the properties of the junction may have spatial variation, for example, due to the effect of surface band-bending, the value of A must be determined for each dark current component. Alternatively, a dynamic resistance-area product characteristic (RA-V) can be defined which has all the characteristics of the R-V but is not scaled with the size of the photodiode. That is, dj RA( V ) = dv 1 (5.13) 5.2 Diffusion Current Expressions for the diffusion current for a photodiode can be obtained by solving the set of Eqns. 5.3 to 5.7. To make this task tractable, certain simplifications and boundary conditions need to be assumed. These include: a. A 1-D p-n junction diode is assumed as illustrated in Fig b. The photodiode is not illuminated, hence the optical generation term, G opt in Eqn. 5.6 and Eqn. 5.7, is zero. For LWIR and MWIR photodetectors to be not illuminated requires all surrounding objects which the detector sees to be at the same temperature as the detector: that is, the surrounding objects must also be cooled so that the diode is in the dark as far as optical radiation is concerned that is of a high enough energy to generate electron-hole pairs. c. Low-level injection conditions prevail and the net recombination rate is given 125

138 Chapter 5 Dark Current Modelling by Eqn. 5.14, where n and p are the excess minority electron and hole concentrations, and τ e and τ h are their respective lifetimes. U n p = and U = (5.14) τ τ e h Under these assumptions, Eqn. 5.6 and Eqn. 5.7 reduce to: 2 d n e 2 n 0 e D = (5.15) dz τ 2 d p h 2 p 0 h D = (5.16) dz τ These equations can then be solved by considering the appropriate boundary conditions. With the assumption that the quasi-fermi levels are constant across the depletion region, the minority carrier concentrations at the edges of the depletion region are: qv nw ( ) = np0 exp (5.17) kt qv p(0) = pn0 exp (5.18) kt where V is the voltage applied across the junction. In cases where the device is not a long-base diode, properties of the interfaces at the surface, contacts, etc, need to be considered since they can act as recombination sites. For the 1-D case considered, with the contact interface characterised by a surface recombination velocity s 0 (see Fig. 5.1), the solution for n(z) in the p-region is given by Eqn. 5.19, where z and d are the distances defined in Fig. 5.1, and L e is the diffusion length for electrons [23]. z d sl 0 e z d cosh sinh qv Le De Le nz ( ) = np0 exp 1 kt d sl 0 e d cosh + sinh Le De Le (5.19) 126

139 Chapter 5 Dark Current Modelling Fig. 5.1 A graphical representation of a 1-D p-n junction showing the relationship between the band diagram, charge density and electric field. 127

140 Chapter 5 Dark Current Modelling The electron diffusion current can then be obtained: d n De qv Je = qde = qnp0 exp 1 α p dz z= 0 Le kt (5.20) where α p is given by: α p = sl 0 e d + tanh De Le sl d + De Le 0 e 1 tanh (5.21) Similarly, the hole diffusion current can be obtained by considering the n-region: J h Dh qv = qpn0 exp 1 α n (5.22) Lh kt where α = n sl 0 h d + tanh Dh Lh. sl d + Dh Lh 0 h 1 tanh The total diffusion current density is the sum of the hole and electron current, and using the Einstein relations, D, eh kt = µ eh,, it can be written as: q J qn kt qn kt qv exp 1 (5.23) N q N q kt i e i h diff = α µ p + α µ n A τe D τh The expression for α p,n derived previously applies to a 1-D case where there is only the contact interface located a distance d from the depletion region (see fig. 5.1). For more complicated device structures such as the fabricated devices of this thesis, multiple interfaces need to be considered and not all parts of the interface are equi-distant from the junction. A 2-D or 3-D model is required to fully determine α n,p which accounts for the effect of the various interfaces present. These include the HgCdTe/substrate interface, HgCdTe/surface passivation interface, and the contacts. In all cases the effect on the diffusion current of each interface will be similar, with the values of α n,p being determined by the surface recombination velocity and 128

141 Chapter 5 Dark Current Modelling 10 s 0 = 10 L/τ s 0 = 5 L/τ s 0 = 2 L/τ s 0 = L/τ α n,p 1 s 0 = 0.2 L/τ s 0 = 0.1 L/τ s 0 = 0.5 L/τ Fig. 5.2 Theoretical plot of α as a function of normalised diode length (d/l e ) plotted for various values of surface recombination velocity (s 0 ). d/l the distance from the edge of the depletion region relative to the diffusion lengths, L e,h. The plot of α n,p as a function of normalised diode length (d/l e ) plotted for various values of s 0 is shown in Fig. 5.2, which shows that: α α α > 1 for s L > τ < 1 for s L < τ = 1 for s L = τ np, 0 np, 0 np, 0 The results in Fig. 5.2 indicate that diffusion currents can be decreased (leading to increased device performance) by making the diode as short as possible provided that the interfaces are electrically reflecting ( s 0 L ). This method of improving photodiode τ performance is limited by the optical absorption of HgCdTe since not all incident signal photons can be absorbed if the HgCdTe layer is too thin. One method of overcoming this thickness limitation is to enable multiple passes of the IR signal through a comparatively thin detector. 129

142 Chapter 5 Dark Current Modelling RA Hole Current N D =10 15 cm -3 N D =5x10 15 cm -3 N D =10 16 cm -3 Electron Current N A =10 15 cm -3 N A =5x10 15 cm -3 N A =10 16 cm Diode bias (V) Fig. 5.3 The R-V characteristic for electron and hole diffusion current for a p-n junction at 80K. Refer to Table 5.1 for other parameter values. The diffusion current density component has a rather simple exponential voltage dependence, with the magnitude characterised by the saturation current, J s, which does not depend on the applied bias voltage: J qn kt µ qn kt µ 2 2 i e i h S = αp + αn NA qτe ND qτh (5.24) The plot of the RA-V characteristic on a log-linear scale is a constant slope graph, as shown in Fig. 5.3, and variations in the parameters result in the R-V plot shifting vertically. In Fig. 5.3 the RA-V for the electron diffusion current is plotted for N A varying from to cm -3, with N D = cm -3 ; and the RA-V for hole diffusion current is plotted for N D varying from to cm -3, with N A = cm -3. Given that typical doping densities for fabricated devices are N A =10 16 cm -3 and N D = cm -3, the plot indicates that the diffusion of electrons tends to dominate over hole diffusion; that is, the diode is effectively a one-sided junction. Therefore, optimisation of the p-type region to minimise diffusion current will have a significant impact on device performance. The data plotted in Fig. 5.3 were obtained by setting the parameters to the values indicated in Table 5.1, with the exception of N A and N D which are indicated on the graph. The parameter values in Table 5.1 are also used as the default values to 130

143 Chapter 5 Dark Current Modelling Table 5.1 Default parameter values used to illustrate dark current models. N A cm -3 N D cm -3 N t cm -3 E t 0.7 E g τ e 1 µs τ h 100 µs τ ns s cm.s -1 x 0.23 generate the other illustrative graphs of the other dark current mechanisms in this chapter. Whenever a parameter is changed from that listed in Table 5.1, it is indicated on the graph. 5.3 Generation-recombination Current Shockley-Read-Hall (SRH) type g-r centres in the space charge region can contribute significantly to the photodiode dark current. The SRH process is explained with reference to Fig Defects and impurities in the crystal can introduce energy levels into the forbidden bandgap which can act as intermediate levels for the transition of holes and electrons to and from the conduction and valence bands. As the transition probability is strongly dependent on the size of the step, the position of the trap in the bandgap has an important role to play. Figure 5.4 shows the four processes which can occur at a SRH g-r centre: capture of an electron from the conduction band at rate r 1. emission of an electron to the conduction band at rate r 2. capture of a hole from the valence band at rate r 3. emission of a hole to the valence band at rate r

144 Chapter 5 Dark Current Modelling Fig. 5.4 An illustration of generation and recombination processes from a SRH g-r centre. An electron can be captured (r 1 ) by the g-r centre when an electron from the conduction band transitions to the trap level (E t ), and emitted (r 2 ) when an electron from the trap level transitions to the conduction band. A hole can be captured (r 3 ) by the g-r centre when an electron from the valence band transitions to the trap level, and emitted (r 4 ) when an electron from the trap level transitions to the valence. The rate of electron capture is proportional to the number of electrons in the conduction band (n), and the density of empty SRH centres given by Eqn. 5.25, where N t is the density of g-r centres, f is the probability function, and E t is the trap energy. ( 1 ( )) n = N f E (5.25) t t t The electron capture rate is also proportional to the capture cross-sectionσ, hence: ( ) r1 = nnt 1 f( Et) υt hσ n (5.26) where υ th is the carrier thermal velocity. The rate of electron emission is given by Eqn. 5.27, where e n is the emission probability. r2 = Nt f( Et) e n (5.27) The emission probability can be expressed in terms of the previously defined quantities by considering r 1 and r 2 at thermal equilibrium. At thermal equilibrium r 1 = r 2 and the electron emission probability is given by Eqn 5.28 if Fermi-Dirac statistics are assumed and f is the Fermi function, and E i is the intrinsic Fermi-level energy: e Et Ei = υσn exp kt (5.28) n th n i n 132

145 Chapter 5 Dark Current Modelling Following similar reasoning, r 3 and r 4 can be written as: r3 = pnt f ( Et) υthσ p (5.29) ( ) r4 = Nt 1 f( Et) e (5.30) p e Ei Et = υσn exp kt p th p i (5.31) The net generation rate, U is given by: U R G = r r = r r (5.32) sp sp U = 2 ( ) Nυσσ np n t th n p i Et Ei Ei Et σn n+ niexp + σ p p+ niexp kt kt 2 np ni = Et Ei Ei Et τn n+ niexp + τ p p+ niexp kt kt (5.33) where τ = τ ( N υ σ ) n t th n = ( N υ σ ) p t th p This derivation of the net generation rate considers the effect of SRH trapping centres which can be characterised by the electron and hole carrier lifetimes, τ n and τ p, respectively, but more generally, there are other recombination mechanisms which may need to be considered, for example, Auger recombination. The effect of each mechanism can be characterised by a carrier lifetime value, and the combined effect can be summarised in a lifetime value that is obtained from the sum of reciprocals of the individual lifetime values. To obtain the expression for the current density the net generation rate is integrated over the depletion region as shown in Eqn g r W J = q U( x) dx 0 (5.34) 133

146 Chapter 5 Dark Current Modelling It is not generally possible to obtain a closed-form expression for J g-r but, as shown in Ref. [58], an approximate expression can be derived for small applied bias (a few kt/q) that is given by Eqn. 5.35, where the carrier lifetime in the depletion region is assumed to be τ 0. qv 2sinh nwkt i J = 2 kt g r ( ) τ V f b (5.35) 0 bi V ( 1 V ) bi f( b) = 0 u 2 du + 2bu+ 1 qv Et Ei 1 τ h b = exp cosh + ln 2kT kt 2 τ e (5.36) For larger reverse bias: qnw i J = g r Et Ei 1 τ h 2τ 0 cosh + ln kt 2 τ e (5.37) 5.4 Band-to-band Tunnelling Current Band-to-band (BTB) tunnelling currents are generated when electrons in the valence band tunnel through the potential barrier of the p-n junction and enter the conduction band, thereby forming a hole in the valence band in the process. The band-to-band tunnelling process is determined by the tunnelling probability which is a function of the potential barrier and the distance through which the electron must tunnel. This has important implications for LWIR photodiodes due to the narrow bandgap of the material. The tunnelling process is schematically represented in Fig. 5.5 and shows how the abrupt p-n junction is best approximated by a triangular potential barrier. It also shows that tunnelling requires the bands to overlap, which usually means that appreciable tunnelling currents are generated only in reverse bias. 134

147 Chapter 5 Dark Current Modelling Fig. 5.5 An illustration of the band-to-band and trap-assisted tunnelling processes for electrons across a p-n junction. Electrons in the valence band see a triangular potential barrier to reach the conduction band. There is a probability that they can tunnel across without requiring energy equal to the barrier height. In the case of band-to-band tunnelling the electrons tunnel directly across, and in the trap assisted tunnelling case, the electron absorbs an amount of energy sufficient to transition to a trap level, from where it can tunnel across to the conduction band. Equation 5.38 gives the current density expression for band-to-band tunnelling assuming a triangular potential barrier [59]. J btb 3 * q 2 m ( /2) e( Vbi V) π m = exp π E g 2q E E * e g E (5.38) The probability for an electron to tunnel across a triangular barrier is dependent on the height of the barrier, which is related to the bandgap energy, and the distance through which it must tunnel which is related to the depletion width of the junction. The dependence on the depletion width is encompassed within the expression for electric field, E, which is given by Eqn and is derived by considering the potential drop across the depletion region. E = qn AND( Vbi V ) 2 εε( N + N ) S 0 A D (5.39) Equation 5.38 shows an exponential dependence of tunnelling current density on the electric field and the bandgap; therefore, it can be expected that band-to-band tunnelling current will be significant for LWIR HgCdTe photodiodes where the bandgap is less than 0.12 ev. For the devices fabricated for this thesis, band-to-band tunnelling current originating in the bulk of 135

148 Chapter 5 Dark Current Modelling RA (Ωcm 2 ) N A =10 16 cm -3 N D =10 15 cm N D =2x10 15 cm -3 N D =3x10 15 cm N D =5x10 15 cm -3 N D =10 16 cm Diode bias (V) Fig. 5.6 The R-V characteristic of band to band tunnelling current for a p-n junction at 80 K. Refer to Table 5.1 for other parameter values. the device can be distinguished only for large reverse bias. This is because the doping density which results from the plasma-induced p-to-n type conversion is relatively low (n-type doping is approximately cm -3 and the p-type doping is also quite low at cm -3 ), which lead to a low value of electric field in the depletion region in the bulk, as indicated by Eqn It should also be noted that the doping density and electric field may be different at the surface compared to the bulk, and hence the two cases should be considered separately. A plot of the R-V characteristics for the band-to-band tunnelling dark current component in Fig. 5.6 shows the impact arising from the variations in the n-type doping density, N D, while keeping N A constant at cm -3. It demonstrates an extremely large variation in the dynamic resistance for a relatively small change in N D over the range from to cm Trap-assisted Tunnelling Current Trap-assisted (TA) tunnelling occurs when an electron in the valence band is thermally excited to a trap level in the bandgap, and from there tunnels through to the conduction band (see Fig. 5.5). The expression for the trap-assisted tunnelling current density is given by Eqn which assumes a single trap level located E t above the valence band [59]. 136

149 Chapter 5 Dark Current Modelling RA (Ωcm 2 ) For E t = 0.7E g : N t =5x10 12 cm -3 N t =1x10 13 cm -3 N t =5x10 13 cm -3 For N t = 1x10 13 cm -3 : E t =0.5E g E t =0.6E g E t =0.7E g Diode bias (V) Fig. 5.7 The R-V characteristic of trap assisted tunnelling current for a p-n junction at 80 K. Refer to Table 5.1 for other parameter values. J tat Et ( Eg ) 2 4 * 2 2 π qmm ( ) 3 e Nt Vbi V Eg 1 = exp f 3 tat h ( Eg Et) 8 2qP E π ftat ( t) = + arcsin(1 2 t) + 2(1 2 t) t(1 t) 2 (5.40) (5.41) The main parameters which influence trap-assisted tunnelling are the trap density, N t, trap level, E t, bandgap energy, and the electric field E. M is the transition matrix element between the trap level and the conduction band and P is the Kane matrix element. The value of M for silicon has been used in the modelling work in this thesis because there have not been any published values of M for HgCdTe. This is the same approach adopted by Refs.[55, 60, 61] among others. The trap energy level (E t ) and trap density (N t ) are the parameters which have the greatest bearing on the trap-assisted tunnelling component for an HgCdTe photodiode of given x value. The effect of variations in these two parameters is illustrated in Fig In general, the trap-assisted tunnelling current increases with increasing trap density, and increases as the trap energy level moves closer to the conduction band. 137

150 Chapter 5 Dark Current Modelling 5.6 Surface Dark Current Considerations The dark current components considered thus far in this chapter were derived assuming an ideal junction with a uniform band structure throughout. Therefore, the current density expressions derived are well suited to the bulk regions of the device, but are inappropriate for the junction near the semiconductor/passivant interface where the band structure may be modified by non-ideal surface passivation. The model for diffusion current presented in this chapter and the expression for surface g-r current of Eqn. 2.3, did give considerations to dark current caused by surface states through the surface recombination velocity parameter, s 0, but the effects of band-bending at the surface were not taken into account. In Chapter 2 it was shown how band-bending modified the depletion region near the surface to create a field-induced junction with properties that are different to those of the bulk region. Depending on surface conditions, the depletion width at the semiconductor surface can either be widened or narrowed, due to the electric field encountered at the surface as a result of interface charges, traps, etc. This has important implications for tunnelling currents because they have an exponential dependence on the electric field (refer to Eqns and 5.40). The expressions for surface tunnelling current density can be obtained for J btb and J tat with modification to the electric field expression to more accurately reflect the electric field at the surface. That is, the band-to-band tunnelling at the surface is given by: J * q 2 m ( V V) π ( me /2) E g = exp 4 (5.42) 2q E b tb, S 3 * e bi btb, S btb, S π Eg where E btb,s is the electric field determining band-to-band tunnelling in the region near the surface. Similarly, the trap-assisted tunnelling at the surface is given by Eqn. 5.43, where E tat,s is the field determining trap-assisted tunnelling in the region near the surface. E J π 3E Et ( ) g 2 4 * 2 2 qmm e Nt( Vbi V) g 1 tat, S = exp f 3 tat E h ( Eg Et) 8 2qP Etat, S (5.43) 138

151 Chapter 5 Dark Current Modelling The effect of surface band-bending on the dark current characteristics will be examined in greater detail in the following chapters. 5.7 HgCdTe Material Parameters In order to numerically evaluate dark current for fitting to experimental data, various material parameters for HgCdTe are required. The parameters used in this work have been taken from published empirical relations, which are summarised below. The bandgap energy (ev) of HgCdTe as a function of x-value and temperature is given by [62] : E x T x x g = (1 2 ) x (5.44) The intrinsic carrier concentration as a function x-value and temperature is given by [63]: E /4 3/2 g ( ) 10 g exp 2 ni = x+ T xt E T (5.45) kt The expression for the effective mass of electrons and holes in HgCdTe are given by Eqns and 5.47, respectively, where m 0 is the rest mass of an electron [64]: m = m Eg * 0 e 2 mp Eg (5.46) m = m * 0 h (5.47) 2 4mP Eg 139

152 Chapter 5 Dark Current Modelling The electron mobility as a function of temperature for 0.2 x 0.6 is given by [65]: b µ e = (5.48) 2a Z where 0.2 a = x 0.6, 0.2 b = x 7.5, Z = T for T > 50 K Z = 2600 T for T < 50 K The hole mobility is estimated as: µ = 0.01µ (5.49) h The static relative permittivity of HgCdTe as a function of x-value is given by [66]: e 2 ε = (5.50) s x x 5.8 Data Fitting and Analysis The dark current models described thus far have been presented as current density expressions. However, to compare the model to experimental data, the total diode current needs to be determined. The total diode dark current is obtained by integrating each of the individual dark current density components over the junction area. While this is trivial for the 1-D model of the diode, the 3-D nature of the actual device under study requires modification of the dark current density expressions to accommodate the contrasting properties of the junction within the various regions of the device: in particular, the differing properties between the bulk region compared to the surface. In order to account for the current generated in the bulk region of the diode, the current density expressions derived above need to be integrated over the entire junction area, which was achieved by assuming that the plasma processing conditions typeconverted the HgCdTe to a depth of approximately 3 µm and a lateral extent of 1 µm. These values are based on work previously undertaken at UWA [15]. The total junction area for circular junction devices, A (µm 2 ), is then given by Eqn. 5.51, where r is the 140

153 Chapter 5 Dark Current Modelling photolithographically defined radius of the HgCdTe surface exposed during the p-to-n typeconversion process: A r r 2 = π( + 1) + 2 π( + 1) 3 (5.51) Assuming that the properties of the junction are uniform within the bulk regions of the diode, the total dark current is given by: ( diff g r btb tat ) I = J + J + J + J A (5.52) Equation 5.52 accounts for the dark current generated in the bulk region of the device, however, the surface dark current contributions detailed previously cannot be included in the same manner. The current generated at the surface or, to be more precise, the small region at and close to where the p-n junction meets the semiconductor surface, are likely to be significant for LWIR photodiodes, since even a small departure from ideal surface passivation conditions will cause sufficient band-bending to enhance the tunnelling current at the surface because of the narrow bandgap. It is generally difficult to determine the appropriate junction area over which to integrate the current density expressions, and the depletion width will also change with the distance away from the surface. One method of quantifying the surface dark current component is to consider any measured dark current in excess of that calculated from Eqn to have originated from the surface. Rather than comparing the results from the dark current modelling to the experimentally obtained data through the I-V characteristics, it is more useful to compare the R-V characteristic (R versus voltage or RA versus voltage). Expressions for dynamic resistance can be obtained by differentiating the expressions for current density, as in Eqns and Each of the individual dark current mechanisms conduct in parallel, and the total dark current can be obtained by summing the individual components. Accordingly, the diode dynamic resistance can be obtained by calculating the resulting resistance from the dynamic resistance of the various components connected in parallel. That is, = (5.53) R R R R R d diff g r btb tat 141

154 Chapter 5 Dark Current Modelling 10 7 Experimental Dynamic Resistance (Ω) Model - Total Diffusion TA BTB G-R Diode Bias (V) Fig.5.8 An example of fitting the dark current model to experimental dynamic resistance data at 80 K. The effect of diode series resistance must also be considered when comparing the model to the measured data. It is more convenient to account for the effect of series resistance in the experimental data as has been described in Chapter 4, rather than to include it in the expressions for current or dynamic resistance. Figure 5.8 shows an example of the modelling results, including the individual components, total, and experimental data, with the data adjusted to remove the effect of series resistance using the procedure described in Chapter 4. To obtain a fit to the experimental data such as in Fig. 5.8, available material parameters, such as nominal values for N A, µ h and x-value provided by the HgCdTe grower, are substituted into the model. Parameters such as N D, µ e and junction depth were obtained from the differential Hall and magnetic field dependant carrier transport studies detailed previously in Chapter 3. For other unknown parameters, an initial estimate is obtained from generalised empirical relations such as Eqns to Using the accumulated parameter values, the expressions for the R-V characteristics are evaluated and compared to the experimental data. By varying the parameter values and evaluating how closely the model fits to the experimental data, the parameter values are successively refined until there is good agreement between the model and the experimental data. Generally, the final parameter values are within their expected range. 142

155 Chapter 5 Dark Current Modelling Figure 5.8 shows an example of the dark current model being fitted to the experimental data. It covers an extended voltage range in the reverse bias in order to show the influence of the band-to-band tunnelling component. Usually the I-V data is only measured from 0.15 V to -0.5 V. In this particular case, the influence of currents induced by surface band-bending was not required to be included to obtain a good fit to the experimental data. Figure 5.8 shows that for large reverse bias band-to-band tunnelling dominates and trap-assisted tunnelling dominates for low reverse bias. Since photodiodes are usually operated at zero bias or slightly reverse biased, it is extremely important to maximise the dynamic resistance in this region. The model shows that three components, diffusion, g-r and trap-assisted tunnelling, are significant in this region. The combined effect of the trap-assisted tunnelling and g-r components acts to reduce the zero-bias RA value by approximately an order of magnitude from the ideal diffusion limited case. 5.9 Analysis of the Temperature Dependence Obtaining a fit of the model to the experimental data with variations in temperature is generally extremely difficult because the temperature dependence of certain parameters such as carrier lifetimes and mobility are usually not known for the material used. These parameters vary widely according to the growth technology used, and even between samples grown by the same technique. A general trend can be distinguished for the different mechanisms if Eqns and 5.49 for mobility are assumed to be accurate, and other parameters are assumed to not vary greatly with temperature. Using these assumptions, and the parameters listed in Table 5.1, the curves in Figs. 5.9 to 5.12 were generated to illustrate the likely temperature dependence of the various dark current mechanisms. Figure 5.9 shows that the diffusion component of dynamic resistance decreases with increasing temperature, and that the rate of increase with increasing reverse bias also decreases with temperature. The same situation occurs for the small bias regime of the g-r component, as shown in Fig The temperature dependence of R 0 A for both diffusion and g-r current is 143

156 Chapter 5 Dark Current Modelling RA (Ωcm 2 ) K 60 K 70 K 80 K 90 K 100 K 110 K 120 K Diode bias (V) R 0 A (Ωcm 2 ) /T (K -1 ) Fig. 5.9 The R-V characteristic of diffusion current for a p-n junction at various temperatures, and R 0 A versus 1000/T. Refer to Table 5.1 for other parameter values RA (Ωcm 2 ) K 60 K 70 K 80 K 90 K 100 K 110 K 120 K R 0 A (Ωcm 2 ) Diode bias (V) /T (K -1 ) Fig.5.10 The R-V characteristic of g-r current for a p-n junction at various temperatures, and R 0 A versus 1000/T. Refer to Table 5.1 for other parameter values. dominated by the temperature dependence of n i, and Eqn shows that the diffusion current is proportional to n 2 i while Eqn shows that g-r current is proportional to n i. The dynamic resistance at large reverse bias for the g-r component also decreases with increasing temperature, but is almost independent of bias voltage. The temperature dependence for the band-to-band and trap-assisted tunnelling components are illustrated in Fig and 5.12, respectively. In comparison with band-to-band tunnelling, the trap-assisted tunnelling component does not have a large variation for changes in 144

157 Chapter 5 Dark Current Modelling RA (Ωcm 2 ) K 60 K 70 K 80 K 90 K 100 K 110 K 120 K R 0 A (Ωcm 2 ) Diode bias (V) /T (K -1 ) Fig The R-V characteristic of band to band tunnelling current for a p-n junction at various temperatures, and R 0 A versus 1000/T. Refer to Table 5.1 for other parameter values. RA (Ωcm 2 ) K K 70 K 80 K 90 K 100 K 110 K 120 K R 0 A (Ωcm 2 ) Diode bias (V) /T (K -1 ) Fig The R-V characteristic of trap assisted tunnelling current for a p-n junction at various temperatures, and R 0 A versus 1000/T. Refer to Table 5.1 for other parameter values. temperature. Another noticeable difference is the increase in dynamic resistance with increasing temperature for trap-assisted tunnelling. The dynamic resistance at zero bias for band-to-band tunnelling, unlike those for diffusion and g-r, increases with increasing temperature. In many cases reported in the literature, analysis of the temperature dependence of the dark current mechanisms usually involves plotting the R 0 A values against inverse temperature and fitting one or two straight lines to the data. An example is given in Fig where one line approximates the diffusion limit (proportional to n -2 i ) and the other approximates the g-r limit (proportional to n -1 i ). The plot allows the departure from the diffusion limited case to be distinguished. This approach is limited because it does not take into account the other dark current mechanisms, and is useful only in identifying g-r as the other limiting mechanism. 145

158 Chapter 5 Dark Current Modelling R 0 A (Ωcm 2 ) Experimental Diffusion G-R /T (K -1 ) Fig Fitting of the diffusion and g-r dark current dependencies to experimental temperature dependent data for a TN7 device R 0 (Ω) Experimental Model - Total Diffusion TA tunnelling G-R Temperature (K) Fig.5.14 The results of fitting the dark current model to the experimental temperature dependent zero-bias dynamic resistance, R 0, data for a TN7 device. 146

159 Chapter 5 Dark Current Modelling Using the dark current model developed here, a more complete understanding of the characteristics of the device can be obtained and the level of confidence in the fit being accurate can be evaluated visually when the results are plotted. If a high level of confidence can be achieved in a fit then the device parameters and useful information can be extracted from the model. Figure 5.14 is an example of the fit of the model to the temperature dependent R 0 data. Taking into consideration the variations in the predicted temperature dependence of the parameters, a good fit is obtained for temperatures greater than 90 K and below 50 K. In the region 60 K to 80 K there is a noticeable divergence of the model from the experimental data. Whether this is due to incorrectly estimating the temperature dependence of parameters such as mobility, carrier lifetimes, n i, etc., or due to the effect of surface dark currents cannot be determined from Fig, However, fitting of the R-V characteristic at these temperatures tends to suggest that it is a surface induced effect Chapter Summary and Conclusions This chapter has presented the analytical photodiode dark current model used to analyse the experimental I-V/R-V data in this thesis. The photodiode dark current components are important because they ultimately determine the performance of the device. The dark current generation mechanisms considered are diffusion, generation and recombination (g-r) in the depletion region, trap-assisted tunnelling, and band-to-band tunnelling. Although experimental data can only measure the total current, the unique junction bias voltage and temperature dependence of the various components may allow identification of the contribution from each component through fitting of the model to the data. Theoretically it should be possible to extract the contribution of the various components using only variable temperature data or only variable junction bias data, but in practice it is more useful and accurate to use variable junction bias data because the temperature dependence of material parameters are not accurately known and are likely to differ between samples. 147

160 Chapter 5 Dark Current Modelling The planar structure of the fabricated devices also needs special consideration because the junction is terminated at the surface of the HgCdTe. Since the surface region may be modified by factors such as band-bending, a distinction needs to be made between dark current generation in the bulk and dark current generation at the surface. 148

161 6 Surface Effects on HgCdTe Photodiodes Chapter 6 Surface Effects on LWIR HgCdTe Photodiodes The results presented in previous chapters have given strong indications that the performance of fabricated HgCdTe LWIR photodiodes is limited by surface effects. To further investigate the influence of the semiconductor surface on device characteristics, and to assess the effectiveness of the thermally deposited CdTe surface passivation technology employed in the passivation process, gated photodiode structures were fabricated and characterised. The gated diode structure is extremely useful for this purpose because it enables the semiconductor surface potential to be varied, allowing the characteristics of surface leakage currents and their impact on device performance to be evaluated. An excellent description of gated diodes and related theory is given in Ref. [18]. A gated diode is effectively a p-n junction diode in which the electrical conditions at the surface can be modified by applying a voltage to the gate contact, which is dielectrically isolated from the underlying diode but is electrostatically coupled to the semiconductor surface. Ideally, under thermal equilibrium conditions, flatband conditions should prevail and the energy bands at the semiconductor surface are the same as in the bulk such that the junction is characterised by the built-in voltage, V bi. When a voltage is applied to the gate, or when there is charge trapped within the passivation layer, charge carriers will either be attracted to or repelled from the semiconductor surface, depending on the polarity of the applied bias and/or the trapped charge. The end result is that the surface is shifted away from flatband, which can give rise to either accumulation, depletion or inversion conditions at the semiconductor surface. These variations in surface conditions can have a profound effect on p-n junction characteristics. 149

162 Chapter 6 Surface Effects on HgCdTe Photodiodes Fig. 6.1: Cross-sectional view of the fabricated gated photodiode with the device being circular in shape (junction diameter = 410µm) and the gate fully overlapping the junction at the surface. 6.1 Fabrication and Characterisation of Gated Photodiodes The gated LWIR HgCdTe photodiodes presented in this chapter were fabricated as part of device lot TN15, in which the ZnS layer provided the gate isolation and the semiconductor surface was passivated by thermally-evaporated CdTe. The resulting device structure is shown in Fig. 6.1, with the completed devices having circular junction areas of diameter 410µm, defined by a photomask. The fabricated devices were characterised by measuring the dark current-voltage (I-V) characteristic of the photodiodes as a function of both temperature and gate bias. The measurement technique and setup was the same as that used for the standard photodiodes, which was detailed in Chapter 5. The HP4156A semiconductor parameter analyser allowed the gate voltage and the diode bias to be set, and the gate leakage current and p-n junction current to be 150

163 Chapter 6 Surface Effects on HgCdTe Photodiodes measured simultaneously. The gate voltage and the diode bias voltage were both referenced to the p-type region of the diode. The temperature during the measurements was varied from 80 K to 160 K, and the gate bias ranged from 12 V to -12 V. 6.2 Analysis of Results The dark I-V and dynamic resistance-voltage (R-V) characteristics obtained at various gate voltages are shown in Fig It is apparent that there is a substantial variation in reverse bias I-V characteristics for the different values of gate bias, whereas the gate bias has little effect on the characteristics when the junction is forward biased. Note that in forward bias, the junction current is dominated by diffusion and depletion region generation-recombination (g-r) current, with diffusion current becoming increasingly dominant with increasing forward bias. The constant slope of the R-V characteristic in forward bias on a log-linear scale is characteristic of the diffusion current component, and the fact that it is independent of gate voltage indicates that the diffusion current is a bulk effect. For the R-V characteristic at 0V gate bias, the rapid decrease in dynamic resistance in the reverse bias regime is indicative of junction breakdown, most likely due to tunnelling. I-V measurements were also taken at 90 K with gate voltage ranging from 10 to -10 V. The R-V characteristics for positive gate voltage are plotted in Fig. 6.3, which shows the tunnelling dark current component increasing further with increasing positive gate voltage, and eventually saturating for gate voltages greater than approximately 6 V. For increasing negative gate voltage, the junction breakdown/tunnelling dark current component decreases accordingly, corresponding to an increase in the dynamic resistance (see Fig. 6.2). It can also be observed that in the diode bias range of -50 to -100 mv, there is a transition from a steeply decreasing to a gradually decreasing dynamic resistance. Whereas the steeper region close to zero diode junction bias can be fitted to a tunnelling current mechanism, the shallower region occurring at higher reverse bias cannot. Possible explanations for this behaviour will be detailed later in this chapter. The final significant point that can be taken from Fig. 6.2 is that the peak value of the 151

164 Chapter 6 Surface Effects on HgCdTe Photodiodes Magnitude of Diode Current (A) (a) -4V -2V 0V2V -6V -8V V g = -10V (b) 10 5 Dynamic Resistance (Ω) V g = -11.5V -10V -8V -6V -4V -2V 0V2V Diode Junction Bias (V) Fig. 6.2: (a) Photodiode dark I-V characteristics with gate voltage as a parameter and (b) the corresponding R-V characteristic. Measurements were conducted at 80K and the p-region is used as the reference for the gate voltage. 152

165 Chapter 6 Surface Effects on HgCdTe Photodiodes 10 5 Diode Dynamic Resistance (Ω) V g = 0 V 1 V 2 V 3 V 4 V 5 V 6 V 7 V 8 V 9 V V g = 10 V Diode Junction Bias (V) Fig. 6.3: Dynamic resistance-voltage (R-V) characteristics for various positive gate bias voltages. Measurements were conducted at 90K and the p-region is the reference for the gate voltage. dynamic resistance initially increases as the gate voltage is decreased from 2 to -6 V, and then decreases with further decreases in gate voltage. This observation will also be elaborated upon later in this chapter. The plot of diode dark current versus gate voltage for various values of diode junction bias is shown in Fig The first point to note is the strong dependence of the diode dark current on the applied gate voltage, where the current varies by over two orders of magnitude in response to an applied gate voltage of about 6 to 8 V. Such a strong dependence is a clear indication of the dominance of surface-related dark current components in determining the diode performance. It can be seen that for the -10 mv diode bias case, the minimum dark current occurs at a gate voltage of approximately -6 V. According to standard gated diode theory [18], this value of gate voltage should also correspond to the semiconductor surface flatband voltage. For curves at higher diode reverse biases, the minimum current level occurs at progressively more negative gate voltages. Another important point to note from Fig. 6.4 is that 153

166 Chapter 6 Surface Effects on HgCdTe Photodiodes n-surface depleted n-surface neutral n-surface accumulated n-surface strongly accumulated 10-3 Magnitude of Diode Dark Current (A) Diode Junction Bias -200 mv -50 mv -100 mv -10 mv Gate Voltage (V) Fig. 6.4: Photodiode dark current versus gate voltage with diode junction bias voltage as a parameter. The state of the surface over the n-type region is indicated for the various gate bias conditions. the rate of increase in diode current is greater for gate voltages more positive than the flatband voltage compared to values more negative than the flatband voltage. The characteristics of the gated diode I-V/R-V dependence on gate voltage described above can be explained by referring to the device cross-sections depicted in Fig The effect of applying a gate bias voltage is to modify the surface potential of the HgCdTe. Any particular value of surface potential, besides flatband, is associated with some degree of band-bending at the surface. Previous studies presented in Chapter 3 have shown that the RIE junction formation process results in an n-type region with doping density of approximately cm -3 when formed on gold doped p-type LWIR HgCdTe with doping density of approximately 154

167 Chapter 6 Surface Effects on HgCdTe Photodiodes cm -3. The lower doping density of the n-type region and the large difference in doping densities between the n- and p-type regions means that the n-type region is most susceptible to trapped charge and gate-induced surface band-bending. Figure 6.5(a) represents the case for when zero gate voltage is applied, assuming that there exists a positive fixed charge within the ZnS/CdTe passivation layer. Due to the higher doping density of the p-type region, the amount of band-bending will be less in comparison to the n-type side. The experimentally observed negative flatband voltage (approximately -6 to -8 V) indicates that the passivation layer and/or interface contains a high density of positive fixed charge, and that there is significant bandbending at the surface at zero gate bias, as shown in Fig. 6.5(a). The surface band-bending is such that it accumulates the lightly-doped n-region, resulting in narrowing of the depletion width near the surface and, correspondingly, increasing the electric field across the depletion region and resulting in enhanced tunnelling dark current. Applying a positive gate bias voltage (see Fig. 6.5(b)) increases the band-bending in the n-type region further, resulting in greater tunnelling and the observed large increase in dark current (see Fig. 6.4). The saturation of the tunnelling current for gate biases greater than 6 V (see Fig. 6.3) is consistent with the edge of the depletion region reaching the p-type region as shown in Fig. 6.5(b). As noted above, the p-region is more heavily doped than the n-type region. As a result, the degree of band-bending induced by the applied gate voltage in the p-type region is expected to be much reduced compared to that of the n-type region. For negative gate biases the junction depletion width at the surface increases, leading to a decrease in the surface electric field across the junction and a dramatic reduction in the tunnelling current in comparison to that at zero gate bias (see Fig. 6.4). This reduction will continue until flatband conditions are reached (see Fig. 6.4 and Fig. 6.5(c)), and the tunnelling current at the surface is no longer enhanced compared to the bulk. The widening of the depletion region with more negative gate bias beyond flatband (see Fig. 6.5(d)) increases the g-r current as the depletion region volume expands to include more fast surface states and bulk generation-recombination (g-r) centres. Hence, for negative gate bias voltages beyond the 155

168 Chapter 6 Surface Effects on HgCdTe Photodiodes ZnS/CdTe Passivation ZnS/CdTe Passivation - V d Gate V g =0 V -V d Gate V g > 0 V Metallurgical Junction n ( lightly doped ) ( lightly doped ) Depletion Region p Metallurgical Junction n Depletion Region p (a) (b) ZnS/CdTe Passivation ZnS/CdTe Passivation - V d Gate V g =V fb - V d Gate V g < V fb Metallurgical Junction n ( lightly doped ) ( lightly doped ) Depletion Region p Metallurgical Junction n Depletion Region p (c) (d) Fig. 6.5: The effect of surface band-bending on an n(lightly doped)-on-p junction in the presence of positive fixed charge in the passivation layer: (a) with 0V applied gate bias (n-surface accumulated), (b) with positive gate bias (n-surface strongly accumulated), (c) with gate bias to give flatband conditions at the semiconductor surface (n-surface neutral), and (d) with gate negatively biased beyond flatband (nsurface depleted). flatband voltage, the observed gradual increase in current with more negative gate voltage is due to an increase in the surface g-r current component (see Fig. 6.4). According to standard gated diode theory [18], the g-r dark current component should increase with increasing negative gate bias past flatband as the n-type surface becomes increasingly depleted. If the gate is negatively biased further the n-type surface should eventually become inverted, whereupon the g-r dark current component should remain constant or decrease slightly because the depletion region no longer increases appreciably with decreasing gate bias. The slight decrease results because the 156

169 Chapter 6 Surface Effects on HgCdTe Photodiodes depletion region is accompanied by an inverted surface which tends to quench g-r current arising from the high concentration of surface g-r centres. This decrease in current at high negative gate bias was not observed in the experimental data over the applied gate bias range, as evident in Fig Analysis Using Dark Current Models The dependence of the diode dark current on gate bias voltage has been qualitatively explained in terms of surface band-bending and the resultant effect on both the tunnelling and g-r current components. This qualitative explanation needs to be supported by dark current modelling of the measured I-V and R-V characteristics. The total diode dark current is obtained by integrating each of the individual dark current density components over the junction area. While this is trivial for the 1-D model of the diode, the 3-D nature of the actual device under study requires modification of the dark current density expressions to accommodate the contrasting properties of the junction within the various regions of the device: in particular, the differing properties between the bulk region compared to the surface. In order to account for the current generated in the bulk region of the diode, the current density expressions derived in Chapter 5 need to be integrated over the entire junction area, A. As described in Chapter 5, this was achieved by assuming that the plasma processing conditions used in this study type-converted the HgCdTe to a depth of 3 µm and a lateral extent of 1 µm beyond the masked dimension, giving an approximate area of: A r r 2 π( + 1) + 2 π( + 1) 3 (6.1) for a circular masking region of radius r. Assuming that the properties of the junction are uniform within the bulk regions of the diode, the total dark current is given by: ( diff g r btb tat ) I = J + J + J + J A (6.2) Any measured dark current in excess of that calculated from Eqn. 6.2 can be considered as having originated from the surface or, to be more precise, the small region at and close to where the p-n junction meets the semiconductor surface. 157

170 Chapter 6 Surface Effects on HgCdTe Photodiodes To more accurately account for the dark current contribution from the surface region, the expressions for the various current components require modification. Referring back to Fig. 6.5 as a guide, the g-r current component will vary with surface potential because the depletion region volume varies with surface potential and, furthermore, the depletion region intersection area at the surface also varies to either include or exclude fast interface states. The expression for g-r current density given in Eqn. 6.2 applies to the bulk regions only, and does not include the g-r dark current arising from the fast interface states. The effect of the additional g-r dark current arising from the surface region is accounted for by adjusting the magnitude of the g-r current obtained when considering only contributions from the bulk. That is, the total g-r dark current component becomes: ( ) I = α J A (6.3) g r g r g r Similarly, the trap-assisted tunnelling current component will also vary with changes in the depletion region volume, which can be included in the expression for the trap-assisted tunnelling dark current in a similar manner: ( ) I = α J A (6.4) tat tat tat The multiplication factors, α tat and α g-r, arise due to modulation of the surface band-bending by the applied gate voltage and/or insulator charge. These factors arise as a direct result of the surface potential, hence they should be a function of gate bias and temperature. The diode bias voltage may also be important because, depending on how it is applied, either the potential difference between the n-type region or the p-type region will also vary. For measurements conducted in this thesis the p-type region was referenced as ground and the gate bias voltage was referenced to ground. As a result, the applied diode bias voltage also modulates the potential difference between the gate and the n-type region below. The precise dependence of α g-r and α tat on gate bias, diode bias and temperature is unknown, and for this work they are approximated to a constant at each gate voltage and the value is determined by fitting the model to the experimental data. 158

171 Chapter 6 Surface Effects on HgCdTe Photodiodes All tunnelling current mechanisms depend strongly on the electric field in the depletion region, and it is well-recognised that surface band-bending modifies the electric field distribution by changing the depletion width (see Fig. 6.5). This surface effect is accounted for by modification of the expression for electric field used to calculate the current density expressions of the two tunnelling current mechanisms: band-to-band and trap-assisted tunnelling. The expression for the electric field in the bulk depletion region is given by: qn AND( Vbi Vd) E = (6.5) 2 εε( N + N ) S 0 A D The effect of the surface band-bending on electric field is more pronounced closest to the surface, since the depletion width is narrowest at the surface. However, the effective electric field influencing band-to-band tunnelling can be modelled by Eqn. 6.6, where β btb represents the electric field enhancement factor due to surface band-bending for band-to-band tunnelling. For the same reasons as with α tat and α g-r, β btb will be a function of gate bias and temperature, but as a first order approximation, it is independent of diode bias. That is, surface band-bending results in an effective electric field that is different only in magnitude to the field expected in the absence of band-bending. E E (6.6) btb = βbtb Similarly, the effective electric field for trap-assisted tunnelling is given by Eqn. 6.7, where β tat is the field-enhancement factor which is constant with diode bias but may depend on temperature and gate bias. E E (6.7) tat = βtat Figures 6.6, 6.7 and 6.8 show the experimentally determined R-V characteristic, along with the dark current modelling results for applied gate voltages of 0 V, -6.5 V and V, respectively. A summary of the model parameters for these three cases is presented in Tables 6.1 and 6.2. Table 6.1 contains the modelling parameters which remained fixed when fitting to experimental data at various gate biases, and Table 6.2 contains only the modelling parameters that need to be varied in order to obtain the fits to the experimental data for the cases shown in 159

172 Chapter 6 Surface Effects on HgCdTe Photodiodes Table 6.1: The modelling parameters which were kept fixed when modelling the diode dark current characteristics at various gate bias voltages. (*) indicate values specified on material datasheets. Modelling Parameter Value x N A (cm -3 ) (*) N D (cm -3 ) N t (cm -3 ) µ e (cm 2 V -1 s -1 ) µ h (cm 2 V -1 s -1 ) 540 (*) τ e (µs) 1.6 τ h (µs) 0.1 τ 0 (µs) 0.3 E t 0.7 E g Figs. 6.6, 6.7 and 6.8. The parameters which needed to be varied for the various gate biasing conditions are the multiplication factors α tat and α g-r for trap-assisted tunnelling and g-r dark current, respectively, and the electric field enhancement factors β tat and β btb, for trap-assisted tunnelling and band-to-band tunnelling, respectively. All other parameters remained constant for fitting to the data of Figs. 6.6, 6.7 and 6.8. A value of 1 for the parameters listed in Table 6.2 corresponds to the respective dark current component or electric field being of the same value as would be expected for the device in the absence of surface effects: that is, at flatband. It is worth noting that the agreement between experimental and modelled results is quite good, especially for the V g = 0 V and V g = V cases in Figs. 6.6 and 6.8, respectively. A good fit is also obtained in Fig. 6.7 for diode bias voltages more positive than -50 mv. Consistent with the reasoning presented earlier, Fig. 6.6 indicates that at zero gate bias the diode R-V characteristic can be modelled by increased band-to-band tunnelling dark current 160

173 Chapter 6 Surface Effects on HgCdTe Photodiodes Table 6.2: Summary of the modelling results of Figures 6.6, 6.7 and 6.8 showing the relative changes in modelling parameters. Gate Bias Conditions Modelling parameter V g = 0V V g = -6.5 V V g = V α g-r α tat β tat β btb resulting from an increase in the effective electric field. It is evident that band-to-band tunnelling dominates in reverse bias and partially into the forward bias regime. Since the total dark current is strongly dominated by band-to-band tunnelling in reverse bias, the precise magnitude of the trap-assisted tunnelling current cannot be accurately determined. In the forward bias regime the dynamic resistance is limited by a combination of g-r and diffusion current. The value used for the electric field is different for the two tunnelling mechanisms modelled because the region (surface or bulk) where the current is generated may be different. The lower magnitude of electric field used to obtain the fit for trap-assisted tunnelling (β tat < β btb, see Table 6.2) indicates that in this case trap-assisted tunnelling is not as important at the surface compared to band-to-band tunnelling. Also significant is the relatively large magnitude of total g-r dark current compared to g-r dark current originating from the bulk (α g-r = 8). This is a strong indication that fast interface states are the major source of generationrecombination centres for the g-r dark current component. The results presented in Fig. 6.7 (V g = -6.5 V) indicate that the dominance of the bandto-band tunnelling component at the surface is reduced since all four dark current mechanisms that were modelled were found to be significant in limiting the dynamic resistance for diode bias in the range of 50 to -50 mv. The fit between calculated and experimental results was achieved by increasing the magnitude of the trap-assisted tunnelling current (α tat = 1.25) and 161

174 Chapter 6 Surface Effects on HgCdTe Photodiodes decreasing the magnitude of the electric field affecting band-to-band tunnelling (α btb = 1). This was based on the reasoning that at V g = -6.5 V, the surface band-bending is almost non-existent (that is, it is approximately at flatband; see Fig. 6.4) in comparison to V g = 0 V, which has the effect of reducing the electric field at the surface and slightly increasing the depletion volume at the surface. Another significant point to be noted from Fig. 6.7 is that the dark current model cannot be made to fit the data for the whole of the reverse bias region. For diode bias more negative than -50 mv, the rate of decrease in the measured dynamic resistance is less than that expected from the dark current model, and is an indication that the assumption that α g-r, α tat, β tat and β btb are constant for a given gate voltage is not valid for diode bias in this range. The explanation for this disagreement may lie with the application of the diode reverse bias voltage to the n-region, as indicated in Fig. 6.5, thus modifying the surface band-bending. That is, for a given gate bias voltage, the surface band-bending can also be modulated by the diode junction bias. For increasing reverse junction bias (-V d is applied to the n-region) the surface over the n- region becomes increasingly more depleted, and the tunnelling dark current is reduced as a consequence. The observed higher dynamic resistance in the experimental data compared to the theoretical results, which were calculated without consideration for changing surface bandbending with diode bias, is consistent with this explanation. Both the experimental and fitted results for V g = V shown in Fig. 6.8 indicate that band-to-band tunnelling is no longer significant around zero bias. Instead, the g-r and trapassisted tunnelling current components are the dominant mechanisms, as reflected by the fitting parameters given in Table 6.2. Once again, a departure of the experimental results to higher values of dynamic resistance is observed in comparison to the modelled results for increasing applied reverse junction bias. 162

175 Chapter 6 Surface Effects on HgCdTe Photodiodes Diode Dynamic Resistance (Ω) 10 5 l 10 4 Gate Voltage: 0 V Experimental Model - Total 10 3 Diffusion TA BTB G-R Diode Junction Bias (V) Fig. 6.6: Experimental and modelled diode dynamic resistance results for the gated diode at a temperature of 80 K and 0 V gate bias. Diode Dynamic Resistance (Ω) Gate Voltage: -6.5 V 10 5 Experimental Model - Total Diffusion TA 10 4 BTB G-R Diode Junction Bias (V) Fig. 6.7: Experimental and modelled diode dynamic resistance results for the gated diode at a temperature of 80 K and -6.5 V Gate bias. Diode Dynamic Resistance (Ω) Gate Voltage: V 10 5 Experimental Model - Total Diffusion TA 10 4 BTB G-R Diode Junction Bias (V) Fig. 6.8: Experimental and modelled diode dynamic resistance results for the gated diode at a temperature of 80 K and V Gate bias. 163

176 Chapter 6 Surface Effects on HgCdTe Photodiodes 6.4 Temperature dependence The results presented for measurements at 80 K have shown that modifying the surface potential by varying the gate voltage can significantly change the dark current characteristics. Variable temperature measurements were also undertaken, and the results are presented in Figs. 6.9, 6.10 and 6.11, showing the effect of both temperature and gate bias for diode bias voltages of 0 V, -10 mv and -50 mv, respectively. For the variable temperature, variable gate voltage dynamic resistance plots, a constant value for dynamic resistance parallel to the V g axis would indicate that the dominant dark current component determining the dynamic resistance at that particular temperature originates in the bulk regions of the device. This is the case at high temperatures, T > 120K, for all three cases shown. Also included in Figs. 6.9, 6.10 and 6.11 is the expected temperature dependence of dynamic resistance due to the diffusion dark current component, R diff, according to the modelling presented previously. The dynamic resistance at high temperatures in Figs. 6.9 and 6.10 can be suitably accounted for by the diffusion dark current component from the bulk regions of the device. However, at higher diode reverse bias (see Fig. 6.11), the dynamic resistance at high temperature indicates that the dynamic resistance values are approximately constant with gate bias voltage, and that the diffusion dark current component alone underestimates the total dark current. The additional dark current components which must be included to account for the total dark current measured at high temperatures must also originate from the bulk region, and are most likely to originate from g-r and trap-assisted tunnelling current. In the low temperature regime, substantial deviations are observed from the diffusion current component arising from the bulk. These deviations are largely due to the effect of surface band-bending which is easily recognised by a variation of the dynamic resistance with gate bias voltage. In general, the effect of temperature and surface potential on the resultant dynamic resistance is complicated, and is most evident in Fig However, it can be said that, in general, the surface band-bending is detrimental to the device, resulting in a greatly 164

177 Chapter 6 Surface Effects on HgCdTe Photodiodes Diode Bias: 0 mv 10 5 R diff Dynamic Resistance (Ω) /T (K -1 ) Gate Bias (V) Fig. 6.9: Dynamic resistance at 0 V diode junction bias as a function of temperature and gate bias. The theoretical temperature dependence of the dynamic resistance for the diffusion dark current component (R diff ) is also shown. reduced dynamic resistance and increased dark current. It should also be noted that flatband conditions ( V 6 V ) results in the highest dynamic resistance values when the diode bias is g close to 0 V. At gate bias voltages more positive than the flatband voltage, the decrease in dynamic resistance is more dramatic in comparison to the situation for gate bias voltages more negative than the flatband voltage. This can be correlated with modelling results presented earlier, which indicate that tunnelling dark currents become increasingly dominant for more positive gate voltages, and g-r dark currents become increasingly dominant for more negative gate bias. 165

178 Chapter 6 Surface Effects on HgCdTe Photodiodes Diode Bias: -10 mv Rdiff 10 5 Dynamic Resistance (Ω) /T (K -1 ) Gate Bias (V) Fig. 6.10: Dynamic resistance at -10 mv diode junction bias as a function of temperature and gate bias. The theoretical temperature dependence of the dynamic resistance for the diffusion dark current component (R diff ) is also shown. Diode Bias: -50 mv R diff 10 5 Dynamic Resistance (Ω) /T (K -1 ) Gate Bias (V) Fig. 6.11: Dynamic resistance at -50 mv diode junction bias as a function of temperature and gate bias. The theoretical temperature dependence of the dynamic resistance for the diffusion dark current component (R diff ) is also shown. 166

179 Chapter 6 Surface Effects on HgCdTe Photodiodes 6.5 Vacuum Bake Stability of Photodiodes Following the initial characterisation of the dark I-V characteristics as a function of varying junction bias, varying gate bias, and temperature, the gated photodiodes were subjected to an 80 C vacuum bake for three hours. The I-V/R-V characterisation process was then repeated. Figures 6.12 and 6.13, respectively, show the R-V characteristics versus gate voltage before and after the baking process. There are several differences between the two figures, the most significant being the increasing dynamic resistance peak with increasing reverse gate voltage observed in the pre-baked data of Fig. 6.12, which is not observed in the data after the vacuum baking process shown in Fig In the latter case, the maximum dynamic resistance plateaus at approximately 10 kω for the vacuum baked devices. Examining the dark I-V curves more closely, there is also an indication that the contribution from the surface band-to-band tunnelling current is significantly lower for the device after vacuum baking. Modelling of the dark R-V characteristic at the three gate bias voltages examined previously (0 V, -6.5 V and V) was performed for the devices after baking. These modelling results are plotted in Figs. 6.14, 6.15 and 6.16, with the corresponding experimental R-V data for the devices before baking also included. A summary of the modelling parameters for the post-bake data are given in Table 6.3. The values of fixed parameters in Table 6.1 also apply to Figs. 6.14, 6.15, and 6.16 since they and all other parameters not specified in Table 6.3 remained constant when used for device modelling both before and after vacuum baking. The modelling results at 0V gate bias for the vacuum baked device presented in Fig were obtained by considering the diffusion, g-r and tunnelling components in the bulk regions and at the surface, plus an additional surface leakage component represented as a shunt resistance, R shunt, in the R-V model. It was found that the dark current components considered for the device after the vacuum bake process could not be made to closely fit the experimental data by reasonably varying the numerous parameters. With the addition of an additional dark current component due to surface leakage with an Ohm s law I-V characteristic, and a resultant dynamic resistance of R shun t = 14 kω, a close fit can be obtained as can be seen in Fig

180 Chapter 6 Surface Effects on HgCdTe Photodiodes Dynamic Resistance ( Ω) Gate bias (V) Junction bias Fig The R-V characteristic as a function of gate bias for the as-processed gated photodiode at 80 K. Dynamic Resistance ( Ω) Gate bias (V) Junction bias Fig The R-V characteristic as a function of gate bias at 80 K for the gated photodiode after vacuum baking at 80 C. 168