ALLIANCE SEMICONDUCTOR
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1 High Performance 32K 8 CMOS SRM S7C26 32K 8 CMOS SRM (Common I/O) FETURES Organization: 32,768 words 8 bits High speed 0/2///2/3 ns address access time 3/3/4//6/8 ns output enable access time Low power consumption ctive: 660 mw max (0 ns cycle) Standby: mw max, CMOS I/O 2.7 mw max, CMOS I/O, L version Very low DC component in active power 2.0V data retention (L version) Equal access and cycle times Easy memory expansion with and OE inputs TTL-compatible, three-state I/O 28-pin JEDEC standard packages 300 mil PDIP and SOJ Socket compatible with 7C2 and 7C mil SOIC TSOP ESD protection > 00 volts Latch-up current > 0 m LOGIC BLOCK DIGRM PIN RRNGEMENT Vcc ROW DECODER 7 8 SELECTION GUIDE INPUT BUFFER RRY (262,44) COLUMN DECODER SENSE MP CONTROL CIRCUIT S7C26-0 OE I/O7 I/O0 DIP, SOJ, SOIC TSOP OE Vcc I/O0 I/O I/O S7C26 S7C Vcc OE 0 I/O7 I/O6 I/O I/O4 I/O I/O7 I/O6 I/O I/O4 I/O3 I/O2 I/O I/O0 0 S7C C26-0 7C26-2 7C26-7C26-7C26-2 7C26-3 Unit Maximum ddress ccess Time ns Maximum Output Enable ccess Time ns Maximum Operating Current m Maximum CMOS Standby Current m L m LLIN SEMICONDUCTOR
2 FUNCTIONL DESCRIPTION The S7C26 is a high performance CMOS 262,44-bit Static Random ccess Memory (SRM) organized as 32,768 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t, t RC, t WC ) of 0/2///2/3 ns with output enable access times (t OE ) of 3/3/4//6/8 ns are ideal for high performance applications. chip enable () input permits easy memory expansion with multiple-bank memory organizations. When is HIGH the device enters standby mode. The standard S7C26 is guaranteed not to exceed mw power consumption in standby mode; the L version is guaranteed not to exceed 2.7 mw, and typically requires only 00 µw. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 300 µw. write cycle is accomplished by asserting chip enable () and write enable () LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of (write cycle ) or (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (). read cycle is accomplished by asserting chip enable () and output enable (OE) LOW, with write enable () HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. ll chip inputs and outputs are TTL-compatible, and operation is from a single V supply. The S7C26 is packaged in all high volume industry standard packages. BSOLUTE MXIMUM RTINGS Parameter Symbol Min Max Unit Voltage on ny Pin Relative to V t V Power Dissipation P D.0 W Storage Temperature (Plastic) T stg +0 o C Temperature Under Bias T bias 0 +8 o C DC Output Current I out m NOTE: Stresses greater than those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.. TRUTH TBLE OE Data Mode H X X High Z Standby (I SB, I SB ) L H H High Z Output Disable L H L Read L L X D in Write Key: X = Don t Care, L = LOW, H = HIGH 2
3 RECOMMENDED OPERTING CONDITIONS (T a = 0 C to +70 C) Parameter Symbol Min Typ Max Unit Supply Voltage Input Voltage *V IL min = 3.0V for pulse width less than t RC /2. V CC V V V IH 2.2 V CC + V V IL 0.* V DC OPERTING CHRCTERISTICS (V CC = V±0%, = 0V, T a = 0 C to +70 C) Parameter Symbol Test Conditions Input Leakage Current Output Leakage Current Operating Power Supply Current Standby Power Supply Current Output Voltage I LI I LO I CC Min Max Min Max Min Max Min Max Min Max Min Max V CC = Max, V in = to V CC µ = V IH, V CC = Max, V out = to V CC µ = V IL, f = f max, I out = 0 m Unit m L m m I SB = V IH, f = f max L m > V CC 0.2V, f = 0, m I SB V in 0.2V or V in V CC 0.2V L m V OL I OL = 8 m, V CC = Min V V OH I OH = 4 m, V CC = Min V 2 CPCITN (f = MHz, T a = Room Temperature, V CC = V) Parameter Symbol Signals Test Conditions Max Unit Input Capacitance C IN,,, OE V in = 0V pf I/O Capacitance C I/O I/O V in = V out = 0V 7 pf 3
4 3, 9 RED CYCLE (V CC = V±0%, = 0V, T a = 0 C to +70 C) Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time t RC ns ddress ccess Time t ns 3 Chip Enable () ccess Time t ns 3 Output Enable (OE) ccess Time t OE ns Output Hold from ddress Change t OH ns LOW to Output in Low Z t CLZ ns 4, HIGH to Output in High Z t CHZ ns 4, OE LOW to Output in Low Z t OLZ ns 4, OE HIGH to Output in High Z t OHZ ns 4, Power Up Time t PU ns 4, Power Down Time t PD ns 4, 3, 6, 7, 9 TIMING WVEFORM OF RED CYCLE (ddress Controlled) t RC ddress t t OH Data Valid 3, 6, 8, 9 TIMING WVEFORM OF RED CYCLE 2 ( Controlled) t RC t OE OE t OLZ t OHZ t t CHZ Data Valid t CLZ Supply Current t PU t PD I CC I SB 0% 0% S7C
5 WRITE CYCLE (V CC = V±0%, = 0V, T a = 0 C to +70 C) Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time t WC ns Chip Enable to Write End t CW ns ddress Setup to Write End t W ns ddress Setup Time t S ns Write Pulse Width t WP ns ddress Hold From End of Write t H ns Data Valid to Write End t DW ns Data Hold Time t DH ns 4, Write Enable to Output in High Z t WZ ns 4, Output ctive from Write End t OW ns 4, 0, TIMING WVEFORM OF WRITE CYCLE ( Controlled) t WC t W t H ddress t WP t S t DW t DH D in Data Valid t WZ t OW 0, TIMING WVEFORM OF WRITE CYCLE 2 S7C26-0 ( Controlled) t W t WC t H ddress t S t CW t WP t WZ t DW t DH D in Data Valid S7C26-06
6 DT RETENTION CHRCTERISTICS (L Version Only) Parameter Symbol Test Conditions Min Max Unit V CC for Data Retention V DR 2.0 V Data Retention Current I CCDR V CC = 2.0V 0 µ V CC 0.2V Chip Enable to Data Retention Time t CDR 0 ns V in V CC 0.2V or Operation Recovery Time t R t V in 0.2V RC ns Input Leakage Current I LI µ DT RETENTION WVEFORM (L Version Only) Data retention mode V CC 4.V 4.V V DR 2.0V t CDR t R V IH V DR V IH S7C26-07 C TEST CONDITIONS Output load: see Figure B, except for t CLZ and t CHZ see Figure C. Input pulse level: to 3.0V. See Figure. Input rise and fall times: ns. See Figure. Input and output timing reference levels:.v. +3.0V NOTES 90% 0% 90% 0% 2Ω 30 pf* Thevenin Equivalent: 68Ω +.728V 2Ω. During V CC power-up, a pull-up resistor to V CC on is required to meet I SB specification. 2. This parameter is sampled and not 00% tested. 3. For test conditions, see C Test Conditions, Figures, B, C. 4. t CLZ and t CHZ are specified with CL = pf as in Figure C. Transition is measured ±00mV from steady-state voltage.. This parameter is guaranteed but not tested. 6. is HIGH for read cycle. 7. and OE are LOW for read cycle. 8. ddress valid prior to or coincident with transition LOW. 9. ll read cycle timings are referenced from the last valid address to the first transitioning address. 0. or must be HIGH during address transitions.. ll write cycle timings are referenced from the last valid address to the first transitioning address. 480Ω +V 480Ω pf* Figure : Input Waveform Figure B: Output Load Figure C: Output Load for t CLZ, t CHZ S7C26-08 S7C26-09 S7C26-0 +V *including scope and jig capacitance 6
7 TYPICL DC ND C CHRCTERISTICS Normalized supply current I CC, I SB vs. supply voltage V CC.4 Normalized supply current I CC, I SB vs. ambient temperature T a.4 Normalized supply current I SB vs. ambient temperature T a Normalized I CC, I SB I CC I SB Supply voltage (V) Normalized I CC, I SB I CC I SB mbient temperature ( C) Normalized I SB (log scale) mbient temperature ( C). Normalized access time t vs. supply voltage V CC. Normalized access time t vs. ambient temperature T a.4 Normalized supply current I CC vs. cycle frequency /t RC, /t WC Normalized access time T a = 2 C Normalized access time Normalized I CC T a = 2 C Supply voltage (V) mbient temperature ( C) Cycle frequency (MHz) 40 Output source current I OH vs. output voltage V OH 40 Output sink current I OL vs. output voltage V OL 3 Typical access time change t vs. output capacitive loading Output source current (m) T a = 2 C Output sink current (m) T a = 2 C Change in t (ns) V CC = 4.V Output voltage (V) Output voltage (V) Capacitance (pf) S7C26-7
8 ORDERING CODES Package / ccess Time 0 ns 2 ns ns ns 2 ns 3 ns Plastic DIP, 300 mil S7C26-0PC -0PC S7C26-2PC -2PC S7C26-PC -PC S7C26-PC -PC S7C26-2PC -2PC S7C26-3PC -3PC Plastic SOJ, 300 mil S7C26-0JC -0JC S7C26-2JC -2JC S7C26-JC -JC S7C26-JC -JC S7C26-2JC -2JC S7C26-3JC -3JC Plastic SOIC, 330 mil S7C26-0SC -0SC S7C26-2SC -2SC S7C26-SC -SC S7C26-SC -SC S7C26-2SC -2SC S7C26-3SC -3SC TSOP S7C26-0TC -0TC S7C26-2TC -2TC S7C26-TC -TC S7C26-TC -TC S7C26-2TC -2TC S7C26-3TC -3TC PRT NUMBERING SYSTEM S7C 26 X XX X C SRM Prefix Device Number Blank = Standard Power L = Low Power ccess Time Package: P = PDIP 300 mil J = SOJ 300 mil S = SOIC 330 mil T = TSOP 8 4 Commercial Temperature Range, 0 C to 70 C REPRESENTTIVES, DISTRIBUTORS, ND SLES OFFIS DOMESTIC REPS LBM () RIZON Competitive Technology (602) RKNSS Southern States Marketing (24) CLIFORNI North: Brooks Technical (4) L rea: Competitive Tech. (74) San Diego: TS (69) COLORDO Technology Sales (303) CONNECTICUT (3) DELWRE Vantage Sales (609) FLORID Micro-Electronic Comp. Deerfield Beach (30) Tampa (83) GEORGI (404) HWII Brooks Technical (4) IDHO ES/Chase (03) ILLINOIS North: El-Mech (32) South: CenTech (34) INDIN CC Electro Sales (37) KNSS CenTech (86) KENTUCKY CC Electro Sales (37) LOUISIN Southern States Marketing North: (24) South: (73) MINE (67) MRYLND Chesapeake Technology (30) MSSCHUSETTS (67) MICHIGN Enco Group (80) MINNESOT D.. Case ssociates (62) MISSOURI East: CenTech (34) West: CenTech (86) MISSISSIPPI () MONTN ES/Chase (03) NEBRSK CenTech (86) NEVD North: Brooks Technical (4) South: Competitive Tech. (602) NEW HMPSHIRE (67) NEW JERSEY North: ER ssociates (800) South: Vantage Sales (609) NEW MEXICO Competitive Technology (602) NEW YORK NYC: ER ssociates (6) Upstate: Tri-Tech Rochester (76) Birmingham (607) Fishkill (94) NORTH CROLIN (99) NORTH DKOT D.. Case ssociates (62) OHIO Midwest Marketing ssoc. Lyndhurst: (26) Dayton: (3) OKLHOM Southern States Marketing (24) OREGON ES/Chase (03) PENNSYLVNI East: Vantage Sales (609) West: Midwest Marketing (26) RHODE ISLND (67) SOUTH CROLIN (99) SOUTH DKOT D.. Case ssociates (62) TENNESSEE () TEXS Southern States Marketing ustin: (2) Dallas: (24) Houston: (73) UTH Charles Fields & ssoc. (80) VERMONT (67) VIRGINI Chesapeake Technology (30) WSHINGTON ES/Chase (6) ST VIRGINI Chesapeake Technology (30) WISCONSIN D.. Case ssociates (62) WYOMING Technology Sales (303) INTERNTIONL USTRLI NJS Technology Pty Ltd. Mulgrave, Victoria R&D Electronics Dingley, Victoria CND Tech Trek Ltd. Mississauga: (90) Montreal: (4) Ottawa: (63) Vancouver: (604) Calgary: (403) EUROPE Britcomp Sales Surrey, England Munich, Germany thismons, France HONG KONG Eastele Technology INDI Priya Electronics, Inc. San Jose, C US (408) ISREL Eldis Technology JPN ctes Engineering Tokyo Rohm Co. Ltd. Kyoto KORE FM Korea Woo Young Tech MLYSI, SINGPORE Technology Distr. Pte Ltd PUERTO RICO Micro-Electronic Comp. (809) TIWN sian Specific Tech Puteam International DISTRIBUTORS ll-merican Locations Nationwide Headquarters: (30) xis Components Sunnyvale, C (408) xis Components Irvine, C (74) 49-0 Future Electronics Locations Worldwide Headquarters: (4) Interface Electronics Hopkinton, M (800) (08) SLES OFFIS HEDQURTERS lliance Semiconductor San Jose, C (408) NORTHEST RE lliance Semiconductor Boston, M (67) TECHNICL NTER TIWN lliance Semiconductor lliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. lliance Semiconductor cannot assume responsibility for circuits shown or represent that they are free from patent infringement. lliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of lliance. The lliance logo is a trademark of lliance Semiconductor Corporation. ll other trademarks are property of their respective holders. LLIN SEMICONDUCTOR 3099 North First Street San Jose, C 934 (408) Fax (408) Printed in U.S.. Copyright 99 ll rights reserved. May 996
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QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT
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74VHCT138ATTR 3 TO 8 LINE DECODER (INVERTING)
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EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
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DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT HIGH SPEED: t PD = 16ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
The 74LV32 provides a quad 2-input OR function.
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MM74HC154 4-to-16 Line Decoder
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