Second Order Function Approximation Using a Single Multiplication on FPGAs

Size: px
Start display at page:

Download "Second Order Function Approximation Using a Single Multiplication on FPGAs"

Transcription

1 FPL 04 Second Order Function Approximation Using a Single Multiplication on FPGAs Jérémie Detrey Florent de Dinechin Projet Arénaire LIP UMR CNRS ENS Lyon UCB Lyon INRIA CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ECOLE NORMALE SUPERIEURE DE LYON

2 Overview 1 Context The SMSO method Optimization Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 1 / 31

3 Context 2 Context Function evaluation State of the art Objectives The SMSO method Optimization Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 2 / 31

4 Context: function evaluation 3 elementary functions sin(x), cos(x), log(x), e x,... signal or image processing neural networks... special functions: logarithmic number system: log 2 (1 + 2 x ) and log 2 (1 2 x ) log 2 (1 + 2 x ) log 2 (1 2 x ) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 3 / 31

5 Context: function evaluation 4 input: function f : [0; 1[ [0; 1[ input precision w I output precision w O (usually w O = w I ) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 4 / 31

6 Context: function evaluation 4 input: function f : [0; 1[ [0; 1[ input precision w I output precision w O (usually w O = w I ) output: X w I w O f(x) where X =.x 1 x 2 x wi and f(x) = Y =.y 1 y 2 y wo f(x) at the required precision Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 4 / 31

7 Context: function evaluation 4 input: function f : [0; 1[ [0; 1[ input precision w I output precision w O (usually w O = w I ) output: X w I? w O f(x) where X =.x 1 x 2 x wi and f(x) = Y =.y 1 y 2 y wo f(x) at the required precision Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 4 / 31

8 Order 0: direct look-up table 5 X w I f(0) f(1).. f(2 w I 2) f(2 w I 1) w O f(x) very short critical path: only 1 table look-up huge look-up table: w O 2 w I bits Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 5 / 31

9 Order 1: lookup-multiply method 6 Mencer, Boullis, Luk and Styles K 0 (A) w O + g X w I A K 1 (A) w O + g K 1 (A) B w O f(x) B smaller tables longer critical path: 1 table look-up, 1 mult and 1 add Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 6 / 31

10 Order 1: bipartite table method 7 Das Sarma and Matula, generalized by Schulte and Stine TIV(A) w O + g A w O f(x) X w I A 0 TO(A 0, B) w O + g B shorter critical path: 1 table look-up and 1 add slightly larger tables Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 7 / 31

11 Order 1: multipartite table method 8 Schulte and Stine, Muller, de Dinechin and Tisserand: generalization and extension of the idea of the bipartite table method X w I A TIV w O + g A 0 B B 0 A 1 O X R TO 0 O X R w O + g w O f(x) B 1 O X R TO 1 O X R w O + g B 2 A 2 O X R TO 2 O X R w O + g critical path: 2 XOR stages, 1 table look-up and log 2 (n) adds much smaller tables, but adder tree Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 8 / 31

12 Higher order methods 9 Hörner evaluation interleaved memory interpolators: Lewis partial product arrays: Hassler and Takagi specialized squaring unit: Piñero, Bruguera and Muller simplified order 5 Taylor approximation: Defour, de Dinechin and Muller... Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 9 / 31

13 Objectives 10 simplify, generalize and extend Defour s method use ideas from order 1 methods (bipartite and multipartite table) for an order 2 approximation Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 10 / 31

14 Objectives 10 simplify, generalize and extend Defour s method use ideas from order 1 methods (bipartite and multipartite table) for an order 2 approximation maintain short critical path while keeping tables as small as possible use only small multipliers (Virtex-II) accurate error analysis for a fine tuning of the operators Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 10 / 31

15 The SMSO method 11 Context The SMSO method General idea Architecture Optimization Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 11 / 31

16 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

17 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β order 2 approximation on each interval addressed by A: f(x) = K 0 (A) + K 1 (A) 2 α B + K 2 (A) 2 2α B 2 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

18 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β order 2 approximation on each interval addressed by A: f(x) = K 0 (A) + K 1 (A) 2 α B + K 2 (A) 2 2α B 2 }{{} look-up table TIV(A) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

19 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β order 2 approximation on each interval addressed by A: f(x) = K 0 (A) + K 1 (A) 2 α B + K 2 (A) 2 2α B 2 }{{} } {{ } look-up table look-up table TIV(A) TO 2 (A, B) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

20 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β order 2 approximation on each interval addressed by A: f(x) = K 0 (A) + K 1 (A) 2 α B + K 2 (A) 2 2α B 2 }{{}}{{}}{{} look-up table multiplier? look-up table TIV(A) look-up table? TO 2 (A, B) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

21 General idea: second order approximation 12 input word decomposition: X = A + 2 α B =.a 1 a 2 a α b 1 b 2 b β w I A α B β order 2 approximation on each interval addressed by A: f(x) = K 0 (A) + K 1 (A) 2 α B + K 2 (A) 2 2α B 2 }{{}}{{}}{{} look-up table multiplier? look-up table TIV(A) look-up table? TO 2 (A, B) both Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 12 / 31

22 General idea: multiplication vs. look-up table tradeoff 13 second decomposition: B = B β 0B 1 =.b 1 b 2 b β0 b β0 +1 b β : w I A α B β B 0 B 1 β 0 β 1 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 13 / 31

23 General idea: multiplication vs. look-up table tradeoff 13 second decomposition: B = B β 0B 1 =.b 1 b 2 b β0 b β0 +1 b β : w I A α B β B 0 B 1 β 0 β 1 we obtain: K 1 (A) 2 α B = K 1 (A) 2 α B 0 + K 1 (A) 2 α β 0B 1 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 13 / 31

24 General idea: multiplication vs. look-up table tradeoff 13 second decomposition: B = B β 0B 1 =.b 1 b 2 b β0 b β0 +1 b β : w I A α B β B 0 B 1 β 0 β 1 we obtain: K 1 (A) 2 α B = K 1 (A) 2 α B 0 + K 1 (A) 2 α β 0B 1 }{{}}{{} multiplier look-up table TS(A) B 0 TO 1 (A, B 1 ) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 13 / 31

25 General idea 14 we have 4 tables: Table of Initial Values: Table of Slopes: Table of Offsets (order 1): Table of Offsets (order 2): TIV(A) = K 0 (A) TS(A) = 2 α K 1 (A) TO 1 (A, B 1 ) = 2 α β 0 K 1 (A) B 1 TO 2 (A, B) = 2 2α K 2 (A) B 2 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 14 / 31

26 General idea 14 we have 4 tables: Table of Initial Values: Table of Slopes: Table of Offsets (order 1): Table of Offsets (order 2): TIV(A) = K 0 (A) TS(A) = 2 α K 1 (A) TO 1 (A, B 1 ) = 2 α β 0 K 1 (A) B 1 TO 2 (A, B) = 2 2α K 2 (A) B 2 we obtain: f(x) = TIV(A) + TS(A) B 0 + TO 1 (A, B 1 ) + TO 2 (A, B) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 14 / 31

27 General idea: degrading accuracy 15 TIV(A) = K 0 (A) α α + β 0 2α f(x) TS(A) B 0 TO 1 (A, B 1 ) TO 2 (A, B) = 2 α K 1 (A) B 0 = 2 α β0 K 1 (A) B 1 = 2 2α K 2 (A) B 2 some of the terms are more accurate than others Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 15 / 31

28 General idea: degrading accuracy 15 TIV(A) = K 0 (A) α α + β 0 2α f(x) TS(A) B 0 TO 1 (A, B 1 ) TO 2 (A, B) = 2 α K 1 (A) B 0 = 2 α β0 K 1 (A) B 1 = 2 2α K 2 (A) B 2 some of the terms are more accurate than others Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 15 / 31

29 General idea: degrading accuracy 15 TIV(A) = K 0 (A) α α + β 0 2α f(x) TS(A) B 0 TO 1 (A, B 1 ) TO 2 (A, B) = 2 α K 1 (A) B 0 = 2 α β0 K 1 (A) B 1 = 2 2α K 2 (A) B 2 some of the terms are more accurate than others we can save area by addressing the more accurate tables with less bits Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 15 / 31

30 General idea: degrading accuracy 16 input word decomposition: w I A α B β A 0 α 0 B 0 β 0 A 1 α 1 B 1 β 1 A 2 α 2 B 2 β 2 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 16 / 31

31 General idea: degrading accuracy 16 input word decomposition: w I A α B β A 0 α 0 B 0 β 0 A 1 α 1 B 1 β 1 A 2 α 2 B 2 β 2 we obtain the final SMSO formula: f(x) = TIV(A) + TS(A 0 ) B 0 + TO 1 (A 1, B 1 ) + TO 2 (A 2, B 2 ) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 16 / 31

32 General idea: exploiting symmetry 17 both TO 1 and TO 2 have symmetry property: TO 1 (A 1, B 1 ) = TO 1 (A 1, B 1 ) TO 2 (A 2, B 2 ) = TO 2 (A 2, B 2 ) TO 1 (A 1, B 1 ) TO 2 (A 2, B 2 ) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 17 / 31

33 Architecture 18 X w I A TIV w O + g 0 B A 0 TS w O + g 1 w O + g 0 B 0 w O f(x) A 1 B 1 O X R TO 1 O X R w O + g 0 A 2 B 2 O X R TO 2 w O + g 0 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 18 / 31

34 Optimization 19 Context The SMSO method Optimization Rounding considerations Parameter space exploration Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 19 / 31

35 Rounding considerations 20 we want to achieve faithful rounding: f(x) f(x) < 2 w O Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 20 / 31

36 Rounding considerations 20 we want to achieve faithful rounding: f(x) f(x) < 2 w O the SMSO operator entails several errors: polynomial approximation: degrading table accuracy: rounding table values: final rounding: ɛ poly ɛ tab ɛ rt < 4 2 w O g w O g 1 1 ɛ rf < 2 w O 1 (1 2 g 0) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 20 / 31

37 Rounding considerations 21 error constraint: ɛ poly + ɛ tab + ɛ rt + ɛ rf < 2 w O Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 21 / 31

38 Rounding considerations 21 error constraint: ɛ poly + ɛ tab + ɛ rt + ɛ rf < 2 w O constraint on g 0 and g 1 : ɛ poly + ɛ tab w O g w O g w O 1 (1 2 g 0 ) < 2 w O Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 21 / 31

39 Rounding considerations 21 error constraint: ɛ poly + ɛ tab + ɛ rt + ɛ rf < 2 w O constraint on g 0 and g 1 : ɛ poly + ɛ tab w O g w O g w O 1 (1 2 g 0 ) < 2 w O assuming g 0 = g 1, we compute the bound: g 0 > log 2 ( ) 4 2 w O 1 ɛ poly ɛ tab w O 1 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 21 / 31

40 Parameter space exploration 22 lots of parameters: α, β, α 0, β 0, α 1, β 1, α 2, β 2, g 0, g 1 to find the best decomposition: parameter space exploration Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 22 / 31

41 Parameter space exploration 22 lots of parameters: α, β, α 0, β 0, α 1, β 1, α 2, β 2, g 0, g 1 to find the best decomposition: parameter space exploration the parameter space is huge, so we need a heuristic: find all the acceptable decompositions such that ɛ poly + ɛ tab < 2 w O 1 for each candidate: compute the bounds for g 0 and g 1 fill the tables compute the width of the signals apply a user-defined score function (area, latency, multiplier size,...) the score determines the best decomposition trial-and-error method to decrease g 0 and g 1 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 22 / 31

42 Results 23 Context The SMSO method Optimization Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 23 / 31

43 Results: ROM size 24 ROM size (in bits) 120k 100k log exp sin 80k 60k 40k 20k Input / output precision w I = w O (in bits) 25 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 24 / 31

44 Results: operator area 25 Operator area (in slices) lookup-multiply multipartite log exp sin Input / output precision w I = w O (in bits) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 25 / 31

45 Results: operator latency 26 Delay (in ns) multipartite log exp sin Input / output precision w I = w O (in bits) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 26 / 31

46 Results: using Virtex-II small multipliers 27 Function log Precision (w I = w O ) 16 bits 20 bits 24 bits Multiplier bit size not using area (slices) block multipliers delay (ns) using area (slices) block multipliers delay (ns) Function sin Precision (w I = w O ) (bits) Multiplier bit size not using area (slices) block multipliers delay (ns) using area (slices) block multipliers delay (ns) Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 27 / 31

47 Conclusion 28 Context The SMSO method Optimization Results Conclusion Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 28 / 31

48 Contribution 29 a novel function approximation method: second order: smaller tables only one small multiplier: shorter critical path, and can benefit from recent FPGA technologies (Virtex-II) accurate approximation and rounding error analysis automated exploration of the parameter space according to user-specified criteria Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 29 / 31

49 Future work 30 split the TO i s on several tables, as in the multipartite table method work on table compression techniques extend this method to higher order approximations Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 30 / 31

50 Thank you for your attention 31 Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 31 / 31

51 Thank you for your attention 31 Questions? Jérémie Detrey, Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs 31 / 31

Table-Based Polynomials for Fast Hardware Function Evaluation

Table-Based Polynomials for Fast Hardware Function Evaluation ASAP 05 Table-Based Polynomials for Fast Hardware Function Evaluation Jérémie Detrey Florent de Dinechin Projet Arénaire LIP UMR CNRS ENS Lyon UCB Lyon INRIA 5668 http://www.ens-lyon.fr/lip/arenaire/ CENTRE

More information

Table-based polynomials for fast hardware function evaluation

Table-based polynomials for fast hardware function evaluation Table-based polynomials for fast hardware function evaluation Jérémie Detrey, Florent de Dinechin LIP, École Normale Supérieure de Lyon 46 allée d Italie 69364 Lyon cedex 07, France E-mail: {Jeremie.Detrey,

More information

Hardware Operator for Simultaneous Sine and Cosine Evaluation

Hardware Operator for Simultaneous Sine and Cosine Evaluation Hardware Operator for Simultaneous Sine and Cosine Evaluation Arnaud Tisserand To cite this version: Arnaud Tisserand. Hardware Operator for Simultaneous Sine and Cosine Evaluation. ICASSP 6: International

More information

Table-based polynomials for fast hardware function evaluation

Table-based polynomials for fast hardware function evaluation Laboratoire de l Informatique du Parallélisme École Normale Supérieure de Lyon Unité Mixte de Recherche CNRS-INRIA-ENS LYON-UCBL n o 5668 Table-based polynomials for fast hardware function evaluation Jérémie

More information

Laboratoire de l Informatique du Parallélisme. École Normale Supérieure de Lyon Unité Mixte de Recherche CNRS-INRIA-ENS LYON n o 8512

Laboratoire de l Informatique du Parallélisme. École Normale Supérieure de Lyon Unité Mixte de Recherche CNRS-INRIA-ENS LYON n o 8512 Laboratoire de l Informatique du Parallélisme École Normale Supérieure de Lyon Unité Mixte de Recherche CNRS-INRIA-ENS LYON n o 8512 SPI A few results on table-based methods Jean-Michel Muller October

More information

Automatic generation of polynomial-based hardware architectures for function evaluation

Automatic generation of polynomial-based hardware architectures for function evaluation Automatic generation of polynomial-based hardware architectures for function evaluation Florent De Dinechin, Mioara Joldes, Bogdan Pasca To cite this version: Florent De Dinechin, Mioara Joldes, Bogdan

More information

Fixed-Point Trigonometric Functions on FPGAs

Fixed-Point Trigonometric Functions on FPGAs Fixed-Point Trigonometric Functions on FPGAs Florent de Dinechin Matei Iştoan Guillaume Sergent LIP, Université de Lyon (CNRS/ENS-Lyon/INRIA/UCBL) 46, allée d Italie, 69364 Lyon Cedex 07 June 14th, 2013

More information

Efficient Function Approximation Using Truncated Multipliers and Squarers

Efficient Function Approximation Using Truncated Multipliers and Squarers Efficient Function Approximation Using Truncated Multipliers and Squarers E. George Walters III Lehigh University Bethlehem, PA, USA waltersg@ieee.org Michael J. Schulte University of Wisconsin Madison

More information

On the number of segments needed in a piecewise linear approximation

On the number of segments needed in a piecewise linear approximation On the number of segments needed in a piecewise linear approximation Christopher L. Frenzen a, Tsutomu Sasao b and Jon T. Butler c. a Department of Applied Mathematics, Naval Postgraduate School, Monterey,

More information

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation Shinobu Nagayama Tsutomu Sasao Jon T. Butler Dept. of Computer Engineering, Dept. of Computer Science

More information

Automated design of floating-point logarithm functions on integer processors

Automated design of floating-point logarithm functions on integer processors 23rd IEEE Symposium on Computer Arithmetic Santa Clara, CA, USA, 10-13 July 2016 Automated design of floating-point logarithm functions on integer processors Guillaume Revy (presented by Florent de Dinechin)

More information

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations electronics Article Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations Masoud Sadeghian 1,, James E. Stine 1, *, and E. George Walters III 2, 1 Oklahoma

More information

NUMERICAL FUNCTION GENERATORS USING BILINEAR INTERPOLATION

NUMERICAL FUNCTION GENERATORS USING BILINEAR INTERPOLATION NUMERICAL FUNCTION GENERATORS USING BILINEAR INTERPOLATION Shinobu Nagayama 1, Tsutomu Sasao 2, Jon T Butler 3 1 Department of Computer Engineering, Hiroshima City University, Japan 2 Department of Computer

More information

Arithmetic Operators for Pairing-Based Cryptography

Arithmetic Operators for Pairing-Based Cryptography Arithmetic Operators for Pairing-Based Cryptography Jean-Luc Beuchat Laboratory of Cryptography and Information Security Graduate School of Systems and Information Engineering University of Tsukuba 1-1-1

More information

Arithmetic Operators for Pairing-Based Cryptography

Arithmetic Operators for Pairing-Based Cryptography Arithmetic Operators for Pairing-Based Cryptography J.-L. Beuchat 1 N. Brisebarre 2 J. Detrey 3 E. Okamoto 1 1 University of Tsukuba, Japan 2 École Normale Supérieure de Lyon, France 3 Cosec, b-it, Bonn,

More information

Automated design of floating-point logarithm functions on integer processors

Automated design of floating-point logarithm functions on integer processors Automated design of floating-point logarithm functions on integer processors Guillaume Revy To cite this version: Guillaume Revy. Automated design of floating-point logarithm functions on integer processors.

More information

A Hardware-Oriented Method for Evaluating Complex Polynomials

A Hardware-Oriented Method for Evaluating Complex Polynomials A Hardware-Oriented Method for Evaluating Complex Polynomials Miloš D Ercegovac Computer Science Department University of California at Los Angeles Los Angeles, CA 90095, USA milos@csuclaedu Jean-Michel

More information

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling esign and Implementation of a Radix-4 Complex ivision Unit with Prescaling Pouya ormiani Computer Science epartment University of California at Los Angeles Los Angeles, CA 90024, USA Email: pouya@cs.ucla.edu

More information

Arithmetic operators for pairing-based cryptography

Arithmetic operators for pairing-based cryptography 7. Kryptotag November 9 th, 2007 Arithmetic operators for pairing-based cryptography Jérémie Detrey Cosec, B-IT, Bonn, Germany jdetrey@bit.uni-bonn.de Joint work with: Jean-Luc Beuchat Nicolas Brisebarre

More information

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs Article Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs E. George Walters III Department of Electrical and Computer Engineering, Penn State Erie,

More information

Hardware implementations of fixed-point Atan2

Hardware implementations of fixed-point Atan2 Hardware implementations of fixed-point Atan2 Florent De Dinechin, Matei Istoan To cite this version: Florent De Dinechin, Matei Istoan. Hardware implementations of fixed-point Atan2. 22nd IEEE Symposium

More information

Karatsuba with Rectangular Multipliers for FPGAs

Karatsuba with Rectangular Multipliers for FPGAs Karatsuba with Rectangular Multipliers for FPGAs Martin Kumm, Oscar Gustafsson, Florent De Dinechin, Johannes Kappauf, Peter Zipf To cite this version: Martin Kumm, Oscar Gustafsson, Florent De Dinechin,

More information

Cost/Performance Tradeoff of n-select Square Root Implementations

Cost/Performance Tradeoff of n-select Square Root Implementations Australian Computer Science Communications, Vol.22, No.4, 2, pp.9 6, IEEE Comp. Society Press Cost/Performance Tradeoff of n-select Square Root Implementations Wanming Chu and Yamin Li Computer Architecture

More information

A Parallel Method for the Computation of Matrix Exponential based on Truncated Neumann Series

A Parallel Method for the Computation of Matrix Exponential based on Truncated Neumann Series A Parallel Method for the Computation of Matrix Exponential based on Truncated Neumann Series V. S. Dimitrov 12, V. Ariyarathna 3, D. F. G. Coelho 1, L. Rakai 1, A. Madanayake 3, R. J. Cintra 4 1 ECE Department,

More information

Return of the hardware floating-point elementary function

Return of the hardware floating-point elementary function Return of the hardware floating-point elementary function Jérémie Detrey, Florent De Dinechin, Xavier Pujol To cite this version: Jérémie Detrey, Florent De Dinechin, Xavier Pujol. Return of the hardware

More information

Section 5.8. Taylor Series

Section 5.8. Taylor Series Difference Equations to Differential Equations Section 5.8 Taylor Series In this section we will put together much of the work of Sections 5.-5.7 in the context of a discussion of Taylor series. We begin

More information

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks Yufei Ma, Yu Cao, Sarma Vrudhula,

More information

AP Calculus Summer Homework MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.

AP Calculus Summer Homework MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. AP Calculus Summer Homework 2015-2016 Part 2 Name Score MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. Find the distance d(p1, P2) between the points

More information

Math Practice Exam 3 - solutions

Math Practice Exam 3 - solutions Math 181 - Practice Exam 3 - solutions Problem 1 Consider the function h(x) = (9x 2 33x 25)e 3x+1. a) Find h (x). b) Find all values of x where h (x) is zero ( critical values ). c) Using the sign pattern

More information

Computing Machine-Efficient Polynomial Approximations

Computing Machine-Efficient Polynomial Approximations Computing Machine-Efficient Polynomial Approximations N. Brisebarre, S. Chevillard, G. Hanrot, J.-M. Muller, D. Stehlé, A. Tisserand and S. Torres Arénaire, LIP, É.N.S. Lyon Journées du GDR et du réseau

More information

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor Proposal to Improve Data Format Conversions for a Hybrid Number System Processor LUCIAN JURCA, DANIEL-IOAN CURIAC, AUREL GONTEAN, FLORIN ALEXA Department of Applied Electronics, Department of Automation

More information

CHALLENGE! (0) = 5. Construct a polynomial with the following behavior at x = 0:

CHALLENGE! (0) = 5. Construct a polynomial with the following behavior at x = 0: TAYLOR SERIES Construct a polynomial with the following behavior at x = 0: CHALLENGE! P( x) = a + ax+ ax + ax + ax 2 3 4 0 1 2 3 4 P(0) = 1 P (0) = 2 P (0) = 3 P (0) = 4 P (4) (0) = 5 Sounds hard right?

More information

Cost/Performance Tradeoffs:

Cost/Performance Tradeoffs: Cost/Performance Tradeoffs: a case study Digital Systems Architecture I. L10 - Multipliers 1 Binary Multiplication x a b n bits n bits EASY PROBLEM: design combinational circuit to multiply tiny (1-, 2-,

More information

A fast segmentation algorithm for piecewise polynomial numeric function generators

A fast segmentation algorithm for piecewise polynomial numeric function generators A fast segmentation algorithm for piecewise polynomial numeric function generators Jon T. Butler a Christopher L. Frenzen b, Njuguna Macaria c, and Tsutomu Sasao d a Department of Electrical and Computer

More information

Gal s Accurate Tables Method Revisited

Gal s Accurate Tables Method Revisited Gal s Accurate Tables Method Revisited Damien Stehlé UHP/LORIA 615 rue du jardin botanique F-5460 Villers-lès-Nancy Cedex stehle@loria.fr Paul Zimmermann INRIA Lorraine/LORIA 615 rue du jardin botanique

More information

Chapter 1 Numerical approximation of data : interpolation, least squares method

Chapter 1 Numerical approximation of data : interpolation, least squares method Chapter 1 Numerical approximation of data : interpolation, least squares method I. Motivation 1 Approximation of functions Evaluation of a function Which functions (f : R R) can be effectively evaluated

More information

ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders

ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders ECE 645: Lecture 3 Conditional-Sum Adders and Parallel Prefix Network Adders FPGA Optimized Adders Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7.4, Conditional-Sum

More information

Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA

Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA Chalermpol Saiprasert, Christos-Savvas Bouganis and George A. Constantinides Department of Electrical &

More information

This practice exam is intended to help you prepare for the final exam for MTH 142 Calculus II.

This practice exam is intended to help you prepare for the final exam for MTH 142 Calculus II. MTH 142 Practice Exam Chapters 9-11 Calculus II With Analytic Geometry Fall 2011 - University of Rhode Island This practice exam is intended to help you prepare for the final exam for MTH 142 Calculus

More information

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER Jesus Garcia and Michael J. Schulte Lehigh University Department of Computer Science and Engineering Bethlehem, PA 15 ABSTRACT Galois field arithmetic

More information

Efficient Polynomial Evaluation Algorithm and Implementation on FPGA

Efficient Polynomial Evaluation Algorithm and Implementation on FPGA Efficient Polynomial Evaluation Algorithm and Implementation on FPGA by Simin Xu School of Computer Engineering A thesis submitted to Nanyang Technological University in partial fullfillment of the requirements

More information

t t t ér t rs r t ét q s

t t t ér t rs r t ét q s rés té t rs té s é té r t q r r ss r t t t ér t rs r t ét q s s t t t r2 sé t Pr ss r rs té P r s 2 t Pr ss r rs té r t r r ss s Pr ss r rs té P r q r Pr ss r t r t r r t r r Prés t r2 r t 2s Pr ss r rs

More information

AES [and other Block Ciphers] Implementation Tricks

AES [and other Block Ciphers] Implementation Tricks AES [and other Bloc Ciphers] Implementation Trics Cryptographic algorithms Basic primitives Survey by Stephen et al, LNCS 1482, Sep. 98 General Structure of a Bloc Cipher Useful Properties for Implementing

More information

Computation of the error functions erf and erfc in arbitrary precision with correct rounding

Computation of the error functions erf and erfc in arbitrary precision with correct rounding Computation of the error functions erf and erfc in arbitrary precision with correct rounding Sylvain Chevillard Arenaire, LIP, ENS-Lyon, France Sylvain.Chevillard@ens-lyon.fr Nathalie Revol INRIA, Arenaire,

More information

Implementation Of Digital Fir Filter Using Improved Table Look Up Scheme For Residue Number System

Implementation Of Digital Fir Filter Using Improved Table Look Up Scheme For Residue Number System Implementation Of Digital Fir Filter Using Improved Table Look Up Scheme For Residue Number System G.Suresh, G.Indira Devi, P.Pavankumar Abstract The use of the improved table look up Residue Number System

More information

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method 3510 PAPER Special Section on VLSI Design and CAD Algorithms Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu NAGAYAMA a), Tsutomu SASAO

More information

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor Proceedings of the 11th WSEAS International Conference on COMPUTERS, Agios Nikolaos, Crete Island, Greece, July 6-8, 007 653 Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

More information

A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications

A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications Neural Engineering 27 A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications Awais M. Kamboh, Andrew Mason, Karim Oweiss {Kambohaw, Mason, Koweiss} @msu.edu Department

More information

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple

More information

Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives

Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives Miloš D. Ercegovac Computer Science Department Univ. of California at Los Angeles California Robert McIlhenny

More information

Newton-Raphson Algorithms for Floating-Point Division Using an FMA

Newton-Raphson Algorithms for Floating-Point Division Using an FMA Newton-Raphson Algorithms for Floating-Point Division Using an FMA Nicolas Louvet, Jean-Michel Muller, Adrien Panhaleux Abstract Since the introduction of the Fused Multiply and Add (FMA) in the IEEE-754-2008

More information

Semi-Automatic Floating-Point Implementation of Special Functions

Semi-Automatic Floating-Point Implementation of Special Functions Semi-Automatic Floating-Point Implementation of Special Functions Christoph Lauter 1 Marc Mezzarobba 1,2 Pequan group 1 Université Paris 6 2 CNRS ARITH 22, Lyon, 2015-06-23 }main() { int temp; float celsius;

More information

Problem 1 Kaplan, p. 436: 2c,i

Problem 1 Kaplan, p. 436: 2c,i Mathematical Methods I - Fall 03 Homework Solutions Page Problem Kaplan, p 36: c,i Find the first three nonzero terms of the following Taylor series: c) ln + x) about x = 0 i) arctanh x about x = 0 The

More information

ABHELSINKI UNIVERSITY OF TECHNOLOGY

ABHELSINKI UNIVERSITY OF TECHNOLOGY On Repeated Squarings in Binary Fields Kimmo Järvinen Helsinki University of Technology August 14, 2009 K. Järvinen On Repeated Squarings in Binary Fields 1/1 Introduction Repeated squaring Repeated squaring:

More information

Bound on Run of Zeros and Ones for Images of Floating-Point Numbers by Algebraic Functions

Bound on Run of Zeros and Ones for Images of Floating-Point Numbers by Algebraic Functions Bound on Run of Zeros and Ones for Images of Floating-Point Numbers by Algebraic Functions Tomas Lang, Jean-Michel Muller To cite this version: Tomas Lang, Jean-Michel Muller Bound on Run of Zeros and

More information

Calcul d indice et courbes algébriques : de meilleures récoltes

Calcul d indice et courbes algébriques : de meilleures récoltes Calcul d indice et courbes algébriques : de meilleures récoltes Alexandre Wallet ENS de Lyon, Laboratoire LIP, Equipe AriC Alexandre Wallet De meilleures récoltes dans le calcul d indice 1 / 35 Today:

More information

Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves

Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves CT-RSA 2012 February 29th, 2012 Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves Joint work with: Nicolas Estibals CARAMEL project-team, LORIA, Université de Lorraine / CNRS / INRIA,

More information

MATH 1231 MATHEMATICS 1B CALCULUS. Section 5: - Power Series and Taylor Series.

MATH 1231 MATHEMATICS 1B CALCULUS. Section 5: - Power Series and Taylor Series. MATH 1231 MATHEMATICS 1B CALCULUS. Section 5: - Power Series and Taylor Series. The objective of this section is to become familiar with the theory and application of power series and Taylor series. By

More information

Power Consumption Analysis. Arithmetic Level Countermeasures for ECC Coprocessor. Arithmetic Operators for Cryptography.

Power Consumption Analysis. Arithmetic Level Countermeasures for ECC Coprocessor. Arithmetic Operators for Cryptography. Power Consumption Analysis General principle: measure the current I in the circuit Arithmetic Level Countermeasures for ECC Coprocessor Arnaud Tisserand, Thomas Chabrier, Danuta Pamula I V DD circuit traces

More information

Computing correctly rounded logarithms with fixed-point operations. Julien Le Maire, Florent de Dinechin, Jean-Michel Muller and Nicolas Brunie

Computing correctly rounded logarithms with fixed-point operations. Julien Le Maire, Florent de Dinechin, Jean-Michel Muller and Nicolas Brunie Computing correctly rounded logarithms with fixed-point operations Julien Le Maire, Florent de Dinechin, Jean-Michel Muller and Nicolas Brunie Outline Introduction and context Algorithm Results and comparisons

More information

Computer Architecture 10. Fast Adders

Computer Architecture 10. Fast Adders Computer Architecture 10 Fast s Ma d e wi t h Op e n Of f i c e. o r g 1 Carry Problem Addition is primary mechanism in implementing arithmetic operations Slow addition directly affects the total performance

More information

Author(s) Beuchat, Jean-Luc; Muller, Jean-Mic. Citation IEEE transactions on computers, 57(

Author(s) Beuchat, Jean-Luc; Muller, Jean-Mic. Citation IEEE transactions on computers, 57( Title Automatic Generation of Modular Mul Applications Author(s) Beuchat, Jean-Luc; Muller, Jean-Mic Citation IEEE transactions on computers, 57( Issue Date 008-1 Text version publisher URL http://hdl.handle.net/41/101169

More information

1. Use the properties of exponents to simplify the following expression, writing your answer with only positive exponents.

1. Use the properties of exponents to simplify the following expression, writing your answer with only positive exponents. Math120 - Precalculus. Final Review. Fall, 2011 Prepared by Dr. P. Babaali 1 Algebra 1. Use the properties of exponents to simplify the following expression, writing your answer with only positive exponents.

More information

Part VI Function Evaluation

Part VI Function Evaluation Part VI Function Evaluation Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations

More information

Lecture 11. Advanced Dividers

Lecture 11. Advanced Dividers Lecture 11 Advanced Dividers Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 15 Variation in Dividers 15.3, Combinational and Array Dividers Chapter 16, Division

More information

Rigorous Polynomial Approximations and Applications

Rigorous Polynomial Approximations and Applications Rigorous Polynomial Approximations and Applications Mioara Joldeș under the supervision of: Nicolas Brisebarre and Jean-Michel Muller École Normale Supérieure de Lyon, Arénaire Team, Laboratoire de l Informatique

More information

NUMERICAL MATHEMATICS & COMPUTING 6th Edition

NUMERICAL MATHEMATICS & COMPUTING 6th Edition NUMERICAL MATHEMATICS & COMPUTING 6th Edition Ward Cheney/David Kincaid c UT Austin Engage Learning: Thomson-Brooks/Cole www.engage.com www.ma.utexas.edu/cna/nmc6 September 1, 2011 2011 1 / 42 1.1 Mathematical

More information

A Deep Convolutional Neural Network Based on Nested Residue Number System

A Deep Convolutional Neural Network Based on Nested Residue Number System A Deep Convolutional Neural Network Based on Nested Residue Number System Hiroki Nakahara Tsutomu Sasao Ehime University, Japan Meiji University, Japan Outline Background Deep convolutional neural network

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19

More information

Laboratoire de l Informatique du Parallélisme

Laboratoire de l Informatique du Parallélisme Laboratoire de l Informatique du Parallélisme Ecole Normale Supérieure de Lyon Unité de recherche associée au CNRS n 1398 Reciprocation, Square root, Inverse Square Root, and some Elementary Functions

More information

Optimizing Scientific Libraries for the Itanium

Optimizing Scientific Libraries for the Itanium 0 Optimizing Scientific Libraries for the Itanium John Harrison Intel Corporation Gelato Federation Meeting, HP Cupertino May 25, 2005 1 Quick summary Intel supplies drop-in replacement versions of common

More information

HARDWARE IMPLEMENTATION OF FIR/IIR DIGITAL FILTERS USING INTEGRAL STOCHASTIC COMPUTATION. Arash Ardakani, François Leduc-Primeau and Warren J.

HARDWARE IMPLEMENTATION OF FIR/IIR DIGITAL FILTERS USING INTEGRAL STOCHASTIC COMPUTATION. Arash Ardakani, François Leduc-Primeau and Warren J. HARWARE IMPLEMENTATION OF FIR/IIR IGITAL FILTERS USING INTEGRAL STOCHASTIC COMPUTATION Arash Ardakani, François Leduc-Primeau and Warren J. Gross epartment of Electrical and Computer Engineering McGill

More information

Complex Square Root with Operand Prescaling

Complex Square Root with Operand Prescaling Complex Square Root with Operand Prescaling Milos Ercegovac, Jean-Michel Muller To cite this version: Milos Ercegovac, Jean-Michel Muller. Complex Square Root with Operand Prescaling. [Research Report]

More information

Analog and Telecommunication Electronics

Analog and Telecommunication Electronics Politecnico di Torino - ICT School Analog and Telecommunication Electronics D3 - A/D converters» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters» Origin of errors 12/05/2011-1

More information

A 32-bit Decimal Floating-Point Logarithmic Converter

A 32-bit Decimal Floating-Point Logarithmic Converter A 3-bit Decimal Floating-Point Logarithmic Converter Dongdong Chen 1, Yu Zhang 1, Younhee Choi 1, Moon Ho Lee, Seok-Bum Ko 1, Department of Electrical and Computer Engineering, University of Saskatchewan

More information

Solution of Algebric & Transcendental Equations

Solution of Algebric & Transcendental Equations Page15 Solution of Algebric & Transcendental Equations Contents: o Introduction o Evaluation of Polynomials by Horner s Method o Methods of solving non linear equations o Bracketing Methods o Bisection

More information

Power Series Solutions We use power series to solve second order differential equations

Power Series Solutions We use power series to solve second order differential equations Objectives Power Series Solutions We use power series to solve second order differential equations We use power series expansions to find solutions to second order, linear, variable coefficient equations

More information

Arithmetic Circuits-2

Arithmetic Circuits-2 Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier

More information

Optimizing MPC for robust and scalable integer and floating-point arithmetic

Optimizing MPC for robust and scalable integer and floating-point arithmetic Optimizing MPC for robust and scalable integer and floating-point arithmetic Liisi Kerik * Peeter Laud * Jaak Randmets * * Cybernetica AS University of Tartu, Institute of Computer Science January 30,

More information

Improving Goldschmidt Division, Square Root and Square Root Reciprocal

Improving Goldschmidt Division, Square Root and Square Root Reciprocal INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE Improving Goldschmidt Division, Square Root and Square Root Reciprocal Milos Ercegovac, Laurent Imbert, David Matula, Jean-Michel Muller,

More information

A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m )

A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) Stefan Tillich, Johann Großschädl Institute for Applied Information Processing and

More information

Taylor and Maclaurin Series. Approximating functions using Polynomials.

Taylor and Maclaurin Series. Approximating functions using Polynomials. Taylor and Maclaurin Series Approximating functions using Polynomials. Approximating f x = e x near x = 0 In order to approximate the function f x = e x near x = 0, we can use the tangent line (The Linear

More information

MATH 115 Precalculus Spring, 2015, V1.2

MATH 115 Precalculus Spring, 2015, V1.2 MULTIPLE CHOICE 1. Solve, and express the answer in interval notation: 6 5x 4. 1. A. (, 2] [2/5, ) B. [2/5, 2] C. (, 2/5] D. (, 2/5] [2, ) 2. Which of the following polynomials has a graph which exhibits

More information

WebAssign Lesson 6-3 Taylor Series (Homework)

WebAssign Lesson 6-3 Taylor Series (Homework) WebAssign Lesson 6-3 Taylor Series (Homework) Current Score : / 56 Due : Tuesday, August 5 204 0:59 AM MDT Jaimos Skriletz Math 75, section 3, Summer 2 204 Instructor: Jaimos Skriletz. /4 points Consider

More information

THIS paper is devoted to the study of modular multiplication

THIS paper is devoted to the study of modular multiplication AUTOATIC GENERATION OF OULAR ULTIPLIERS FOR FPGA APPLICATIONS Automatic Generation of odular ultipliers for FPGA Applications Jean-Luc Beuchat and Jean-ichel uller, Senior ember, IEEE LIP Research Report

More information

On-Line Hardware Implementation for Complex Exponential and Logarithm

On-Line Hardware Implementation for Complex Exponential and Logarithm On-Line Hardware Implementation for Complex Exponential and Logarithm Ali SKAF, Jean-Michel MULLER * and Alain GUYOT Laboratoire TIMA / INPG - 46, Av. Félix Viallet, 3831 Grenoble Cedex * Laboratoire LIP

More information

Taylor and Maclaurin Series. Approximating functions using Polynomials.

Taylor and Maclaurin Series. Approximating functions using Polynomials. Taylor and Maclaurin Series Approximating functions using Polynomials. Approximating f x = e x near x = 0 In order to approximate the function f x = e x near x = 0, we can use the tangent line (The Linear

More information

FPGA Resource Utilization Estimates for NI crio LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008

FPGA Resource Utilization Estimates for NI crio LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 FPGA Resource Utilization Estimates for NI crio-9104 LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your

More information

function independent dependent domain range graph of the function The Vertical Line Test

function independent dependent domain range graph of the function The Vertical Line Test Functions A quantity y is a function of another quantity x if there is some rule (an algebraic equation, a graph, a table, or as an English description) by which a unique value is assigned to y by a corresponding

More information

Numerical Solution of f(x) = 0

Numerical Solution of f(x) = 0 Numerical Solution of f(x) = 0 Gerald W. Recktenwald Department of Mechanical Engineering Portland State University gerry@pdx.edu ME 350: Finding roots of f(x) = 0 Overview Topics covered in these slides

More information

Efficient Subquadratic Space Complexity Binary Polynomial Multipliers Based On Block Recombination

Efficient Subquadratic Space Complexity Binary Polynomial Multipliers Based On Block Recombination Efficient Subquadratic Space Complexity Binary Polynomial Multipliers Based On Block Recombination Murat Cenk, Anwar Hasan, Christophe Negre To cite this version: Murat Cenk, Anwar Hasan, Christophe Negre.

More information

Computing Machine-Efficient Polynomial Approximations

Computing Machine-Efficient Polynomial Approximations Computing Machine-Efficient Polynomial Approximations NICOLAS BRISEBARRE Université J. Monnet, St-Étienne and LIP-E.N.S. Lyon JEAN-MICHEL MULLER CNRS, LIP-ENS Lyon and ARNAUD TISSERAND INRIA, LIP-ENS Lyon

More information

Math Numerical Analysis

Math Numerical Analysis Math 541 - Numerical Analysis Joseph M. Mahaffy, jmahaffy@mail.sdsu.edu Department of Mathematics and Statistics Dynamical Systems Group Computational Sciences Research Center San Diego State University

More information

The GigaFitter for Fast Track Fitting based on FPGA DSP Arrays

The GigaFitter for Fast Track Fitting based on FPGA DSP Arrays The GigaFitter for Fast Track Fitting based on FPGA DSP Arrays Pierluigi Catastini (Universita di Siena - INFN Pisa) For the SVT Collaboration SVT: A Success for CDF 35µm 33µm resol beam σ = 48µm SVT provides

More information

Continued fractions and number systems: applications to correctly-rounded implementations of elementary functions and modular arithmetic.

Continued fractions and number systems: applications to correctly-rounded implementations of elementary functions and modular arithmetic. Continued fractions and number systems: applications to correctly-rounded implementations of elementary functions and modular arithmetic. Mourad Gouicem PEQUAN Team, LIP6/UPMC Nancy, France May 28 th 2013

More information

An Algorithm for the η T Pairing Calculation in Characteristic Three and its Hardware Implementation

An Algorithm for the η T Pairing Calculation in Characteristic Three and its Hardware Implementation An Algorithm for the η T Pairing Calculation in Characteristic Three and its Hardware Implementation Jean-Luc Beuchat 1 Masaaki Shirase 2 Tsuyoshi Takagi 2 Eiji Okamoto 1 1 Graduate School of Systems and

More information

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process Computer Architecture ESE 345 Computer Architecture Design Process 1 The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH

More information

Hardware Acceleration of the Tate Pairing in Characteristic Three

Hardware Acceleration of the Tate Pairing in Characteristic Three Hardware Acceleration of the Tate Pairing in Characteristic Three CHES 2005 Hardware Acceleration of the Tate Pairing in Characteristic Three Slide 1 Introduction Pairing based cryptography is a (fairly)

More information

EECS150 - Digital Design Lecture 22 - Arithmetic Blocks, Part 1

EECS150 - Digital Design Lecture 22 - Arithmetic Blocks, Part 1 EECS150 - igital esign Lecture 22 - Arithmetic Blocks, Part 1 April 10, 2011 John Wawrzynek Spring 2011 EECS150 - Lec23-arith1 Page 1 Each cell: r i = a i XOR b i XOR c in Carry-ripple Adder Revisited

More information