Electro-Thermal Modelling of High Power Light Emitting Diodes Based on Experimental Device Characterisation

Transcription

1 Presented at the COMSOL Conference 2008 Boston Electro-Thermal Modelling of High Power Light Emitting Diodes Based on Experimental Device Characterisation Toni López Comsol Conference, Boston 2008

2 Outline Introduction LUXEON K2 Emitter LED Characterisation and Modelling Electric model Thermal model Coupled electro-thermal model Experimental validation Summary 2

3 LUXEON K2 Lamps The goal is to accurately model the electro-thermal performance of high power LEDs for the assessment of relevant effects such as, Current crowding Thermal hot spots Self-heating Forward voltage Operating Specs: 1A forward current, over 200lm, 185 C junction temperature 3

4 Structure of TFFC LED 1mm Thin-Film Flip-Chip Technology N-layer contacted from p-layer side by means of 16 circular vias and edge contact P-metal contact also acts as optical reflector 25 gold stud-bumps employed to interconnect chip and submount 4

5 Outline Introduction LUXEON K2 Emitter LED Characterisation and Modelling Electric model Thermal model Coupled electro-thermal model Experimental validation Summary 5

6 Basic Representation of the Chip Multilayer Stack LED chip consists out of multiple semiconductor, dielectric and metal layers, which are arranged according to the TFFC arquitecture Basically, the n-semiconductor sheet (of just a few microns thick) is used as spreading layer. It is the only semiconductor layer where current may flow laterally Thus, the distributed effects may be represented by a ladder network of lumped elements, the vertical elements being non-linear according to a diode like function and a series resistance N-metal Dielectric Active region (AR) P-layer P-metal layer P-contact 6

7 Basic Representation of the Chip Multilayer Stack LED chip consists out of multiple semiconductor, dielectric and metal layers, which are arranged according to the TFFC arquitecture Basically, the n-semiconductor sheet (of just a few microns thick) is used as spreading layer. It is the only semiconductor layer where current may flow laterally Thus, the distributed effects may be represented by a ladder network of lumped elements, the vertical elements being non-linear according to a diode like function and a series resistance I f Rnc drn drn drn drn drar drar drar drar drar drar N-metal Active region (AR) P-layer V f drpc drpc drpc drpc drpc drpc P-metal layer Dielectric P-contact 7

8 Electric Model Implementation a) The basic multilayer stack may require up to six different subdomains. At least one of them, the AR subdomain, may involve the definition of a non-linear conductivity that is dependent on the local electric field (a) (b) N-m etal Active region (AR) P-layer P-metal layer N-metal P-layer P-metal layer AR P-contact Dielectric P-contact Dielectric (c) (d) N-m etal P-metal layer Dielectric P-contact+AR P-contact+AR 8

9 Electric Model Implementation b) The current flows unidirectionally vertically in the AR. Thus, it may be described by way of an interior boundary condition as opposed to a subdomain. The boundary condition is of the type distributed resistance where the conductivity may be nonlinear and dependent on the local voltage difference between the two sem. layers (a) (b) N-m etal Active region (AR) P-layer P-metal layer N-metal P-layer P-metal layer AR P-contact Dielectric P-contact Dielectric (c) (d) N-m etal P-metal layer Dielectric P-contact+AR P-contact+AR 9

10 Electric Model Implementation c) The current through the p-layer flows vertically. This layer is very thin and thus it can be omitted since its contribution to electric losses is negligible. The elimination of the p-layer involves the combination of the AR and p-contact in one single interior boundary (a) (b) N-m etal Active region (AR) P-layer P-metal layer N-metal P-layer P-metal layer AR P-contact Dielectric P-contact Dielectric (c) (d) N-m etal P-metal layer Dielectric P-contact+AR P-contact+AR 10

11 Electric Model Implementation d) The elimination of the metal layers, which do not contribute to losses, enables the use of external boundary conditions as opposed to interior ones for the definition of the contacts and AR, thereby greatly simplifiyng the implementation (a) (b) N-m etal Active region (AR) P-layer P-metal layer N-metal P-layer P-metal layer AR P-contact Dielectric P-contact Dielectric (c) (d) N-m etal P-metal layer Dielectric P-contact+AR P-contact+AR 11

12 Simplified Electric Model Implementation Single subdomain characterised by a temperature dependent conductivity, which is described by a look up table (LUT) Distributed resistance boundary conditions for metal-semicond. contacts and active region (AR) representation. Conductivities may be voltage and temperature dependent. Use of LUTs ρ = ( T ) d n R SH d Parameter Units Variable of dependence n Measurement technique Specific n-contact Ω-cm 2 T TLM ctlm resistance ρ nc AR _ pc( V1+ Specific p-contact Ω-cm 2 V, T TLM ctlm resistance ρ pc R SH (T ) : N-layer resistivity ρ n Ω-cm T TLM ctlm Specific active region resistance ρ AR V n J = (T ) ρ nc Ω-cm 2 V, T IV curve tracer P-contact+AR Vf V J = ρ (, ) Test structure AR _ pc Vf V T Extraction method Single side n- contact emitter ctlm equation, = linear ρ ARextrapolation ( V1, T) ctlm equation, linear extrapolation ctlm equation, linear extrapolation Algorithm of system identification ρ V 2, T) + ρ Vf : pc ( V 2, T) Sheet resistance (Ω/ ). Measurable quantity Applied voltage 12

13 Extension to a 3D Subdomain Simplified 2D structure TFFC 3D structure (¼ chip) ρ = ( T) d n R SH d ρ n d Non-isolated boundary conditions (Distributed resistance): n J P-contact+AR = ρ AR _ pc Vf V ( Vf V, T ) n J = ρ nc V (T ) 13

14 Extraction of Device Characteristics Parameter (No thermal params. included) Variable of dependence Measurement technique Test structure Extraction method 1. Specific n-contact resistance 2. Sheet resistance Temperature TLM ctlm ctlm equation, linear extrapolation 3. Specific p-contact resistance Temperature and current density TLM ctlm ctlm equation, linear extrapolation 4. Active region IV curve Temperature and current density IV-curve tracer Single side n-contact emitter Algorithm of system identification 5. Radiant emittance and/or irradiance Temperature and current density Integrating sphere, gonometer Single side n-contact emitter Algorithm of system identification 14

15 AR & P-contact resistivity extraction algorithm FE Simulation of Test structure Rs ρ cn ρ AR_pc =ρ pc +ρ AR (?) Goal: Extraction of the AR & p-contact resistivities from the IV curves measured at the device terminals Challenge: This is not readily obtained due to the non-linearity of the resistivities and the distributed nature of the device structure (i.e. non-uniform current distribution) Solution: System identification techniques. I.e. advance algorithms to determine model parameters from measured data. 15

16 AR & P-contact resistivity extraction algorithm FE Simulation of Test structure Rs ρ cn ρ AR_pc =ρ pc +ρ AR (?) AR & P-contact resistivity improved GUESS If Meas. vs. sim. Error evaluation Parameter estimation 100 ρ AR_pc 10 Vf Jf 16

17 AR & P-contact resistivity extraction algorithm FE Simulation of Test structure Rs Repeat loop until error is minimised 1 ρ cn Current (A) 0.01 Goal: Extraction of the AR & p-contact resistivities from the IV curves measured Meas. vs. sim. Measurement Parameter estimation at the If device terminals Challenge: This is not readily obtained Error due to the non-linearity ρ 10 of the resistivities and the distributed nature of the evaluation Voltage (V) AR_pc device structure (i.e. non-uniform current distribution) Vf 0.1 ρ AR_pc =ρ pc +ρ AR (?) Simulation AR & P-contact resistivity improved GUESS Solution: System identification techniques. I.e. advance algorithms to determine model parameters from measured data. 100 Jf 17

18 Thermal Model Governing equation: Fourier s law of heat conduction Generated heat in the chip is transferred to the PCB through the package submount and heat-sink Constant board temperature (boundary condition) Model considers 3D package and chip geometry and all material s thermal conductivities Chip Au-Au interconnect Submount attach Pb-free solder Q Submount Heat-sink PCB (Uniform Board Temperature) 18

19 Coupling Thermal and Electric Models Electric and thermal models are coupled by the mutual dependencies of the following parameters Electric conductivities (contacts, spreading layer...) P ( T ) = P ( T ) 1 WPE( T ), P ( T ) = I ( T ) V Power dissipation: ( ) Heat Total Total f f I f (T) Electric Thermal V f LED P Heat (T) R TH T 19

20 Meshing Thin Layers 1. Boundary free mesh parameters for x-y boundary plane d 2. Swept mesh parameters for z (use of 2 element layers) y z x d y x Top view z x Lateral view 20

21 Outline Introduction LUXEON K2 Emitter LED Characterisation and Modelling Electric model Thermal model Coupled electro-thermal model Experimental validation Summary 21

22 Coupled Electro-Thermal Simulation Example Use of Direct solver PARDISO, num. mesh elements: , degrees of freedom: , computation time: 17min., WinXP 64bit, Intel Xeon CPU, 2.66GHz, 12GB RAM Thermal non-uniformity impacts power density distribution and thus the surface brightness Estimated thermal resistance matches experimental results (a) Power density map (W/mm 2 ) (b) Thermal map Junction-Case Temp. (K) Average heat power=1.97w, If=0.74A, Vf=3.09V, Tcase=89.6 C Average Tj=108.5 C, Vf=3.09V, If=0.74A, Tcase=89.6 C, Rth(j-c)=9.6K/W (w.r.t average temperature) 22

23 IV-Curves of Various Primary Emitter Layouts Simulations match up accurately measurement curves at constant 30 C junction temperature (pulse operation). Wafer near neighbor devices Current If (A) Measurement Simulation Voltage Vf (V) Current If (A) Measurement Simulation Voltage Vf (V) 10 1 Current If (A) Current (A) Measurement Simulation Voltage Vf (V) Measurement Simulation Voltage (V) 23

24 Surface Brightness of Various Primary Emitter Layouts Predictions within 15% error at constant 30 C junction temperature (pulse operation). Wafer near neighbor devices. Irradiance (mw/mm^2) (W/mm^2) 40 Vf=5V, If=1.8A Irradiance (mw/mm^2) Vf=5.5V, If=2.4A Measurement Simulation x (mm) x (mm) Irradiance (mw/mm^2) (W/m^2) Vf=7V, If=175mA Irradiance (mw/mm^2) (W/m^2) Vf=3V, If=40mA Measurement Simulation x (mm) x x (mm) (um) 24

25 IV-Curves of a LUXEON K2 Emitter without Self-Heating Experimental and simulated IV-curve characteristics at constant 90 C under pulse operation (i.e. without self-heating) 10 Forward current (A) Simulation Measurement Forward voltage (V) 25

26 IV-Curves of a LUXEON K2 Emitter with Self-Heating Experimental and simulated IV-curve characteristics under dc operation (i.e. with self-heating) Forward current If (A) Tj=130 C Tj=110 C Tj=90 C Tj=70 C Tj=50 C Tj=30 C Junction-Case Temp. (K) Simulation Measurement Forward voltage Vf (V) Forward current (ma) Measurement (pulse) Simulation (dc) Measurement (dc) 26

27 Outline Introduction LUXEON K2 Emitter LED Characterisation and Modelling Electric model Thermal model Coupled electro-thermal model Experimental validation Summary 27

28 Summary and Conclusions 3D FE model is shown to be an effective tool to analyse the electrothermal behaviour of power LEDs Current crowding, forward voltage, self-heating, average thermal resistance and hot spots have been accurately modelled and validated over a wide range of operating conditions Simple model implementation based on a single subdomain and distributed resistance boundary conditions Four basic electric parameters to describe electrical behaviour are experimentally characterised and expressed in Comsol by means of LUTs Algorithm of system identification implemented in the Script language has been proposed for the extraction of the LED active region electrical characteristics from experimental data 28

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