ELECTRONICS & TELECOMMUNICATION ENGINEERING SUBJECT: ANALOG ELECTRONICS AND DIGITAL ELECTRONICS AND MICRO PROCESSORS SOLUTIONS

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1 S ID: 0 S- 09 (Pelis) - Offline est Seies est- LCONICS & LCOMMUNICAION NGINING SUJC: ANALOG LCONICS AND DIGIAL LCONICS AND MICO POCSSOS SOLUIONS 0. Ans: (b) he given cicuit can be edawn as below A A XNO of equal inputs is Z = 0. Ans: (b) A C Aʘ = Aʘ = y A he coon aea occupied by the given venn diaga is equivalent to its oolean epession = A C AC 03. Ans: (c) uth table of copaato: C ʘy Z = (Aʘ)ʘ(Aʘ) A C X A A Y A A Z = A ʘ A = It is a copaato 04. Ans: (c) Miniization of oolean epession is educing copleity and cost of syste. It educes nube of gates equied fo ipleentation and also nube of inputs (fan-in) of gates. 05. Ans: (d) f A,,C,D A C D f(a,,c,d) CD A CD A f(a,, C, D) 0 0 nube of intes in f(a,, C, D) is 9. A A = A < A > Ans: (a) he ange of decial integes can be epesented using n bits is n to ( n ) he ange of decial integes using 9 bits is 9 to ( 9 ) i.e., 56 to 55. AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

2 : : lectonics & elecounication ngineeing 07. Ans: (a) he F's copleent of headecial nube C09.0F30 F s copleent 08. Ans: (a) It is od counte. Afte 300 clock cycles 300% = 0 So, the state afte 300 clock cycles is initial state only. So, Q 3 Q Q Q 0 state afte 300 clock cycles is Ans: (d) A synchonous counte state changes in one Flipflop delay, if it is changing fo one state to anothe state. he popagation delay is independent of nube of bits. he aiu tie equied is 0ns. 0. Ans: (b) It is a ing counte. So D 3 =Q 0, D = Q 3, D = Q, D 0 = Q Q 3 Q Q Q he odulus of counte is. Ans: (c) he size of the OM = 88 = 7 8 he total nube of bits need not to be pogaed = [ 7 8] [ 6 6] = 6 [(8) 6] = 640 = 640 AC ngineeing Acadey () FFFF. FFFFF C09. 0F30 3F6. DF0CF. Ans: (d) he capacity of PLA is specified by the nube of inputs, nube of poduct tes and nube of outputs. 3. Ans: (c) MOS logic offes low powe consuption. ecause of the low voltage equieent, it is highly suitable fo battey opeated systes. MOS logic has highest packing density and high fan-out 4. Ans: (b) Fo the signals fo evaluating noise agin shown above, OH > IH IL > OL OH > OL IH > IL option (b) is incoect 5. Ans: (c) Fo had eal-tie systes, no deadline isses ae toleated. Fo soft eal-tie systes, it is acceptable fo tasks to iss deadlines occasionally and tasks not finished by thei deadlines ae still copleted, albeit with educed values. Fi eal-tie systes also allow occasional deadline isses. Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad CC 0 output voltage ange OH OL High state noise agin CC IH IL low-state noise agin 0 input voltage ange

3 : 3 : S - 09 (Pelis) Offline est Seies 6. Ans: (d) Z C D A CD A A CDA A C D 0,5,3, 5 A CD ACD ACD 7. Ans: (b) (A) Y AC AC A C C A A Fo Y opeation 6 NAND gates ae equied () Y A A C C No need of NAND gate (C) Y A C A Y A A A A 4 NAND gates ae equied. 8. Ans: (a) A C AC is a self dual function A C AC is cay output of full adde A C AC is esulting output when nube of s ae oe Full subtacto boow epession is = A C AC 9. Ans: (c) f(a,,c,d) = (, 5, 7,, 3, 4) d(3,, 5) A A Y A A,,C,D A AD f Fo the input 00, f = (0.0) (.) = Fo the input 0, f = (.0) (0.) = 0 0. Ans: (a) CD Ans: (c) he cicuit is S flip flop with S Q and = Q. So the output Q is copleenting at evey clock cycle clock Q Q = f f Q GHz 0.5GHz A D A 47 = sign agnitude. Ans: (c) CD to 7 segent ---cobinational cicuit 4 to ultiplee ---- cobinational cicuit 4 bit shift egiste --- sequential cicuit CD counte ---- sequential cicuit AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

4 : 4 : lectonics & elecounication ngineeing 3. Ans: (c) Synchonous counte will povide clock at a tie to all flip flops. Hence it povides least delay copaed to othe countes. 4. Ans: (b) (a) Coect stateent = esolution of 0 bit digital ap ADC ef 0 = esolution of 8 bit digital ap ADC ef 8 < has bette esolution than (b) Convesion tie of SA = n hat eans independent of input voltage, SA convesion tie is always depends on nube of bits only (c) A flash ADC not contains a DAC is also ight stateent. (d) CO is the ain coponent of a voltage to fequency ADC. his also ight stateent. 5. Ans: (c) esolution = p he nube of steps equied fo 50 speed 50 is = 30 = Ans: (b) esolution 0.0% n 0,000 Miniu nube of bits = 4 7. Ans: (b) A dual slope ADC integates an unknown input voltage ( in ) fo a fied aount of tie ( int ), then de-integates ( de-int ) using a known efeence voltage ( F ) fo a vaiable aount of tie. int is fied in de-int F Any eo intoduced by a coponent value duing the integate cycle will be cancelled out duing the de-integate phase. De-integation tie peiod is vaiable and depends on nube of pulses counted duing st integation. 8. Ans: (a) MI, 00H; [] = 00H MI C, 00H; [C] = 00H LOOP: DC C ; [C] = FFH JNZ LOOP DC JNZ LOOP ; Z-flag = so again loop eecutes till [C] = 00H, i.e 56 ties ; [] = FFH ; zeo flag = so again loop eecutes AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

5 : 5 : S - 09 (Pelis) Offline est Seies Fo [] = FFH 56 ties Fo [] = FH 56 ties Fo [] = FDH 56 ties Fo [] = 00H 56 ties loop eecutes fo ties 9. Ans: (b) XA A ; [A] = 00H, CY = 0 ACI 05H ; [A] = [A] CY 05H = 05H = LC ; [A] = = 0AH, CY = 0 MO, A ; [] = 0AH LC ; [A] = , CY = 0 LC ; [A] = , CY = 0 ADD ; [A] [A] [] = 3H MO C, A ; [C] = 3H 30. Ans: (c) he inteupt vecto table consists of 56 nube of 4-byte pointes, and esides in the fist k of addessable eoy. ach inteupt nube is eseved fo a specific pupose. 3. Ans: (a) hee ae total 9 flags in 8086 (a) conditional o status flags : 6 flags. Sign flag (S). Zeo flag (Z) 3. Auiliay cay flag (AC) 4. Paity flag (P) 5. Cay flag (CY) 6 Ove flow flag (O) (b) Contol flags : 3 flags. Diectional flag (D). Inteupt flag (I) 3. ap flag () 3. Ans: (a) he flag egiste (poga status wod) of 805 icocontolle is: CY AC F0 S S0 O P Cay flag (CY), auiliay cay (AC), paity (P) and oveflow (O) ae conditional flags. hee is no zeo flag in Ans: (c) XL opeand, opeand: a bitwise "XCLUSI O" opeation between opeand and opeand, leaving the esulting value in opeand. Hee, opeand is [A] = FFH [A] FF 6 So, it finds the 's copleent of 6 egiste. AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

6 : 6 : lectonics & elecounication ngineeing AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

7 : 7 : S - 09 (Pelis) Offline est Seies 34. Ans: (b) he tie delay fo JNZ is 0 if it satisfies the condition othewise it is 7. LOOP eecutes till the content of C egiste becoes 0, i.e., fo 5 ties. Fo the fist fou ties JNZ condition will not satisfies, so this instuction will take 0 states. ut duing 5th tie, JNZ satisfies, which takes 7 states. Delay = O L 3 = 4 (56) 3 = Ans: (c). ADY is active high signal. When it is high, it indicates that the device is eady to tansfe data. When it is low, it indicates wait state.. AL is high only duing. when AL goes low, the addess is saved and AD7 - AD0 lines can be used fo thei pupose as the bi-diectional data lines. Stateents () & () ae false 3) C configuation has high voltage gain and its cuent gain is appoiately. Given thee stateents ae incoect. 37. Ans: (c) 38. Ans: (a) in ype of powe aplifie Class-A Class- Class-A Conduction angle 360 o 80 o > 80 o Class-C < 80 d d d d 0 0k 36. Ans: (d) ) In Coon eitte configuation the input chaacteistics ae plotted between and I at constant C. in d 0k 0 I Constant C 0 in 0k 0k d ) Coon base configuation is acts as a cuent buffe whose input esistance is vey low(zeo ideally). So C configuation has lowe esistance copaed to C. AC ngineeing Acadey d I / I I = 5 A in Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally d 0k 0 0k 0k k 5A 0.5 /

8 : 8 : lectonics & elecounication ngineeing 39. Ans: (b) Fo i = 5 (Q ) gets ON, (Q ) gets OFF 5 0k I 0.7 Q I k 0 g f ICQ A 0.04 A / kHz 3 30 Q is in active egion Apply KL I 0.7 0I 5 = 0 I I I = 3.9A. 0 = I (k) = Ans: (b) g f (C C ) 5 4. Ans: (c) Maiu voltage on seconday side olts dc no load olts 4. Ans: (c) Negative feedback in OP-ap educes the voltage gain and akes the linea opeations possible. Oscillations possible with positive feedback. 43. Ans: (d) (A) Hatley oscillato () C phase shift oscillato (C) Wein bidge oscillato (D) Colpitt s oscillato : Inductive feedback is used : Pue sine wave output is possible : oth positive and negative feedback : Capacitive feedback is used 44. Ans: (a) da 0 Given that, 0. A 00 daf 0. aiation in closed loop gain Af 00 Sensitivity facto = A Desensitivity facto = = A Sensitivit y AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

9 : 9 : S - 09 (Pelis) Offline est Seies daf da Af A A 0.00 (0.) A 0. A Ans: (b) Case: I Conside D - OFF, D - ON I 0.5k.3 0 D oc 0 y KL oc I = 0 oc = I Fo D ON oc > 0.7 I > 0.7 I >.7 0 =.7 olts Case: III Conside D - OFF & D OFF oth diodes ae OFF if.3 < I <.7 Hee, I = 0 0 y KL oc I = 0 oc = I Fo D ON oc > 0.7 I > 0.7 I <.3 0 =.3 olts Case: II Conside D - ON, D - OFF I 0.5k D.7 I oc 0 I.7.3 Hence by cobining above thee cases, the input-output chaacteistics is Ans: (c) I 0 = I 03 = I ef I 04 = 3I ef I 0 = I ef Given that I 0 = 00 A I I ef = 0 = 00 A I 04 = 3I ef = 300 A.7 I Slope =.3.7 I AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

10 : 0 : lectonics & elecounication ngineeing 47. Ans: (d) Method- out M M Finding : M 0 = gs g gs (0A) 0 I I 0 eplace M by 0 I out M 0 I gs g gs 0 0 g gs 0 out I I 0 AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

11 : : S - 09 (Pelis) Offline est Seies KCL at output node: I I ggs 0 I g(0 I0) 0 I I 0 g g I out Method- Calculation of output esistance ( out ) ; ( in = 0) G gs g gs S D 0 I I I gs 0 g gs 0 0 I Hee, 0 g 0 gs gs gs 0I 0 gs 0I y KL I g I 0 0 gs 0 0I g gs 0 0I I g I I g out 0 0 g I 0 I 0 0 AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

12 : : lectonics & elecounication ngineeing AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

13 : 3 : S - 09 (Pelis) Offline est Seies 48. Ans: (a) A Af 0 A A 4 0 A Hf = H (A ) = = 5000 ad/sec 5. Ans: (d) ipple facto of powe supply is a easue of puity of powe output. 5. Ans: (d) Output fo ectifie L C C L Output 49. Ans: (c) CO : oltage acoss ase-collecto junction when eitte open CO = C open 0 0 = 70 0 = Ans: (d) in AC ngineeing Acadey I out = Z = = 7 C = in out = 5 7 = 8 I I Z L in Z I A 000A 7.3k out 7 IL A L 3.5k I I 0A [ I = I L ] 00 I Z = I I = = 980 A I Z =7.7 I L out (i) When actual load is connected, thee is a sall additional voltage dop. hus the diffeence between no load and full load voltage is educed. hus, voltage egulation is ipoved. (ii) leede esisto ipoves the filteing action by aintaining a iniu cuent though the choke (iii)when a bleede is not used and powe supply is switched off, the capacito etains its chage fo soe tie which is dangeous fo people woking with equipent. his high voltage dischages though bleede. 53. Ans: (b) In class Fo low signal voltage, Ic = 0 Coss- ove distotion poble is thee In class A ven fo no signal, sall cuent flows Hence powe dawn is not zeo 54. Ans: (b) Monolithic ICs offe low powe ating. So, stateent(iii) is wong stateent. Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

14 : 4 : lectonics & elecounication ngineeing 55. Ans: (a) (A) hin and thick laye IC s ae also known as pinted fil cicuits because in thei anufactuing silk-sceen pinting techniques ae used. () Hybid IC is cobination of nube of onolithic IC s. hese ae widely used fo high powe audio aplifie applications. (C) Linea IC s input and output elationship is linea. So used in aplifies, oscillatos etc (D) Digital IC s find wide applications in coputes and logic cicuits. 56. Ans: (a) =, i.e. base cuents ae zeo fo both Q & Q. So, the cicuit can be edawn as below, = 5 ( k) = 3 = 0.7 = 0.7 = 0.7 = =.3 = 0.7 = = 0.7 AC ngineeing Acadey 0A k CC Q C Q A C.7 = 0.7 Given that C =.7 C =.7 C =.7 = = 3.5 C 57. Ans: (b) I I 0 I CC CC Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad CC I I CC ( (I ) IC di dic S di dic S = 9.7 I C I ) C Ans: (d) he node at which input is given is sae as the feedback taken node. So shunt at input. If the feedback node is at one node and output taken fo anothe node, then it is said to be Seies at output.

15 : 5 : S - 09 (Pelis) Offline est Seies 59. Ans: (c) W id Kn GS L At i D = A W K L At i D = 9A W 9 K L n 9 n..()..() = 33 = = = 4 = 0.5 = GS = < So = 0.5 not possible = 60. Ans: (d) K s - 0K KCL S 00 K 0K 0 S 0 = S = = S = 00 = S 0 S 6. Ans: (d) SL L = = SL L F A= ; A = fo sustained oscillations) F L L F 5H k H F = 5k 6. Ans: (b). In 555 ties, theshold level is CC 3. ve tigge pulse is equied to change the output state in onostable ultivibato 3. One of the application of 555 in Astable odes FSK geneation 4. In Schitt tigge using 555 tie, UP = CC and LP = CC Ans: (b) Step (): ffective voltage applied at the inveting input teinal of op-ap 0k = () 0k 0k Step (): Fo the output of op-ap to be positive, the input at non-inveting teinal of op-ap should of oe than 6, i.e i > () Step (3): In the op-ap cicuit shown, fo the LD to tun ON, the output of op-ap should be positive. o get this ve output, i > 6 AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

16 : 6 : lectonics & elecounication ngineeing 64. Ans: (c) In the cicuit a half wave ectifie and a diffeentiato is cascaded when we give a squae-wave input to the half-wave ectifie, the output voltage 0 is shown below. he diffeentiato, the voltage a is to be diffeentiate and esults a output voltage, 0 which is ipulse (spikes) wave as shown above. 65. Ans: (c) oltage at non-inveting teinal p = P i a f 3 f f f 4 f f 0 f t t t 66. Ans: (b) JF has low esistance ( GS ) copaed to MOSF. So, the stateent (a) is wong. g of JF is aiu when GS = 0 I g g D I DSS I g 0 D GS GS P I DSS P P GS he above g is aiu when GS = 0 lbes-moll odel can be used fo both npn and pnp tansistos Usually F has infinite esistance between gate and souce 67. Ans: (b) he Gate can be self aligned to souce and dain in a MOSF with polysilicon gate. So it is pefeed than a MOSF with Aluiniu gate. Oveload and peak cuent handling capability is high 68. Ans: (d) Positive cycle the fist capacito chages to peak of 5v, Duing negative cycle D is, D is F capacito chages to 0 in the polaity shown heefoe = 0 GS P 0 AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

17 : 7 : S - 09 (Pelis) Offline est Seies 69. Ans: (c) evese ecovey tie (t ): 7. Ans: (b) Deultiplee using AND gates I D Change of state (ONOFF) A F(input) I F t applied at t =t o (desied state) t O 0 I t s t t t = t s t t O t O Whee t : evese ecovey tie t s : Stoage tie t t : tansition tie Diffusion capacitance eist in fowad biasegion and tansition capacitance eist in evese-bias egion. 70. Ans: (c) () he coss ove distotion is eliinated in a push-pull aplifie by poviding a sall fowad bias to the tansisto. () he haonic distotion efes to the non-sinusoidal natue of a peiodic wave fo and it defined at peiodic fequency and ultiple of that fequency. he stateent() and () ae coect stateents. O 3 Whee A, ae contol inputs O 0, O,O, O 3 ae outputs A deultiplee can be used as decode and deultiplee can be built by AND gates. Stateent (I) is tue. Stateent (II) is also tue, but not giving coect eplanation fo I 7. Ans: (b) In I L logic all individual tansistos of L ae eplaced by ulti collecto tansistos. oth stateents ae tue but stateent(ii) is not giving coect eplanation fo stateent(i). 73. Ans: (d) DMA is a pocess whee the data is tansfeed between two peipheals diectly without the involveent of the icopocesso. stateent (I) is false & stateent (II) is tue AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally

18 74. Ans: (d) locking oscillato is a elaation oscillato which geneates shot tie duation pulse using a tansisto as an active device. Stateent (I) is false. locking oscillatos ae used to geneate pulses of lage peak powe. Stateent (II) is tue. 75. Ans: (d) Zene egulato has low efficiency fo heavy load cuents as thee is a consideable powe loss in. out = Z I Z Z I he egulato is used only when thee ae sall vaiations in load cuent and input voltage. Stateent (I) is wong and stateent (II) is tue. : 8 : lectonics & elecounication ngineeing AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada izag iupati Kolkata Ahedabad

19 : 9 : S - 09 (Pelis) Offline est Seies AC ngineeing Acadey Hydeabad Delhi hopal Pune hubaneswa Lucknow Patna engaluu Chennai ijayawada Kolkata izag iupati Kukatpally