Power efficiency and optimum load formulas on RF rectifiers featuring flow-angle equations

Transcription

1 LETTE IEICE Electonics Expess, Vol.10, No.11, 1 9 Powe efficiency and optimum load fomulas on F ectifies featuing flow-angle equations Takashi Ohia a) Toyohashi Univesity of Technology, 1 1 Hibaigaoka, Tempaku, Toyohashi Japan a) ohia@tut.jp Abstact: This pape consides thee pais of cicuit schemes fo F ectification. Given finite available powe fom F souce and load esistance, we fomulate DC output powe and efficiency of each scheme. esultant fomulas find that load-to-souce esistance atio / dominates the cicuit pefomance. Maximum efficiency eaches 81.1% at / = 1 fo single-diode half wave ectifies. It also eaches 92.3% fo multiple-diode full wave ones at / = in bidge with capacito, in bidge with inducto, in double-voltage, and in double-cuent topologies. Keywods: ectifie, powe efficiency, optimum load, flow angle Classification: Micowave and millimete wave devices, cicuits, and systems efeences [1] M. Saito and K. Aaki: Koea Japan Micowave Confeence (2011) 58. [2] T. Saen, K. Itoh, S. Betsudan, S. Makino, T. Hiota, K. Noguchi and M. Shimozawa: IEEE Int. Micowave Wokshop Seies on Innovative Wieless Powe Tansmission (2011) Intoduction Indeed the ectifie theoy looks well-matued, cicuit enginees often need numeical simulatos in designing adio-fequency (F) ectifies. Actually, they have to exploe possible topologies and find thei optimum load esistance o input matching impedance. This is because F ectifies ae expected to squeeze DC enegy as much as possible fom given finite F enegy. Unlike low-fequency powe electonics, this equiement is especially cucial fo enegy havesting and wieless powe tansfe applications [1, 2]. This pape consides F ectifying schemes in single-seies, single-shunt, bidge, double-voltage, and double-cuent topologies. Fomulating the cicuit behavio fom the aspect of diode s flow angle, we deive the optimum load 1

2 condition and maximum available powe efficiency fo each topology. 2 F-to-DC powe convete Conside an F ectifie a block having an F input pot and a DC output pot as shown in Fig. 1. The F souce with finite available powe is epesented by time-sinusoidal voltage souce v s (t) =v s cos ωt, v s = 8, ω =2π/T (1) with equivalent intenal esistance in seies [1, 2]. The ectifie eceives the F powe in educed voltage v 1 (t) =v s cos ωt i 1 (t) (2) at its input pot, whee i 1 (t) stands fo cuent fom the souce. On the othe side, esistance simply epesents the output load since output voltage v o and cuent i o consist of only thei DC components thanks to an ideal smoothe we assume inside of the block. Output DC voltage v o,powep o, and powe efficiency η ae theefoe witten as v o = i o, P o = v o i o, η = P o = 8 v o i o (3) v 2 s Fig. 1. Geneal F-to-DC convesion scheme 3 Single-seies topology Conside a simple scheme fo F ectification employing single diode D as shown in Fig. 2. Inducto L makes a DC gound path fom the diode to the load,aswellaschokesi 2 against F cuent. Namely suppose ωl, to avoid any F effect on the input pot. Capacito C makes an F gound path fom the souce to the diode, as well as smoothes out the output ipple. Suppose in the same way 1/ωC, to keep output voltage v o constant enoughatleastovetimepeiodt. Fotime-invaiantload, output cuent Fig. 2. Single-seies F ectifie 2

3 i o also keeps constant. Fo simplicity, assume a pefect one-way switch model fo diode D. Note that D may epesent a synchonized switching powe tansisto. Let us focus on diode cuent i d to satisfy Kichhoff s cuent law i 1 (t)+i 2 = i d (t) =i 3 (t)+i o (4) at any time in the peiod. Note again that i 2 and i o ae constant as descibed above. Fom Eqs. (2) and (4), we get wavefoms in two states (i) D = ON v 1 (t) =v o, i 1 (t) = 1 (v s cos ωt v o ) t 1 <t<t 1 (ii) D = OFF i 1 (t) = i 2, v 1 (t) =v s cos ωt + i 2 t 1 <t<t t 1 (5) which ae plotted in Fig. 3. While the F souce povides a pue sinusoidal wave as v s (t), it is distoted at once fo the ectifie input as v 1 (t). This is due to the stong smoothing capacito duing when the diode makes ON. Integating Eq. (2) ove a peiod, we get. v 1 (t)dt = v s cos ωtdt i 1 (t)dt (6) Fig. 3. Voltage time wavefoms and paametes behavio as / inceases whee the cicula symbol on integals implies one cycle of t. The left-hand side makes zeo as v 1 (t) has no DC component acoss an inducto. The fist tem of ight-hand side also tivially vanishes. Since >0, Eq. (6) esults in v 1 (t)dt =0, i 1 (t)dt =0 (7) We call them cyclostationay conditions. Integal of Eq. (4) fo a cycle gives i 1 (t)dt + i 2 T = i d (t)dt = i 3 (t)dt + i o T (8) As i 3 (t) has only displacement cuent acoss a capacito, its one-cycle integal vanishes again. Since T>0, Eq. (8) with (4) esults in i o = i 2 = 1 i d (t)dt, i 1 (t) =i 3 (t) =i d (t) 1 i d (t)dt (9) T T Substituting Eq. (5) into Eq. (7) with integal fo a cycle of ON and OFF states pat by pat, we get 3

4 t1 T t1 v o dt + (v s cos ωt + i 2 )dt = 0 (10) t 1 t 1 emembeing i o = i 2, v o = i o,andωt =2π, we can ewite Eq. (10) as v s sin φ = {φ +(π φ)}i o, φ = ωt 1 (11) Voltage and cuent wavefom ae geneally continuous at any time and any node in the cicuit. This is tue even with a switching diode because it tansits between ON and OFF states always via its zeo-voltage and -cuent oigin. Imposing such continuity at tansient time t 1 upon Eq. (5), we get v s cos φ = v o i 2 =( )i o, φ = ωt 1 (12) The quotient of Eqs. (11) to (12) yields tan φ φ = o sin φ +(π φ)cosφ =, 0 <φ<π (13) sin φ φ cos φ whee 2φ is called flow angle anging fom 0 to 2π. Feeding Eq. (13) back into (12), we finally obtain DC output cuent and voltage i o = v s cos φ = v s (sin φ φ cos φ) (14) v o = i o = v s (sin φ φ cos φ) =v s {sin φ +(π φ)cosφ} (15) π They poduce output powe P o = i o v o associated with efficiency η = P o = 8 π 2 (sin φ φ cos φ){sin φ +(π φ)cosφ} 8 π 2 sin3 φ (16) These fomulas enable us to find how φ, v o, i o,andη behave as / inceases as shown in Table in Fig. 3. In paticula, η eaches its maximum = 8 π % at =1 o φ = π 2 (17) This condition should be igoously called half-wave ectification. The est 18.9% of input powe dissipates in distotion. It means pospective oom at most fo efficiency impovement by eactive temination against hamonics. 4 Single-shunt topology Thanks to the duality theoem, we can chaacteize the single-shunt topology shown in Fig. 4 by intechanging voltage/cuent, ON/OFF, L/C, and / Fig. 4. Single-shunt F ectifie 4

5 fom fomulas fo the single-seies one. Begin with Eqs. (4) and (5) eplaced by v 1 (t)+v C = v d (t) =v L (t)+v o (18) (i) D = ON v 1 (t) = v o, i 1 (t) = 1 (v s cos ωt + v o ) t 1 <t<t 1 (ii) D = OFF i 1 (t) =i o, v 1 (t) =v s cos ωt i o t 1 <t<t t 1 (19) whee v C and v L (t) stand fo voltages on capacito C and inducto L. Then imposing the cyclostationay condition and wavefom continuity descibed in the pevious section, we each tan φ φ = v o = i o = v s cos φ π o = sin φ φ cos φ, 0 <φ<π (20) sin φ +(π φ)cosφ = v s (sin φ φ cos φ) (21) π i o = v s π (sin φ φ cos φ) = v s {sin φ +(π φ)cosφ} (22) The powe pefomance afte all emains exactly the same as descibed in Eqs. (16) and (17). This esult agees with the duality theoem whee impedance tems ae all evesed while powe tems totally keep unchanged. 5 Bidge topology Figue 5 shows a widely used topology fo full-wave ectification. Unlike single-diode ones, we need a eacto only at the output pot. This is because DC cuents geneated fom two banches cancel each othe at the input pot. Capacito C acts not only fo output smoothing in a passive fashion, but woks fo powe efficiency enhancement. Fig. 5. Bidge F ectifie Since the cicuit has two pais of diodes, it looks complicated to fomulate the wavefoms. We actually conside fou sequential states (i) D 1,3 = ON, D 2,4 =OFF v o <v s (t) t 1 <t<t 1 (ii) D 1,2,3,4 =OFF v o <v s (t) <v o t 1 <t<t/2 t 1 (iii) D 1,3 = OFF, D 2,4 =ON v s (t) < v o T/2 t 1 <t<t/2+t 1 (iv) D 1,2,3,4 =OFF v o <v s (t) <v o T/2+t 1 <t<t t 1 continuously taking place synchonized to F sinusoidal stimulus v s (t) with peiod T. Note that the two pais cannot make ON at the same time. Defining φ =2πt 1 /T (0 <φ<π/2), we call 4φ flow angle anging fom 0 to 2π. 5

6 Fom Eqs. (1), (2), the above fou diode states, and wavefom continuity at t 1, we get voltage and cuent v s cos φ fo (i) v 1 (t) = v s cos ωt fo (ii) (iv), v s cos φ fo (iii) v s (cos ωt cos φ) fo (i) i 1 (t) = 0 fo (ii) (iv) (23) v s (cos ωt +cosφ) fo (iii) at the input pot. Imposing the cyclostationay condition fo capacito cuent, we obtain flow-angle equation and output pefomance fomulas tan φ φ = 2, 0 <φ<π 2, v o = v s cos φ, i o = 2v s (sin φ φ cos φ) (24) η = P o = 16 π (sin φ φ cos φ)cosφ = 8 (sin 2φ φ φ cos 2φ) (25) π To find optimum flow angle φ opt,solvedη/dφ = 0 on Eq. (25). We finally each tan φ opt =2φ opt o φ opt (26) 92.3% at = π (27) 2φ opt This is 11.2 points highe than pedecesso s study [2] that deduced η max = 81.1% without employing C. We theefoe conclude that C successfully squeezes such amount of ectified enegy fom diodes and bings it to the load. Facto implies that C acts to incease DC output-matching o equivalently decease F input-matching impedance by 34.7%. Imagine an altenative cicuit in dual to the bidge shown in Fig. 5. This is done by just eplacing the shunt smoothing capacito by a seies choke inducto at the output pot. By this eplacement, the fou states become (i) D 1,3 = ON, D 2,4 =OFF i o <v s (t) t 1 <t<t 1 (ii) D 1,2,3,4 =ON i o <v s (t) <i o t 1 <t<t/2 t 1 (iii) D 1,3 = OFF, D 2,4 =ON v s (t) < i o T/2 t 1 <t<t/2+t 1 (iv) D 1,2,3,4 =ON i o <v s (t) <i o T/2+t 1 <t<t t 1 Due to the inducto loaded in seies, the two pais make simultaneous ON duing (ii) and (iv), but not OFF at the same time. Though the same opeation, we obtain tan φ φ = π 2, 0 <φ<π 2,v o = 2v s π (sin φ φ cos φ), i o = v s 92.3% at = 2φ opt π cos φ (28) (29) Note / optimum be invese of that appeaed in Eq. (27). This is mathematically easonable fo duality. In physical effects, the choke inducto enhances the cuent and saves the voltage in its smoothing pocess. 6

7 6 Double-voltage topology Figue 6 shows a ectifie employing two diodes and two capacitos. A half cycle of input sinusoidal voltage suges though one diode, then the opposite half cycle does though anothe in tun. epeating such a cycle, the voltage sums up double and chage the final capacito. Exactly speaking, thee ae intevals between the two half cycles when the two diodes make simultaneously OFF. This scenaio can be explained by fou sequential states Fig. 6. Double-voltage F ectifie (i) D 1 = OFF, D 2 =ON v o < 2v s (t) t 1 <t<t 1 (ii) D 1,2 =OFF v o < 2v s (t) <v o t 1 <t<t/2 t 1 (iii) D 1 =ON,D 2 =OFF 2v s (t) < v o T/2 t 1 <t<t/2+t 1 (iv) D 1,2 =OFF v o < 2v s (t) <v o T/2+t 1 <t<t t 1 We define flow angle again as same as pevious. Thanks to the continuity of the voltage and cuent wavefoms at the input pot, they ae exactly same as Eq. (23). Imposing the cyclostationay condition fo capacitos cuent, we obtain flow-angle equation and output pefomance fomulas tan φ φ = 2, 0 <φ<π 2, v o =2v s cos φ, i o = v s (sin φ φ cos φ) (30) 92.3% at = 2π (31) φ opt whee η and φ opt come again fom Eqs. (25) and (26). The optimum load esistance becomes fou times highe than that fo the fist bidge topology. This esult agees with what we pedicted i.e. double-voltage and half-cuent output fom the same input powe. 7 Double-cuent topology The duality theoem enables us again to deive the fomulas fo the doublecuent ectifie shown in Fig. 7. We can stat by intechanging ON/OFF states, voltage/cuent, and souce/load. The fou states become (i) D 1 = ON, D 2 =OFF i o < 2v s (t) t 1 <t<t 1 (ii) D 1,2 =ON i o < 2v s (t) <i o t 1 <t<t/2 t 1 (iii) D 1 = OFF, D 2 =ON 2v s (t) < i o T/2 t 1 <t<t/2+t 1 (iv) D 1,2 =ON i o < 2v s (t) <i o T/2+t 1 <t<t t 1 We define flow angle as same as pevious. The voltage and cuent wavefoms become 7

8 Fig. 7. Double-cuent F ectifie v s (cos ωt cos φ) fo (i) v 1 (t) = 0 fo (ii) (iv) v s (cos ωt +cosφ) fo (iii) v s cos φ fo (i) v s i 1 (t) = cos ωt fo (ii) (iv) v s cos φ fo (iii), (32) at the input pot. Imposing the cyclostationay condition fo inductos voltage, we obtain flow-angle equation and output pefomance fomulas tan φ φ = 2, 0 <φ<π 2, v o = v s π (sin φ φ cos φ), i o = 2v s cos φ (33) 92.3% at = φ opt 2π (34) whee η and φ opt come ove again fom Eqs. (25) and (26). It is woth emaking that the optimum load esistance becomes one fouth of Eq. (29), and invese of Eq. (31). These elations sound complicated but ae conveniently tabulated below. 8 Conclusion The optimum load and maximum powe efficiency fomulas have been suc- Table I. F ectifies theoetical popeties at a glance 8

9 cessfully deived fo F ectifies in thee pais of topologies. The esistance atio and flow angle play cucial oles to fomulate the ectifying behavios. The esultant fomulas summaized in Table I give a clea vista to cicuit designes in F powe electonics. This is much moe elegant and insightful than seeking the solution by epeating nonlinea time-domain o hamonicbalance simulations. The theoy can be even extended to fomulation of tiple- and highe-ode multiple voltage o cuent topologies. 9