Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems

Transcription

1 Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems Weixun Wang and Prabhat Mishra Department of Computer and Information Science and Engineering University of Florida, Gainesville, FL Abstract System optimization techniques are widely used to improve energy efficiency as well as overall performance. Dynamic voltage scaling (DVS) is acknowledged to be successful in reducing processor energy consumption. Due to the increasing significance of the memory subsystem s energy consumption, dynamic cache reconfiguration (DCR) techniques are recently proposed at the aim of saving cache subsystem s energy consumption. As the manufacturing technology scales into the order of nanometers, leakage current, both in the processor and cache subsystem, becomes a significant contributor in the overall power dissipation. In this paper, we efficiently integrate processor voltage scaling and cache reconfiguration together that is aware of leakage power to minimize overall system energy consumption. Experimental results demonstrate that our approach outperforms existing techniques by on average 12-23%. I. INTRODUCTION Energy conservation is a primary optimization objective in embedded systems design since these systems are generally limited by battery lifetime. Various low-power techniques focus on different components in the system. Dynamic voltage scaling (DVS) [1] of the processor takes the advantage of the fact that linear reduction in the supply voltage can quadratically reduce the power consumption while linearly slows down the frequency. At the same time, memory hierarchy, especially cache subsystem, has become comparable to the processor with respect to the contribution in overall energy consumption [2]. Dynamic cache reconfiguration (DCR) offers the ability to tune the cache configuration parameters at runtime to meet application s unique requirement so that significant amount of memory subsystem energy consumption can be saved [3]. It will be promising to use both DVS and DCR to conserve both processor and memory energy dissipations. Real-time embedded systems bring particular design and optimization considerations in order to satisfy the deadline constraints imposed on each task. In real-time systems, all tasks have to finish execution before their deadlines to ensure correct system behavior. Earliest Deadline First (EDF) [4], which employs a dynamic priority scheme, is the most commonly used scheduling algorithm in the real-time research community. Under EDF, a preemptive task set is said to be schedulable as long as the system utilization rate is not more than 1 [5]. Essentially, DVS in real-time systems slows This work was partially supported by NSF grant CCF down the processor, thus saves power/energy, at the cost of stretched task execution time. On the other hand, applying DCR in such systems may lead to similar effects so that it needs to be done in a controlled way. While existing research works exploit them separately, our proposed research efficiently employs both DVS and DCR simultaneously to reduce overall energy consumption, in hard real-time systems with preemptive periodic task sets. In the last decade, we have observed a continuous CMOS device scaling process in which higher transistor density and smaller device dimension lead to increasing leakage (static) power consumption. This is mainly due to the proportionally reduced threshold voltage level with the supply voltage. Lower threshold voltage results in larger leakage current which mainly consists of subthreshold current [6] and reverse bias junction current [7]. Study has shown that leakage power is increased by five times in each technology generation [8] and can exceed above half of the total power dissipation [9]. On-chip caches nowadays contribute a significant share of the system leakage power. Static energy is projected to account for near 70% of the cache subsystem s budget in 70nm technology [9]. Furthermore, higher temperature have adverse impact on leakage power in both processor [10] and cache [11]. Therefore, decisions should be made judiciously on whether slowing down the system to save dynamic power or switching the system to sleep mode to reduce static power. While existing techniques try to control the leakage power along with DVS [12], extra consideration needs to be taken when DCR is also employed as described in this paper. The rest of the paper is organized as follows. Related works are discussed in Section II. Section III presents the system model of our work. Our leakage-aware voltage scaling and cache reconfiguration technique is described in Section IV. Section V demonstrates our experimental results. Finally, Section VI concludes the paper. II. RELATED WORK A great deal of research work exists on dynamic voltage scaling in real-time systems. A lot of them focus on minimizing dynamic power consumption and ignoring the static portion by slowing down the processor as long as possible through various directions including task scheduling,

2 voltage selection and worst-case execution time estimation [13][14][15]. Meanwhile, a number of existing works pay attention to control processor leakage power in real-time systems [16][12][17][18]. Lee et al. [16] propose a scheduling algorithm to minimize leakage energy consumption by procrastinating currently ready tasks to enlarge system idle periods based on a non-dvs platform. Jejurikar et al. [12] present a leakage-aware DVS scheme which does not allow to slow down the processor speed below a certain level called critical speed to avoid growing static energy consumption to compensate the reduction in dynamic energy. They also propose a procrastination scheduling technique to maximize processor idle intervals. Chen et al. [17] address the same problem in a rate-monotone scheduling system. They also propose a procrastination scheme based on energy consumption evaluation [18]. However, none of the above techniques considers dynamic cache reconfiguration. Cache reconfiguration has drawn considerable amount of research efforts in both general-purpose [19] and real-time [20][21] systems. Reconfigurable cache architectures are proposed in [2][22]. Wang et al. [20] employed DCR in realtime systems by dynamically utilizing static profiling information to tune the cache configuration in order to achieve significant energy savings. Micro-architecture level techniques are proposed at the aim of saving leakage energy in cache subsystem by switching unused cache sub-arrays into lowpower mode [23][24]. Chi et al. [25] applied these techniques in hard real-time systems. However, none of these approaches takes processor voltage into consideration. Nacul et al. [26] presented preliminary results to demonstrate the benefit of combining DVS and DCR together in real-time systems but they did not consider leakage power which may make their solution inferior when leakage energy dominates the total consumption. Our proposed research in this paper integrates DVS and DCR in hard real-time systems to reduce both dynamic and static energy consumption. We take a step forward by examining the correlation between the energy models of processor and cache subsystem. We statically assign voltage level and cache configuration to each task based on slack allocation method and procrastinate task execution at runtime to shutdown the processor/cache when beneficial to achieve more energy savings. Extensive experiments show that our approach can result on average 46% energy savings compared to DVSonly systems and up to 12-23% extra savings compared to leakage-oblivious DVS + DCR technique [26]. III. SYSTEM MODEL In this section, we describe our system model including the task model and the energy model. We assume that DVS and DCR are available in the target system. Specifically, we have: A voltage scalable processor which supports h different voltage levels V{v 1,v 2,...,v h }. A highly configurable cache architecture, with reconfigurable parameters including cache size, line size and associativity, which can be tuned to l different configurations C{c 1,c 2,...,c l }. A. Task Model If each task is uniformly assigned one voltage level and one cache configuration throughout all its instances, we have: A set of m independent periodic tasks T{τ 1,τ 2,...,τ m }. Each task τ i T has known period and deadline d i. Task τ i T has energy consumption and execution time E i (v j,c k ) and T i (v j,c k ) with voltage level v j V and cache configuration c k C, respectively. We assume that task deadlines are equal to their periods and the task set is schedulable by EDF scheduler under the highest voltage level and largest cache configuration. Let P denote the task set s hyper-period (equal to the least common multiple of all tasks periods). j i and k i represent the indices of selected voltage level and cache configuration for task τ i, respectively. Our objective can be stated as: subject to, B. Energy Model min(e = m i=1 P E i (v ji,c ki )) (1) m T i (v ji,c ki ) U EDF (2) i=1 1) Processor Energy Model: Since short circuit power is negligible [27], the energy consumed in a processor mainly comes from dynamic and static power. The dynamic power can be presented as: P dyn proc = C e f f V 2 dd f (3) where C e f f is the total effective switching capacitance of the processor, V dd is the supply voltage level and f is the operating frequency. We adapt the analytical processor energy model from [7], whose accuracy has been verified with SPICE simulation. The threshold voltage V th can be presented as: V th = V th1 K 1 V dd K 2 V bs (4) where V th1, K 1, K 2 are all constants and V bs represents the body bias voltage. As mentioned in Section I, static current mainly consists of the subthreshold current I subth and the reverse bias junction current I j. Hence, the static power is given by: P sta proc = V dd I subth + V bs I j (5) where I j is approximated as a constant and I subth can be calculated by: I subth = K 3 e K 4V dd e K 5V bs (6) where K 3, K4 and K 5 are constant parameters. Obviously, to avoid junction leakage power overriding the gain in lowering I subth, V bs has to be constrained (between 0 and -1V). Let Pproc on be the intrinsic energy needed for keeping the processor on (idle energy). The processor power consumption can be computed as: P proc = P dyn proc + P sta proc + P on proc (7)

3 Total Energy (nj) Total Energy (nj) The cycle length, t cycle, is given by a modified alpha power model which is verified by SPICE simulation: 6.0E E+06 EprocDyn EprocSta EprocOn Eproc Critical Speed t cycle = L d K 6 (V dd Vth) α (8) where K 6 is a constant. In this paper, we estimate L d to be the average logic depth of all instructions critical path in the processor. Table I lists the constants for 70nm technology. Let CC denote the number of clock cycles executed, the processor energy consumption becomes: E proc = P proc CC t cycle (9) TABLE I CONSTANTS FOR 70NM TECHNOLOGY Const Value Const Value Const Value K K V th K K I j K V dd [0.5,1.0] C e f f K V bs [ 1.0,0.0] L d 37 K α 1.5 L g E E E E E V dd (V) Fig. 1. Processor energy consumption E proc for executing cjpeg: E procdyn is the dynamic energy, E procsta is the static energy and E procon is the intrinsic energy needed to keep processor on. 1.6E E E E E+06 EprocDyn EprocSta EprocOn Eproc EcacheDyn EcacheSta Ecache Etotal Critical Speed 6.0E+06 2) Cache Energy Model: Cache energy consumption also consists of dynamic energy E dyn cache and static energy Esta cache : E cache = E dyn cache + Esta cache (10) The number of cache accesses num accesses, cache misses num misses and clock cycles CC are obtained from simulation using SimpleScalar [28] for any given task and cache configuration. Let E access and E miss denote the energy consumed per cache access and miss, respectively. Therefore, we have: E dyn cache = num accesses E access + num misses E miss (11) E miss = E o f f chip access + E µp stall + E block f ill (12) E sta cache = Psta cache CC t cycle (13) where E o f f chip access is the energy required for fetching data from off-chip memory, E µp stall is the energy consumed when the processor is stalled due to cache miss, E block f ill is for cache block refilling after a miss and Pcache sta is the static power consumption of cache. We collect E access, Pcache sta and E block f ill from CACTI [29] for all cache configurations and adopt numbers for others from [22]. IV. LEAKAGE-AWARE DVS AND DCR Our approach addresses three major challenges including profiling information analysis to determine the critical speed, configuration selection and task procrastination to significantly reduce overall energy consumption while meeting task deadlines. This section describes each of these steps in detail. 4.0E E E V dd (V) Fig. 2. Overall system energy consumption E total of the processor and cache subsystem (configured to 16KB,32B,2-way) for executing cjpeg: E cachedyn and E cachesta are the dynamic and static cache consumption, respectively. A. Critical Speed The critical speed for processor voltage scaling defines a point which the processor speed cannot be slowed down below otherwise DVS will no longer be beneficial [12]. The dynamic power consumption of processors, which is exclusively considered in traditional DVS, is usually a convex and increasing function of the operating frequency. However, since lower processor speed stretches the task execution time which leads to higher static energy consumption, the energy consumed per cycle in the processor will start increasing due to further slowdown. By taking DCR into consideration, we find that cache configuration has significant impact on the critical speed with respect to the overall system energy consumption. Note that as described in Section III-B, there exists strong correlation between the energy models of the processor and cache subsystem. Since different cache configuration leads to different miss ratio and miss penalty cycles, the number of clock cycles (CC) required to execute an application is decided by the cache configuration, which directly affects processor s energy consumption as shown in Equation (9). On other hand, the length of each clock cycle (t cycle ) and the energy consumed at the stalled processor during an off-chip access (E µp stall ) are determined by the processor frequency, which directly affects

4 Total Energy (nj) 2.0E E E E E E E E E E E V dd (V) 4096B_1W_16B 4096B_1W_32B 4096B_1W_64B 8192B_1W_16B 8192B_2W_16B 8192B_1W_32B 8192B_2W_32B 8192B_1W_64B 8192B_2W_64B 16384B_1W_16B 16384B_2W_16B 16384B_4W_16B 16384B_1W_32B 16384B_2W_32B 16384B_4W_32B 16384B_1W_64B 16384B_2W_64B 16384B_4W_64B Fig. 3. Total energy consumption across all cache configurations for executing cjpeg. cache energy consumption as shown in Equation (12) and (13). The former fact results in drastically varying processor energy consumption across different cache configurations. The later factor leads to faster critical speed compared to the DVSonly scenario. It is caused by the impact of increasing cache static power on the total static energy consumption when the processor is slowed down. Now we show a simple motivating example in which a single benchmark (cjpeg) is executed under all processor voltage levels. It can be observed that in Figure 1, when only processor energy is considered, the critical speed is achieved at V dd = 0.7V. However, as shown in Figure 2, with respect to the total amount of energy consumption, combining DVS and DCR increases the critical speed to around V dd = 0.85V. In fact, when DCR is applied, different cache configuration will lead to different critical speeds. B. Real-Time Scaling and Reconfiguration We define a configuration point as a pair of processor voltage level and cache configuration: (v j,c k ) where v j V and c k C. For each task, we can construct a profile table which consists of all possible configuration points as well as the corresponding total energy consumption and execution time. Clearly, all points with the voltage level lower than the critical speed are eliminated. Furthermore, non-beneficial configuration points, which is inferior in both energy and time compared to some other points, are also discarded. In other words, we only consider those Pareto-optimal tradeoff points. In fact, we observe that cache configurations behave quite consistently across different processor voltage levels as shown in Figure 3. The cache configuration favored by cjpeg, 8KB cache size with 32B line size and 2-way associativity, outperforms all the other configurations with respect to energy consumption. Although there are some exceptions that large cache configurations with highest voltage level could have slightly fast performance, they normally consume much more energy. Hence, we setup the profile table of each task consisting of its favored cache configurations with all the voltage levels higher than the critical speed. Any existing static slack allocation scheme can be employed in our approach. For each task, we assign the configuration point which is most energy efficient while does not stretch the task execution beyond the deadline decided by the allocated slack. As long as the slack allocation is safe, we can always ensure that the schedulability condition (Equation (2)) is satisfied. Any DVS algorithm that can generate optimal or approximated-optimal voltage assignment is also applicable though most of them are more computationally complex. In this paper, we use a heuristic algorithm motivated by the uniform constant slowdown scheme which is proved to be optimal in continuous voltage scaling [30]. The optimal common slowdown factor η is given by the system utilization rate. In our approach, we only consider a finite number of discrete configuration points as defined above. Therefore, for each task, we select the configuration point with minimum energy consumption but equal or shorter execution time compared to the one decided by the optimal slowdown factor. Note that we use each task s execution under the highest voltage in V and largest cache configuration in C as the base case (v base,c base ), which is used in the optimal slowdown factor calculation. Algorithm 1 illustrates our method. Algorithm 1 Configuration selection heuristic. T i (v base,c base ) η = m i=1 for all task τ i T do Ti bound = T i (v base,c base )/η; Assign τ i with (v ji,c ki ) which satisfied: 1) E i (v ji,c ki ) is the minimum; 2) T i (v ji,c ki ) T bound i ; end for return (v ji,c ki ), i [1,m] C. Procrastination To further control static energy consumption, it is beneficial to put the system into a sleep mode instead of keet idle since the static power could be lower by order-of-magnitude. As discussed in Section IV-A, taking cache into consideration leads to even faster critical speed compared to leakage-aware DVS-only scenario. In other words, for a same task set, the idle periods during which there is no active task are getting longer. However, bringing the system into sleep mode and vice versa requires certain amount of overhead in terms of energy and timing. In order to reduce the number of processor mode switches, we need to make the busy/idle periods as long as possible. One way to achieve this is to procrastinate task execution when no time constraint will be violated. We adapt the task procrastination algorithm from [16] into our EDF scheduler. We ensure that when the system gets shut down, there is no unfinished job in the system. This avoids cold start penalty being introduced since otherwise resumed task after wakeup has to refetch its data from memory. Hence, the shutdown overhead consists of the energy consumed for circuit logic recharging and dirty data flushing-back in the cache subsystem provided write-back policy is used. Algorithm 2 outlines our procrastination scheme. A timer is enabled when idle period starts and disabled when busy period starts. A newly arrived task during idle period will

5 Energy Normalized to DVS update the timer if it has earlier absolute deadline compared to the current earliest deadline. Upon timeout, all delayed ready tasks are executed in EDF order. Arriving tasks during busy period are allowed to preempt as normal EDF scheduler does. Note that time represents the current time instant and (v ji,c ki ) stands for the chosen configuration point for task τ i. Here, isearlier[i] records whether the current job of τ i s deadline is earlier than all the pending tasks in the system at the time when it arrives. Also, p r time p r and p r time are essentially the absolute deadline and the arrive time of τ i s current job. Algorithm 2 Task procrastination algorithm. isearlier[i] is initialized to be all false; Current earliest deadline of delayed jobs δ = 0; On arrival of a new job of task τ r : d r = p r time p r ; T i (v ji,c ki ) ; actutil = m i=1 if System is in sleep mode or is idle then if timer is disabled then timer = (1 actutil) p r ; δ = d r ; isearlier[r] = true; else if d r < δ then for all τ i in ready task queue do if isearlier[i] is true then delayed = delayed + time time p i ; timer = (1 actutil delayed) p r ; δ = d r ; isearlier[r] = true; end for V. EXPERIMENTS A. Experimental Setup To evaluate the effectiveness of our approach, we select benchmarks from MediaBench[31], MiBench[32] and EEMBC[33] to from four task sets with each consists of 5 to 8 tasks. While DVS techniques usually use synthetic tasks for evaluation, we choose real benchmarks so that cache behaviors of real applications can be revealed. Table II lists our task sets. Task Set 1 consists of tasks from MediaBench, Set 2 from EEMBC, Set 3 from MiBench and Set 4 is a mixture of all three suites. In Set 4, the two benchmarks from Sets Set 1 Set 2 Set 3 Set 4 TABLE II TASK SETS CONSISTING OF REAL BENCHMARKS. Tasks cjpeg, djpeg, mpeg2, pegwit, rawcaudio A2TIME01, BaseFP01, BITMNP01, RSPEED01, TBLOOK01 CRC32, susan, dijkstra, rijndael, adpcm, qsort, FFT, stringsearch cjpeg, rawdaudio, pegwit, A2TIME01, RSPEED01, pktflow, FFT, dijkstra EEMBC are set to iterate 100 times in order to make their size comparable with others. We adapt processor constants described in Section III-B from [12]: V bs = 0.7V, L d = 37, α = 1.5. We assume dirty data write back and circuit logic recharging penalty for shutdown to be 85µJ and 300µJ. Idle power for processor and cache subsystem are assumed to be 240mW and 36mW. System in sleep mode is assumed to consume 80µW of power. Hence, the shutdown threshold interval is 1.14ms and any interval whose length is shorter than the threshold will not lead to a shutdown. Energy model as well as the scheduling simulator are implemented in C++. B. Results We compare the following techniques across various system utilizations (from 0.1 to 0.9): DVS: Traditional DVS without DCR which assigns lowest voltage level to each task whenever possible. CS-DVS: Leakage-aware DVS without DCR which never assigns a processor speed level below the critical speed. CS-DVS-P: Leakage-aware DVS without DCR which employs task procrastination. DVS-DCR: DVS + DCR without leakage awareness which assigns the configuration point that best fits the slack. CS-DVS-DCR: Leakage-aware DVS + DCR which generates profile table in aware of leakage power and never assigns a configuration point below the critical speed. CS-DVS-DCR-P: Leakage-aware DVS + DCR which also employs task procrastination. Note that all the results are the average of all task sets and are normalized to DVS scenario. Figure 4 shows total energy consumption (processor + cache) of different approaches. The first observation is that generally, applying DVS + DCR outperforms DVS-only across all utilization rates by 43% on average. Our approach (cs-dvs- DCR) outperforms leakage-aware DVS (cs-dvs) by 46% on average. Above the critical speed point, as expected, leakageaware and leakage-oblivious approaches behave almost the same way since they are inclined to make similar decisions. But when the utilization ratio is low, cs-dvs-dcr achieves around 12-23% (up to 55%) energy savings compared to DVS-DCR. Figure 5 (a) shows the reduction in static energy DVS cs-dvs DVS-DCR cs-dvs-dcr Utilization Fig. 4. Total energy consumption of different approaches.

6 Energy Normalized to DVS-DCR Energy Normalized to cs-dvs-dcr Fig DVS-DCR cs-dvs-dcr cs-dvs-dcr cs-dvs-dcr-p Utilization Utilization (a) (b) Results: (a) Static energy consumption of DVS-DCR and cs-dvs-dcr; (b) Idle energy consumption of cs-dvs-dcr and cs-dvs-dcr-p consumption by using cs-dvs-dcr compared to DVS-DCR. Our approach gains averagely about 25% static energy savings across all utilizations and around 42% in low utilization cases. Note that with respect to total energy consumption, techniques with and without procrastination show similar energy savings. It is mainly due to the fact that the dynamic and static energy of real benchmarks we used dominates the idle energy consumption. To illustrate the effectiveness of procrastination, Figure 5 (b) shows the result in idle energy savings. It can be observed that around 10-40% savings can be achieved across all utilization rates by using cs-dvs-dcr-p. VI. CONCLUSION Leakage power can adversely impact any system energy optimization techniques including both dynamic voltage scaling and cache reconfiguration. Employing both DVS and DCR together can lead to greater system energy savings than using them independently. In this paper, we presented an efficient approach to integrate DVS and DCR that is aware of leakage power. We focus on reducing both dynamic and static overall energy consumption. We also integrate task procrastination to further save the energy consumption when the system is idle. Our approach is shown to be superior than both leakage-aware DVS techniques by around 46% and outperform leakageoblivious DVS + DCR techniques by up to 42%. REFERENCES [1] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava, Power optimization of variable-voltage core-based systems IEEE TCAD, vol. 18, pp , [2] A. Malik et al., A low power unified cache architecture providing power and performance flexibility ISLPED, [3] D. H. Albonesi, Selective cache ways: On-demand cache resource allocation Micro, [4] G. Buttazzo, Hard Real-Time Computing Systems. Kluwer, [5] J. Liu, Real-Time Systems. Prentice Hall, [6] J. A. Butts et al., A static power model for architects Micro, [7] S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads ICCAD, [8] S. Borkar, Design challenges of technology scaling Micro, [9] N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, Leakage current: Moore s law meets static power Computer, vol. 36, no. 12, pp , [10] L. Yuan, S. Leventhal, and G. Qu, Temperature-aware leakage minimization technique for real-time systems ICCAD, [11] H. Noori et al., The effect of temperature on cache size tuning for low energy embedded systems GLSVLSI, [12] R. Jejurikar, C. Pereira, and R. K. Gupta, Leakage aware dynamic voltage scaling for real-time embedded systems DAC, [13] R. Jejurikar and R. Gupta, Energy-aware task scheduling with task synchronization for embedded real-time systems IEEE TCAD, vol. 25, pp , [14] S. Zhang, K. Chatha, and G. Konjevod, Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules ISLPED, [15] S. Oh, J. Kim, S. Kim, and C. Kyung, Task partitioning algorithm for intra-task dynamic voltage scaling ISCAS, [16] Y.-H. Lee, K. Reddy, and C. Krishna, Scheduling techniques for reducing leakage power in hard real-time systems ECRTS, [17] J.-J. Chen and T.-W. Kuo, Procrastination for leakage-aware ratemonotonic scheduling on a dynamic voltage scaling processor LCTES, [18] J.-J. Chen and T.-W. Kuo, Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems ICCAD, [19] A. Gordon-Ross and F. Vahid, A self-tuning configurable cache DAC, [20] W. Wang, P. Mishra, and A. Gordon-Ross, Sacr: Scheduling-aware cache reconfiguration for real-time embedded systems in VLSI Design, [21] W. Wang and P. Mishra, Dynamic reconfiguration of two-level caches in soft real-time embedded systems ISVLSI, [22] C. Zhang, F. Vahid, and W. Najjar, A highly configurable cache for low energy embedded systems ACM TECS, vol. 6, pp , [23] M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories ISLPED, [24] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction imicro, [25] J.-W. Chi, C.-L. Yang, Y.-J. Chen, and J.-J. Chen, Cache leakage control mechanism for hard real-time systems CASES, [26] A. C. Nacul and T. Givargis, Dynamic voltage and cache reconfiguration for low power DATE, [27] H. J. M. Veendrick, Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits IEEE Journal of Solid-State Circuits, vol. 19, no. 4, pp , Aug [28] D. Burger, T. M. Austin, and S. Bennett, Evaluating future microprocessors: The simplescalar tool set University of Wisconsin-Madison, Tech. Rep., [29] CACTI, CACTI, HP Labs, CACTI 4.2, [30] H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, Dynamic and aggressive scheduling techniques for power-aware real-time systems in RTSS, [31] C. Lee, M. Potkonjak, and W. H. Mangione-smith, Mediabench: A tool for evaluating and synthesizing multimedia and communications systems Micro, [32] M. Guthaus, J. Ringenberg, D.Ernest, T. Austin, T. Mudge, and R. Brown, Mibench: A free, commercially representative embedded benchmark suite WWC, [33] EEMBC, EEMBC, The Embedded Microprocessor Benchmark Consortium,