AON7 3V PChannel MOSFET General Description Product Summary The AON7 uses advanced trench technology to provide excellent R DS(ON) with low gate charge. This device is ideal for load switch and battery protection applications. RoHS and HalogenFree Compliant V DS 3V I D (at V GS = V) A R DS(ON) (at V GS = V) < 6.mΩ R DS(ON) (at V GS = 6V) < 8.9mΩ % UIS Tested % R g Tested DFN 3.3x3.3 EP Top View Bottom Pin 3 Top View 8 7 6 D G S Absolute Maximum Ratings T A = C unless otherwise noted Parameter DrainSource Voltage Symbol V Maximum 3 GateSource Voltage Continuous Drain Current G Pulsed Drain Current C T C = C T C = C Continuous Drain T A = C I DSM Current T A =7 C Avalanche Current C Repetitive avalanche energy L=.mH C I AR, I AS E AR, E AS 97 T C = C 83 P Power Dissipation B D T C = C 33 Junction and Storage Temperature Range T J, T STG to V DS V GS I D 39 I DM T A = C 6. P Power Dissipation A DSM W T A =7 C ± Units V V A A A mj W C Thermal Characteristics Parameter Symbol Typ Max Maximum JunctiontoAmbient A t s 6 Maximum JunctiontoAmbient A D R θja SteadyState Maximum JunctiontoCase SteadyState.. R θjc Units C/W C/W C/W Rev.. : May 3 www.aosmd.com Page of 6
AON7 Electrical Characteristics (T J = C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =µa, V GS =V 3 V V DS =3V, V GS =V I DSS Zero Gate Voltage Drain Current µa T J = C I GSS GateBody leakage current V DS =V, V GS = ±V ± na V GS(th) Gate Threshold Voltage V DS =V GS I D =µa.7..8 V I D(ON) On state drain current V GS =V, V DS =V A R DS(ON) Static DrainSource OnResistance V GS =V, I D =A. 6. T J = C 7.6 9. V GS =6V, ID=A 7. 8.9 mω V GS =.V, I D =A.7 mω g FS Forward Transconductance V DS =V, I D =A 6 S V SD Diode Forward Voltage I S =A,V GS =V.7 V I S Maximum BodyDiode Continuous Current G A DYNAMIC PARAMETERS C iss Input Capacitance 96 9 pf C oss Output Capacitance V GS =V, V DS =V, f=mhz 38 7 pf C rss Reverse Transfer Capacitance 37 pf R g Gate resistance V GS =V, V DS =V, f=mhz 7 8 Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 33 nc Q g (.V) Total Gate Charge 6 6 nc V GS =V, V DS =V, I D =A Q gs Gate Source Charge. 7 8. nc Q gd Gate Drain Charge 7 7 nc t D(on) TurnOn DelayTime 9. ns t r TurnOn Rise Time V GS =V, V DS =V, ns t D(off) TurnOff DelayTime R L =.7Ω, R GEN =3Ω ns t f TurnOff Fall Time 78 ns t rr Body Diode Reverse Recovery Time I F =A, di/dt=a/µs 3 ns Q rr Body Diode Reverse Recovery Charge I F =A, di/dt=a/µs 37 7 7 nc A. The value of R θja is measured with the device mounted on in FR board with oz. Copper, in a still air environment with T A = C. The Power dissipation P DSM is based on R θja t s value and the maximum allowed junction temperature of C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) = C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Repetitive rating, pulse width limited by junction temperature T J(MAX) = C. Ratings are based on low frequency and duty cycles to keep initial T J = C. D. The R θja is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3µs pulses, duty cycle.% max. F. These curves are based on the junctiontocase thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) = C. The SOA curve provides a single pulse rating. G. The maximum current rating is limited by package. H. These tests are performed with the device mounted on in FR board with oz. Copper, in a still air environment with T A = C. mω THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Rev.. : May 3 www.aosmd.com Page of 6
AON7 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS V V DS =V 8 6V,8V,V 8 I D (A) 6 V V GS =3.V I D (A) 6 C C 3 V DS (Volts) Fig : OnRegion Characteristics (Note E) 3 6 V GS (Volts) Figure : Transfer Characteristics (Note E) 9.8 R DS(ON) (mω) 8 7 6 V GS =6V V GS =V Normalized OnResistance.6.. V GS =V I D =A 7 V GS =6V I D =A 3 3 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage (Note E).8 7 7 Temperature ( C) Figure : OnResistance vs. Junction 8Temperature (Note E) 7 I D =A.E.E.E R DS(ON) (mω) 3 9 I S (A).E.E.E3 C 3 6 7 8 9 V GS (Volts) Figure : OnResistance vs. GateSource Voltage (Note E).E.E....6.8. V SD (Volts) Figure 6: BodyDiode Characteristics (Note E) Rev.. : May 3 www.aosmd.com Page 3 of 6
AON7 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 V DS =V I D =A 3 3 C iss V GS (Volts) 6 Capacitance (pf) C oss 3 Q g (nc) Figure 7: GateCharge Characteristics C rss 3 V DS (Volts) Figure 8: Capacitance Characteristics I D (Amps).... R DS(ON) DC µs. T J(Max) = C T C = C... V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note F) µs µs ms Power (W) 3 3 T J(Max) = C T C = C 7.... 8 Figure : Single Pulse Power Rating Junctionto Case (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =. C/W In descending order D=.,.3,.,.,.,., single pulse Single Pulse T...... Figure : Normalized Maximum Transient Thermal Impedance (Note F) P D T on Rev.. : May 3 www.aosmd.com Page of 6
AON7 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS I AR (A) Peak Avalanche Current T A = C T A = C T A = C T A = C Time in avalanche, t A (µs) Figure : Single Pulse Avalanche capability (Note C) Power Dissipation (W) 9 8 7 6 3 7 T CASE ( C) Figure 3: Power Derating (Note F) 6 Current rating I D (A) 3 Power (W) T A = C 7 7 T CASE ( C) Figure : Current Derating (Note F)... 8 Figure : Single Pulse Power Rating Junctionto Ambient (Note H) Z θja Normalized Transient Thermal Resistance... D=T on /T T J,PK =T A P DM.Z θja.r θja R θja = C/W In descending order D=.,.3,.,.,.,., single pulse Single Pulse T..... Figure 6: Normalized Maximum Transient Thermal Impedance (Note H) P D T on Rev.. : May 3 www.aosmd.com Page of 6
AON7 Gate Charge Test Circuit & Waveform Qg V Qgs Qgd Ig Charge RL Resistive Switching Test Circuit & Waveforms ton toff td(on) t r td(off) t f Rg 9% % Id L Unclamped Inductive Switching (UIS) Test Circuit & Waveforms E = / LI AR AR Rg Id BV DSS I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr Rev.. : May 3 www.aosmd.com Page 6 of 6