DATASHEET HI-506, HI-507, HI-508, HI-509. Features. Applications. Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers

DTSHEET HI-506, HI-507, HI-508, HI-509 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS nalog Multiplexers FN3142 Rev 10.00 The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see pplication Note N520). The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic 1 and maximum 0.8V for logic 0. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200 resistor and diode clamp to each supply. The HI-506 is a single 16-channel, the HI-507 is an 8-channel differential, the HI-508 is a single 8-channel and the HI-509 is a 4-channel differential multiplexer. If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. Features Pb-Free vailable (RoHS Compliant) (See Ordering Info) Low ON Resistance........................ 180 Wide nalog Signal Range ±15V TTL/CMOS Compatible ccess Time............................. 250ns Maximum Power Supply...................... 44V Break-Before-Make Switching No Latch-Up Replaces DG506/DG506 and DG507/DG507 Replaces DG508/DG508 and DG509/DG509 pplications Data cquisition Systems Precision Instrumentation Demultiplexing Selector Switch FN3142 Rev 10.00 Page 1 of 25

Ordering Information PRT NUMBER PRT MRKING TEMP. RNGE ( C) PCKGE PKG. DWG. # HI1-0506-2 HI1-506-2-55 to +125 28 Ld CERDIP F28.6 HI4P0506-5Z (Note 1) HI4P 506-5Z 0 to +75 28 Ld PLCC (Pb-free) N28.45 HI9P0506-9Z (Note 1) HI9P506-9Z -40 to +85 28 Ld SOIC (Pb-free) M28.3 HI3-0507-5Z (No longer available, recommended replacement: HI3-0547-5Z) HI3-507-5Z 0 to +75 28 Ld PDIP (Note 3) (Pb-free) E28.6 HI1-0508-2 HI1-508-2-55 to 125 16 Ld CERDIP F16.3 HI3-0508-5Z (Note 1) HI3-508-5Z 0 to +75 16 Ld PDIP (Note 3) (Pb-free) E16.3 HI9P0508-5Z (Notes 1, 2) HI9P508-5Z 0 to +75 16 Ld SOIC (Pb-free) M16.15 HI9P0508-9Z (Note 1) HI9P508-9Z -40 to +85 16 Ld SOIC (Pb-free) M16.15 HI1-0509-2 HI1-509-2-55 to +125 16 Ld CERDIP F16.3 HI4P0509-5Z (Notes 1, 2) (No longer available, recommended replacement: DG409DYZ) HI4P 509-5Z 0 to +75 20 Ld PLCC (Pb-free) N20.35 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS NNEL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. dd 96 suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN3142 Rev 10.00 Page 2 of 25

Pinouts HI-506 (CERDIP, SOIC) TOP VIEW HI-506 (PLCC) TOP VIEW +V SUPPLY 1 2 28 27 -V SUPPLY IN 16 +V SUPPLY -V SUPPLY IN 8 IN 16 3 4 26 25 IN 8 IN 7 IN 15 5 4 3 2 1 28 27 26 25 IN 7 IN 15 IN 14 IN 13 IN 12 5 6 7 8 24 23 22 21 IN 6 IN 5 IN 4 IN 3 IN 14 IN 13 IN 12 6 7 8 24 23 22 IN 6 IN 5 IN 4 IN 11 9 20 IN 2 IN 11 9 21 IN 3 IN 10 IN 9 GND 10 11 12 13 19 18 17 16 IN 1 ENBLE DDRESS 0 DDRESS 1 IN 10 IN 9 10 11 12 13 14 15 16 17 18 20 19 IN 2 IN 1 DDRESS 3 14 15 DDRESS 2 GND 3 2 1 0 ENBLE HI-507 (PDIP, CERDIP) TOP VIEW HI-508 (PDIP, CERDIP, SOIC) TOP VIEW +V SUPPLY B IN 8B IN 7B IN 6B IN 5B IN 4B IN 3B 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 -V SUPPLY IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 0 ENBLE -V SUPPLY IN 1 IN 2 IN 3 IN 4 1 2 3 4 5 6 7 8 16 1 15 2 14 GND 13 +V SUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8 IN 2B 10 19 IN 1 IN 1B 11 18 ENBLE GND 12 17 DDRESS 0 13 16 DDRESS 1 14 15 DDRESS 2 FN3142 Rev 10.00 Page 3 of 25

Pinouts (Continued) HI-509 (PDIP, CERDIP, SOIC) TOP VIEW HI-509 (PLCC) TOP VIEW 0 ENBLE 1 2 16 15 1 GND ENBLE 0 1 GND -V SUPPLY 3 14 +V SUPPLY 3 2 1 20 19 IN 1 IN 2 IN 3 IN 4 4 5 6 7 8 13 12 11 10 9 IN 1B IN 2B IN 3B IN 4B B -V SUPPLY IN 1 IN 2 4 5 6 7 18 17 16 15 +V SUPPLY IN 1B IN 2B IN 3 8 14 IN 3B 9 10 11 12 13 IN 4 B IN 4B FN3142 Rev 10.00 Page 4 of 25

Truth Tables HI-506 3 2 1 0 EN ON CHNNEL X X X X L None L L L L H 1 L L L H H 2 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 HI-508 2 1 0 EN ON CHNNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 HI-509 1 0 EN ON CHNNEL PIR X X L None L L H 1 L H H 2 H L H 3 H H H 4 HI-507 2 1 0 EN ON CHNNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 FN3142 Rev 10.00 Page 5 of 25

Functional Diagrams HI-506 HI-507 IN 1 IN 1 IN 2 DECODER/ DRIVER IN 8 IN 1B B IN 16 5V REF LEVEL SHIFT IN 8B DECODER/ DRIVER DIGITL INPUT PROTECTION 0 1 2 3 EN 5V REF DIGITL INPUT PROTECTION LEVEL SHIFT 0 1 2 EN HI-508 HI-509 IN 1 IN 1 IN 2 DECODER/ DRIVER IN 4 IN 1B B IN 8 5V REF LEVEL SHIFT IN 4B DECODER/ DRIVER DIGITL INPUT PROTECTION 0 1 2 EN 5V REF DIGITL INPUT PROTECTION LEVEL SHIFT 0 1 EN FN3142 Rev 10.00 Page 6 of 25

Schematic Diagrams DDRESS DECODER V+ P P P P P P P N N N TO P-CHNNEL DEVICE OF THE SWITCH 0 OR 0 N 2 OR 2 1 OR 1 N N TO N-CHNNEL DEVICE OF THE SWITCH 3 OR 3 N ENBLE DELETE 3 OR 3 INPUT FOR HI-507, HI-508, HI-509 DELETE 2 OR 2 INPUT FOR HI-509 V- DDRESS INPUT BUFFER LEVEL SHIFTER P3 V+ V+ D1 P1 N1 P4 P5 P6 P7 P8 P9 P10 200 D2 V L V R P2 N4 N6 N7 N8 N9 N10 V- N2 N5 IN N3 V- LL N-CHNNEL BODIES TO V- LL P-CHNNEL BODIES TO V+ UNLESS OTHERWISE INDICTED TTL REFEREE CIRCUIT MULTIPLEX SWITCH P15 Q1P Q2P Q3P V+ Q4P FROM DECODE N18 Q5N Q6N Q8N IN V+ N19 N17 V L N12 R2 16.8k P17 Q11P Q7P Q10N Q9P N13 N14 N15 D3 R3 6.8k Q12N P16 V R P18 V- V- GND FROM DECODE FN3142 Rev 10.00 Page 7 of 25

bsolute Maximum Ratings V+ to V-...........................................+44V V+ to GND.........................................+22V V- to GND......................................... -25V Digital Input Voltage (V EN, V )..... (V-) -4V to (V+) +4V or 20m, Whichever Occurs First nalog Signal (V IN, V, Note 5).......... (V-) -2V to (V+) +2V Continuous Current, In or Out......................... 20m Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max). 40m Operating Conditions Temperature Ranges HI-50X-2................................-55 C to +125 C HI-50X-4.................................-25 C to +85 C HI-50X-5.................................. 0 C to +75 C HI-50X-9.................................-40 C to +85 C Typical Minimum Supply Voltage............ 10V or Single 20V Thermal Information Thermal Resistance (Typical, Note 4) J ( C/W) JC ( C/W) 16 Ld CERDIP Package............ 85 32 16 Ld SOIC Package.............. 115 N/ 16 Ld PDIP Package.............. 100 N/ 20 Ld PLCC Package.............. 80 N/ 28 Ld CERDIP Package............ 55 18 28 Ld PDIP Package.............. 60 N/ 28 Ld SOIC Package.............. 70 N/ 28 Ld PLCC Package.............. 70 N/ Maximum Junction Temperature Ceramic Packages............................... +175 C Plastic Packages................................ +150 C Maximum Storage Temperature Range..........-65 C to +150 C Pb-free reflow profile..........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp CUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. Signals on IN or exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. Electrical Specifications Supplies = +15V, -15V; V H (Logic Level High) = 2.4V; V L (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section -2-4, -5, -9 PRMETER TEST CONDITIONS TEMP ( C) MIN (Note 11) TYP MX MIN (Note 11) TYP MX UNITS DYNMIC CHRCTERISTICS ccess Time, t 25-250 500-250 - ns Full - - 1000 - - 1000 ns Break-Before-Make Delay, t OPEN 25 25 80-25 80 - ns Enable Delay (ON), t ON(EN) 25-250 500-250 - ns Full - - 1000 - - 1000 ns Enable Delay (OFF), t OFF(EN) 25-250 500-250 - ns Full - - 1000 - - 1000 ns Settling Time, t S To 0.1% 25-1.2 - - 1.2 - s (HI-506 and HI-507) To 0.01% 25-2.4 - - 2.4 - s Settling Time, t S To 0.1% 25-360 - - 360 - ns (HI-508 and HI-509) To 0.01% 25-600 - - 600 - ns Off Isolation Note 9 25-68 - - 68 - db Channel Input Capacitance, C S(OFF) 25-10 - - 10 - pf Channel Output Capacitance, C D(OFF) HI-506 25-52 - - 52 - pf HI-507 25-30 - - 30 - pf HI-508 25-17 - - 17 - pf HI-509 25-12 - - 12 - pf Digital Input Capacitance, C 25-6 - - 6 - pf Input to Output Capacitance, C DS(OFF) 25-0.08 - - 0.08 - pf DIGITL INPUT CHRCTERISTICS Input Low Threshold, V L Full - - 0.8 - - 0.8 V Input High Threshold, V H Full 2.4 - - 2.4 - - V FN3142 Rev 10.00 Page 8 of 25

Electrical Specifications Supplies = +15V, -15V; V H (Logic Level High) = 2.4V; V L (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) PRMETER TEST CONDITIONS TEMP ( C) -2-4, -5, -9 MIN (Note 11) TYP MX MIN (Note 11) TYP MX Input Leakage Current Note 8 Full - - 1.0 - - 1.0 (High or Low), I NLOG CHNNEL CHRCTERISTICS nalog Signal Range, V IN Full -15 - +15-15 - +15 V On Resistance, r ON Note 6 25-180 300-180 400 r ON, (ny Two Channels) 25-5 - - 5 - % Off Input Leakage Current, I S(OFF) Note 7 25-0.03 - - 0.03 - n Full - - 50 - - 50 n Off Output Leakage Current, Note 7 25-0.3 - - 0.3 - n I D(OFF ) HI-506 Full - - 300 - - 300 n HI-507 Full - - 200 - - 200 n HI-508 Full - - 200 - - 200 n HI-509 Full - - 100 - - 100 n On Channel Leakage Current, I D(ON) Note 7 25-0.3 - - 0.3 - n HI-506 Full - - 300 - - 300 n HI-507 Full - - 200 - - 200 n HI-508 Full - - 200 - - 200 n HI-509 Full - - 100 - - 100 n Differential Off Output Leakage Current, I DIFF Full - - 50 - - 50 n (HI-507, HI-509 Only) POWER SUPPLY CHRCTERISTICS Current, I+ HI-506/HI-507 Note 10 Full - 1.5 3.0-1.5 3.0 m HI-508/HI-509 Note 10 Full - 1.5 2.4-1.5 2.4 m Current, I- HI-506/HI-507 Note 10 Full - 0.4 1.0-0.4 1.0 m HI-508/HI-509 Note 10 Full - 0.4 1.0-0.4 1.0 m Power Dissipation, P D HI-506/HI-507 Full - - 60 - - 60 mw HI-508/HI-509 Full - - 51 - - 51 mw NOTES: 6. V = ±10V, I = +1m. 7. 10n is the practical lower limit for high speed measurement in the production test environment. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1n at +25 C. 9. V EN = 0.8V, R L = 1k, C L = 15pF, V S = 7V RMS, f = 100kHz. 10. V EN, V = 0V or 2.4V. 11. Parts are 100% tested at +25 C. Over-temperature limits established by characterization and are not production tested. UNITS FN3142 Rev 10.00 Page 9 of 25

Test Circuits and Waveforms T = +25 C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified 1m V 2 IN V IN ron = V 2 1m FIGURE 1. TEST CIRCUIT 400 2.2 ON RESISTE ( ) 300 200 100 +125 C +25 C -55 C NORMLIZED RESISTE (REFERRED TO VLUE T 15V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8-55 C TO +125 C V IN = 0V 0-15 -10-5 0 5 10 15 NLOG INPUT (V) 0.6 10 11 12 13 14 15 SUPPLY VOLTGE ( V) FIGURE 1B. ON RESISTE vs NLOG INPUT VOLTGE FIGURE 1C. NORMLIZED ON RESISTE vs SUPPLY VOLTGE FIGURE 1. ON RESISTE 100n 10n OFF PUT LEKGE CURRENT I D(OFF) LEKGE CURRENT 1n 100p I D(ON) OFF INPUT LEKGE CURRENT I S(OFF) 10V EN 0.8V I D(OFF) 10V 10p 25 50 75 100 125 TEMPERTURE ( C) FIGURE 2. LEKGE CURRENT vs TEMPERTURE FIGURE 2B. I D(OFF) TEST CIRCUIT (NOTE 12) FN3142 Rev 10.00 Page 10 of 25

Test Circuits and Waveforms T = +25 C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) I S(OFF) EN 0.8V 0 1 EN I D(ON) 10V +10V +10V 10V 2.4V FIGURE 2C. I S(OFF) TEST CIRCUIT (NOTE 12) FIGURE 2D. I D(ON) TEST CIRCUIT (NOTE 12) FIGURE 2. LEKGE CURRENTS NOTE: 12. Two measurements per channel: ±10V and +10V. (Two measurements per device for I D(OFF) ±10V and +10V) 70 60-55 C SWITCH CURRENT (m) 50 40 30 20 +125 C +25 C V IN 10 0 0 2 4 6 8 10 12 14 16 VOLTGE CROSS SWITCH ( V) FIGURE 3. ON CHNNEL CURRENT vs VOLTGE FIGURE 3. ON CHNNEL CURRENT FIGURE 3B. TEST CIRCUIT 8 +15V/+10V +I SUPPLY V SUPPLY = 15V SUPPLY CURRENT (m) 6 4 2 0 1k V SUPPLY = 10V 10k 100k 1M 10M TOGGLE FREQUEY (Hz) V 50 3.5V EN GND HIGH = 3.5V V LOW = 0V 50% DUTY CYCLE Similar connection for HI-507/ HI-508/HI-509 V+ 3 IN 1 HI-506 2 IN 2 THRU 1 IN 7/15 0 IN 8/16 V- -I SUPPLY -15V/-10V 10V/ 5V +10V/+5V 10 14 M pf FIGURE 4. SUPPLY CURRENT vs TOGGLE FREQUEY FIGURE 4. DYNMIC SUPPLY CURRENT FIGURE 4B. TEST CIRCUIT FN3142 Rev 10.00 Page 11 of 25

Test Circuits and Waveforms T = +25 C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) +15V 600 3 V+ IN 1 10V CCESS TIME (ns) 400 200 V 50 3.5V 2 IN 2 THRU IN 7/15 1 HI-506 0 IN 16 EN GND V- +10V 10 50 k pf -15V 0 2 3 4 5 13 14 15 LOGIC LEVEL (HIGH) (V) Similar connection for HI-507/ HI-508/HI-509 FIGURE 5. CCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 5B. TEST CIRCUIT 50% 3.5V DDRESS DRIVE (V ) 0V V INPUT 2V/DIV. S 1 ON +10V 10% PUT -10V PUT 5V/DIV. t S 16 ON FIGURE 5C. MESUREMENT POINTS FIGURE 5. CCESS TIME 200ns/DIV. FIGURE 5D. WVEFORMS +15V 3 2 V+ HI-506 IN 1 +5V V 50 1 IN 2 THRU IN 7/IN 15 IN 8 /16 3.5V 0 EN GND V- 200 V 50pF -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 6. TEST CIRCUIT FN3142 Rev 10.00 Page 12 of 25

Test Circuits and Waveforms T = +25 C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) 3.5V V INPUT 2V/DIV. 0V DDRESS DRIVE (V ) S 1 ON S 16 ON PUT PUT 1V/DIV. 50% 50% t OPEN 100ns/DIV. FIGURE 6B. MESUREMENT POINTS FIGURE 6. BREK-BEFORE-MKE DELY FIGURE 6C. WVEFORMS +15V 3 2 1 V+ HI-506 IN 1 IN 2 THRU IN 7/IN 15 IN 8 /16 +10V V 50 0 EN GND V- 200 V 50pF -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 7. TEST CIRCUIT 50% 3.5V 50% ENBLE DRIVE (V ) ENBLE DRIVE 2V/DIV. 0V 90% PUT DISBLED ENBLED (S 1 ON) t ON(EN) 10% 0V PUT 2V/DIV. t OFF(EN) 100ns/DIV FIGURE 7B. MESUREMENT POINTS FIGURE 7. ENBLE DELYS FIGURE 7C. WVEFORMS FN3142 Rev 10.00 Page 13 of 25

Typical Performance Curves T = 25 C, V SUPPLY = 15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified 4 100 INPUT LOGIC THRESHOLD (V) 3 2 1 0 10 12 14 16 18 20 POWER SUPPLY VOLTGE ( V) (V S ), (V D ) OFF ISOLTION (db) 80 60 40 20 0 10 4 V EN = 0V C LOD = 28pF V S = 7V RMS R L = 1k R L = 10M 10 5 10 6 10 7 FREQUEY (Hz) FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTGE FIGURE 9. OFF ISOLTION vs FREQUEY 3 3 POWER SUPPLY CURRENT (m) 2 1 V EN = 0V V EN = 2.4V POWER SUPPLY CURRENT (m) 2 1 EN = 5V EN = 0V 0-55 -35-15 -5 25 45 65 85 105 125 0-55 -35-15 -5 25 45 65 85 105 125 TEMPERTURE ( C) TEMPERTURE ( C) FIGURE 10. HI-506/HI-507 FIGURE 10B. HI-508/HI-509 FIGURE 10. POWER SUPPLY CURRENT vs TEMPERTURE FN3142 Rev 10.00 Page 14 of 25

Die Characteristics METLLIZTION: Type: Cul Thickness: 16kÅ ±2kÅ SUBSTRTE POTENTIL (NOTE): -V SUPPLY PSSIVTION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CSE CURRENT DENSITY: 1.4 x 10 5 /cm 2 TRNSISTOR COUNT: 421 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -V SUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SUPPLY potential. Metallization Mask Layout HI-506 HI-507 EN 0 1 2 3 GND EN 0 1 2 GND IN 1 IN 9 IN 1 IN 1B IN 2 IN 10 IN 2 IN 2B IN 3 IN 11 IN 3 IN 3B IN 4 IN 12 IN 4 IN 4B IN 5 IN 13 IN 5 IN 5B IN 6 IN 14 IN 6 IN 6B IN 7 IN 15 IN 7 IN 7B IN 8 IN 16 IN 8 IN 8B -V +V -V +V B FN3142 Rev 10.00 Page 15 of 25

Die Characteristics METLLIZTION: Type: Cul Thickness: 16kÅ 2kÅ SUBSTRTE POTENTIL (NOTE): -V SUPPLY PSSIVTION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CSE CURRENT DENSITY: 1.4 x 10 5 /cm 2 TRNSISTOR COUNT: 234 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -V SUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SUPPLY potential. Metallization Mask Layout HI-508 HI-509 EN 0 1 2 GND EN 0 1 GND -V SUP +V SUP -V SUP +V SUP IN 1 IN 5 IN 1 IN 1B IN 2 IN 6 IN 2 IN 2B IN 3 IN 3 IN 7 IN 3B IN 4 IN 8 IN 4 B IN 4B FN3142 Rev 10.00 Page 16 of 25

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DTE REVISION CHNGE May 24, 2016 FN3142.10 Updated ordering information table on page 2. ugust 7, 2015 FN3142.9 Updated ordering information table on page 2. dded Revision History and bout Intersil sections. Updated M28.3 to most recent revision with change as follows: dded land pattern bout Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN3142 Rev 10.00 Page 17 of 25

Dual-In-Line Plastic Packages (PDIP) INDEX RE BSE PLNE SETING PLNE D1 B1 -C- -- N 1 2 3 N/2 B D e D1 E1 NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per NSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions, 1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030-0.045 inch (0.76-1.14mm). -B- 1 0.010 (0.25) M C 2 L B S e C E C L e C e B E16.3 (JEDEC MS-001-BB ISSUE D) 16 LED DUL-IN-LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES - 0.210-5.33 4 1 0.015-0.39-4 2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005-0.13-5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e 0.300 BSC 7.62 BSC 6 e B - 0.430-10.92 7 L 0.115 0.150 2.93 3.81 4 N 16 16 9 Rev. 0 12/93 FN3142 Rev 10.00 Page 18 of 25

Dual-In-Line Plastic Packages (PDIP) INDEX RE BSE PLNE SETING PLNE D1 B1 -C- -- N 1 2 3 N/2 B D e D1 E1 NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per NSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions, 1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030-0.045 inch (0.76-1.14mm). -B- 1 0.010 (0.25) M C 2 L B S e C E C L e C e B E28.6 (JEDEC MS-011-B ISSUE B) 28 LED DUL-IN-LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES - 0.250-6.35 4 1 0.015-0.39-4 2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.380 1.565 35.1 39.7 5 D1 0.005-0.13-5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - e 0.600 BSC 15.24 BSC 6 e B - 0.700-17.78 7 L 0.115 0.200 2.93 5.08 4 N 28 28 9 Rev. 1 12/00 FN3142 Rev 10.00 Page 19 of 25

Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BSE PLNE SETING PLNE S1 b2 ccc M bbb S b C - B Q -C- -B- C - B S D e D S -D- -- NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y14.5M - 1982. 10. Controlling dimension: IH. E L M c1 e/2 S D S aaa M C - B LED FINISH BSE METL b1 M (b) SECTION - S e c D S (c) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURTION ) 16 LED CERMIC DUL-IN-LINE FRIT SEL PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES - 0.200-5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840-21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - e 0.300 BSC 7.62 BSC - e/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005-0.13-7 90 o 105 o 90 o 105 o - aaa - 0.015-0.38 - bbb - 0.030-0.76 - ccc - 0.010-0.25 - M - 0.0015-0.038 2, 3 N 16 16 8 Rev. 0 4/94 FN3142 Rev 10.00 Page 20 of 25

Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BSE PLNE SETING PLNE S1 b2 ccc M bbb S b C - B Q -C- -B- C - B S D e D S -D- -- NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y14.5M - 1982. 10. Controlling dimension: IH. E L M c1 e/2 S D S aaa M C - B LED FINISH BSE METL b1 M (b) SECTION - S e c D S (c) F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURTION ) 28 LED CERMIC DUL-IN-LINE FRIT SEL PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES - 0.232-5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490-37.85 5 E 0.500 0.610 12.70 15.49 5 e 0.100 BSC 2.54 BSC - e 0.600 BSC 15.24 BSC - e/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005-0.13-7 90 o 105 o 90 o 105 o - aaa - 0.015-0.38 - bbb - 0.030-0.76 - ccc - 0.010-0.25 - M - 0.0015-0.038 2, 3 N 28 28 8 Rev. 0 4/94 FN3142 Rev 10.00 Page 21 of 25

Small Outline Plastic Packages (SOIC) N INDEX RE 1 2 3 e D B 0.25(0.010) M C M E -B- -- -C- SETING PLNE B S H 0.25(0.010) M B 1 0.10(0.004) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per NSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 45 C M16.15 (JEDEC MS-012-C ISSUE C) 16 LED NRROW BODY SMLL LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES 0.0532 0.0688 1.35 1.75-1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N 16 16 7 0 8 0 8 - Rev. 1 6/05 FN3142 Rev 10.00 Page 22 of 25

Small Outline Plastic Packages (SOIC) N INDEX RE 1 2 3 D e B 0.25(0.010) M C M E -B- -- -C- SETING PLNE B S H 0.25(0.010) M B 1 a 0.10(0.004) L M h x 45o C M28.3 (JEDEC MS-013-E ISSUE C) 28 LED WIDE BODY SMLL LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES 0.0926 0.1043 2.35 2.65-1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N 28 28 7 0 o 8 o 0 o 8 o - Rev. 1, 1/13 TYPICL RECOMMENDED LND PTTERN (1.50mm) (9.38mm) (1.27mm TYP) (0.51mm TYP) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per NSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN3142 Rev 10.00 Page 23 of 25

Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER D1 D 0.020 (0.51) MX 3 PLCS 0.026 (0.66) 0.032 (0.81) C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP E1 E C L 1 0.013 (0.33) 0.021 (0.53) 0.004 (0.10) C 0.025 (0.64) 0.045 (1.14) R D2/E2 D2/E2 VIEW NOTES: 1. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per NSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. llowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. -C- 0.020 (0.51) MIN SETING PLNE N28.45 (JEDEC MS-018B ISSUE ) 28 LED PLSTIC LEDED CHIP CRRIER PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES 0.165 0.180 4.20 4.57-1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 0.045 (1.14) MIN VIEW TYP. 0.025 (0.64) MIN Copyright Intersil mericas LLC 2001-2016. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3142 Rev 10.00 Page 25 of 25