DATASHEET ISL70024SEH, ISL73024SEH. Features. Applications. Related Literature. 200V, 7.5A Enhancement Mode GaN Power Transistor

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DATASHEET 2V, 7.5A Enhancement Mode GaN Power Transistor FN8976 Rev.4. The ISL724SEH and ISL7324SEH are 2V N-channel enhancement mode GaN power transistors.

1 DATASHEET 2V, 7.5A Enhancement Mode GaN Power Transistor FN8976 Rev.4. The ISL724SEH and ISL7324SEH are 2V N-channel enhancement mode GaN power transistors. These GaN FETs have been characterized for destructive Single Event Effects (SEE) and tested for Total Ionizing Dose (TID) radiation up to 1krad(Si) High Dose Rate (HDR) and 75krad(Si) Low Dose Rate (LDR). Applications for these devices include commercial aerospace, medical, and nuclear power generation. GaN s exceptionally high electron mobility and low temperature coefficient allows for very low r DS(ON), while its lateral device structure and majority carrier diode provide exceptionally low Q G and near zero Q RR. The end result is a device that can operate at a higher switching frequency with more efficiency while reducing the overall solution size. By combining the exceptional performance of the GaN FET in a hermetically sealed Surface Mount Device (SMD) package with manufacturing in a MIL-PRF like flow results in best-in-class power transistors that are ideally suited for high reliability applications. Related Literature For a full list of related documents, visit our website: device pages Features Very low r DS(ON) 45mΩ (typical) Ultra low total gate charge 2.5nC (typical) SEE tolerance (V DS = 16V, V GS = V) Characterized at LET 86MeV cm 2 /mg Radiation hardness assurance testing (lot-by-lot) High dose rate (5-3rad(Si)/s): 1krad(Si) Low dose rate (.1rad(Si)/s): 75krad(Si) Ultra small hermetically sealed 4 Ld Surface Mount Device (SMD) package Package area: 42mm 2 Full military-temperature range operation T A = -55 C to +125 C T J = -55 C to +15 C Applications Switching regulation Motor drives Relay drives Inrush protection Down hole drilling High reliability industrial On-State Resistance (mω) ID =.8A ID = 2.4A ID = 4.A ID = 5.6A ID = 7.2A Gate-Source Voltage (V) Figure 1. ISL724SEH 4 Ld SMD Package Figure 2. On-State Resistance (+25 C) FN8976 Rev.4. Page 1 of 13

2 1. Overview 1. Overview 1.1 Ordering Information Ordering Part Number (Note 1) ISL724SEHML Radiation Hardness (Total Ionizing Dose) HDR to 1krad(Si) LDR to 75krad(Si) Temperature Range ( C) Package (RoHS Compliant) Package Drawing -55 to Ld SMD J4.A ISL7324SEHML LDR to 75krad(Si) -55 to Ld SMD J4.A ISL724SEHMX HDR to 1krad(Si) -55 to +125 Die - LDR to 75krad(Si) ISL7324SEHMX LDR to 75krad(Si) -55 to +125 Die - ISL724SEHX/SAMPLE (Note 2) N/A +25 Die - ISL7324SEHX/SAMPLE (Note 2) N/A +25 Die - ISL724SEHL/PROTO (Note 2) N/A -55 to Ld SMD J4.A ISL7324SEHL/PROTO (Note 2) N/A -55 to Ld SMD J4.A ISL74SEHEV3Z (Note 3) Evaluation board with the ISL74SEH low-side driver and ISL724SEH 2V GaN FET ISL734SEHEV4Z (Note 3) Half bridge power stage using the ISL734SEH, ISL7324SEH, and the ISL7161M Notes: 1. These Pb-free Hermetic packaged products employ 1% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. The /PROTO and /SAMPLE parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO and /SAMPLE parts meet the electrical limits and conditions across the temperature range specified in this datasheet and are of the same form and fit as the ISL724SEHML/ISL7324SEHML devices. The /PROTO and /SAMPLE parts do not come with a Certificate of Conformance (C of C) and have no accompanying data or documentation. 3. Evaluation boards use the /PROTO parts and /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. Table 1. Key Differences Between Family of Parts Part Number Breakdown Voltage Radiation Assurance ISL724SEH 2V HDR to 1krad(Si) LDR to 75krad(Si) ISL7324SEH 2V LDR to 75krad(Si) ISL723SEH 1V HDR to 1krad(Si) LDR to 75krad(Si) ISL7323SEH 1V LDR to 75krad(Si) FN8976 Rev.4. Page 2 of 13

3 1. Overview 1.2 Pin Configuration 4 Ld SMD (4) G (3) D (1) S (2) SUB (4) G (3) D Pin #1 Index Area (1) S Top View (2) SUB Bottom View Note: The ESD triangular mark indicates Pin #1. It is a part of the device marking and is placed on the lid in the quadrant where Pin #1 is located. 1.3 Pin Descriptions Pin Number Pin Name Description 1 S Source connection for the GaN FET. 2 SUB Substrate connection for the GaN FET which is internally shorted in to source. Tie this pin to source on the PCB. 3 D Drain connection for the GaN FET. 4 G Gate connection for the GaN FET. Minimize trace inductance from driver to reduce over-stressing the gate. NA Lid Internally tied to the source pin. FN8976 Rev.4. Page 3 of 13

4 2. Specifications 2. Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit V DS 2 V V DS (Note 4) 16 V V GS -4 6 V ESD Rating (Drain-to-Source) Value Unit Human Body Model (Tested per MIL-STD-883 TM315) 2 kv Machine Model (Tested per JESD22-A115C) 2 V Charged Device Model (Tested per JS-2-214) 75 V ESD Rating (Gate-to-Source) Value Unit Human Body Model (Tested per MIL-STD-883 TM315) 5 V Machine Model (Tested per JESD22-A115C) 2 V Charged Device Model (Tested per JS-2-214) 75 V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Note: 4. Tested in a heavy ion environment at LET = 86.4MeV cm 2 /mg at +125 C (T C ). 2.2 Thermal Information in SMD Package J4.A Thermal Resistance Typical Maximum Unit θ JA (Note 5) C/W θ JC (Note 6) C/W Notes: 5. θ JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB For θ JC, the case temp location is on the solder terminations adjacent to the center of the package underside. Parameter Minimum Maximum Unit Maximum Junction Temperature C Storage Temperature Range C 2.3 Recommended Operating Conditions Parameter Minimum Maximum Unit Temperature C V DS 16 V I D (V GS = 5.V, T C = +25 C) (Note 7) 7.5 A I D (V GS = 5.V, T C = +15 C) (Note 7) 4.5 A Note: 7. T J = +15 C. Current limited by package constraints. FN8976 Rev.4. Page 4 of 13

5 2. Specifications 2.4 Electrical Specifications Unless otherwise noted, V DS = 16V. Boldface limits apply across the operating temperature range, -55 C to +125 C; over a total ionizing dose of 1krad(Si) with exposure at a high dose rate of 5-3rad(Si)/s; or over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <1mrad(Si)/s. Parameter Symbol Test Conditions Min (Note 9) Typ (Note 9) Max (Note 9) Unit Static Characteristics Drain-to-Source Breakdown Voltage BV DSS V GS = V, I D = 125µA V Drain-to-Source Leakage Current I DSS V DS = 16V, V GS = V µa Drain-to-Gate Leakage Current I GSX V DS = 16V, V GS = V µa Gate-to-Source Forward Leakage I GSS V GS = 5V ma Gate-to-Source Reverse Leakage V GS = -4V µa Gate Threshold Voltage V GS(th) V DS = V GS, I D = 1.5mA V Drain-to-Source ON-Resistance r DS(ON) V GS = 5V, I D = 7A mω Source-to-Drain Forward Voltage V SD I S =.5A, V GS = V V Dynamic Characteristics Input Capacitance C ISS V DS = 1V, V GS = V (Note 1) pf Output Capacitance C OSS V DS = 1V, V GS = V, T A = +25 C pf Reverse Transfer Capacitance C RSS V DS = 1V, V GS = V (Note 1) pf Gate Resistance r G T A = +25 C (Note 1) mω Total Gate Charge Q G V DS = 1V, V GS = 5V, I D = 7A, T A = +25 C nc Gate Charge at Threshold Q G(th) V DS = 1V, I D = 7A (Note 1) nc Gate-to-Source Charge Q GS V DS = 1V, I D = 7A, T A = +25 C nc Gate-to-Drain Charge Q GD V DS = 1V, I D = 7A, T A = +25 C nc Output Charge Q OSS V DS = 1V, V GS = V (Note 1) nc Notes: 8. Typical values shown are not guaranteed. 9. Parameters with MIN and/or MAX limits are 1% tested at -55 C, +25 C, and +125 C, unless otherwise specified. 1. Limits are established by characterization and/or design and are not tested. FN8976 Rev.4. Page 5 of 13

6 3. Typical Performance Curves 3. Typical Performance Curves Unless otherwise noted, V DS = 16V; T A = +25 C Drain Current (A) VGS = 2V VGS = 3V VGS = 4V VGS = 5V Drain Current (A) VGS = 2V VGS = 3V VGS = 4V VGS = 5V Drain-Source Voltage (V) Figure 3. Output Characteristics (+25 C) Drain-Source Voltage (V) Figure 4. Output Characteristics (+125 C) Drain Current (A) VGS = 2V VGS = 3V VGS = 4V VGS = 5V Drain Current (A) C 125 C -55 C Drain-Source Voltage (V) Figure 5. Output Characteristics (-55 C) Gate-Source Voltage (V) Figure 6. Transfer Characteristics On-State Resistance (mω) ID =.8A ID = 2.4A 1 ID = 4.A ID = 5.6A ID = 7.2A Gate-Source Voltage (V) Figure 7. On-State Resistance (+25 C) On-State Resistance (mω) ID =.8A ID = 2.4A 2 ID = 4.A ID = 5.6A ID = 7.2A Gate-Source Voltage (V) Figure 8. On-State Resistance (+125 C) FN8976 Rev.4. Page 6 of 13

7 3. Typical Performance Curves Unless otherwise noted, V DS = 16V; T A = +25 C. (Continued) On-State Resistance (mω) ID =.8A ID = 2.4A ID = 4.A ID = 5.6A ID = 7.2A Capacitance (pf) CISS CRSS COSS Gate-Source Voltage (V) VDS (V) Figure 9. On-State Resistance (-55 C) Figure 1. Capacitance (Linear Scale) 1 7 Capacitance (pf) CISS CRSS COSS Source-Drain Current (A) C -55 C +125 C VDS (V) Figure 11. Capacitance (Log Scale) Source-Drain Voltage (V) Figure 12. Reverse Drain-Source Characteristics Normalized On-State Resistance Normalized On-State Resistance Ambient Temperature ( C) Ambient Temperature ( C) Figure 13. Normalized On-State Resistance Figure 14. Normalized Threshold Voltage FN8976 Rev.4. Page 7 of 13

8 3. Typical Performance Curves Unless otherwise noted, V DS = 16V; T A = +25 C. (Continued) 1 Steady State, T J = +15 C, θ JC = 18.7 C/W 1 Steady State, T J = +15 C, θ JC = 23.7 C/W Drain-Source Current (A) Limited by r DS(ON) T C = +15 C T C = +25 C Drain-Source Current (A) Limited by r DS(ON) T C = +15 C T C = +25 C Drain-Source Voltage (V) Figure 15. Safe Operating Area Drain-Source Voltage (V) Figure 16. Safe Operating Area (Derated) FN8976 Rev.4. Page 8 of 13

9 4. Die Characteristics 4. Die Characteristics Die Information Table 2. Die and Assembly Related Information Dimensions 2766µm x 95µm (18.9 mils x 37.4 mils) Thickness: 685µm (26.97 mils) Solder Bar View A f d 2 6 i c h B 1 7 Side View e g g 685µm 815µm 1 ±2µm Color Key: Pads in Green are the Source Pads in Orange are the Drain Pad in Blue is the Gate Pad in Purple is the Substrate Table 3. Dimensions Dimension Min (µm) Nominal (µm) Max (µm) A B c d e f g h i FN8976 Rev.4. Page 9 of 13

10 5. Revision History 5. Revision History Rev. Date Description 4. Updated ordering information table by adding evaluation boards and Note 3. Updated disclaimer. 3. Mar 8, 218 Updated ordering information table by correcting /SAMPLE part numbers and adding Die where applicable. Updated Section 4 heading from Die and Assembly Characteristics to Die Characteristics. 2. Feb 5, 218 Changed 55mΩ to 45mΩ in the first Features bullet. 1. Jan 15, 218 Updated Figure 1. Added ISL7324SEH part to datasheet. Ordering Information table on page 2 and updated Note 2. Added Table of Differences on page 2. Electrical Spec table - updated Note 9 on page 5. Added Die and Assembly Characteristics section on page 9. Removed About Intersil section. Updated disclaimer and moved to last page.. Oct 4, 217 Initial release FN8976 Rev.4. Page 1 of 13

11 6. Package Outline Drawing 6. Package Outline Drawing J4.A 4 PIN 9.mmx4.7mm HERMETIC SURFACE MOUNT PACKAGE Rev, 2/16 #4 GATE #3 DRAIN For the most recent package outline drawing, see J4.A. 4.7 ±.13 SOURCE #1 9. ±.13 SUBSTRATE # ±.2 PIN #1 INDEX AREA TOP VIEW END VIEW SIDE VIEW.75 TYPICAL (REF).5 ±.7 (2x).45 REF. x45 SOURCE #1 SUBSTRATE #2.7 ± ±.8 (2x) 1.9 ±.8 (4x) #4 GATE #3 DRAIN.1 TYPICAL (REF) 5.9 ±.8 (2x) BOTTOM VIEW NOTES: 1. The corner shape (radius, chamfer, etc.) may vary at the manufacturer s option from that shown on the drawing. 2. The package thickness dimension is the package height before being solder dipped. 3. Dimensions are in millimeters. FN8976 Rev.4. Page 11 of 13

12 6. Package Outline Drawing #4 GATE #3 DRAIN SOURCE #1 SUBSTRATE # TYPICAL RECOMMENDED LAND PATTERN FN8976 Rev.4. Page 12 of 13

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AUTOMOTIVE GRADE. A I DM Pulsed Drain Current P A = 25 C Maximum Power Dissipation 2.0 P A = 70 C Maximum Power Dissipation 1.

AUTOMOTIVE GRADE. A I DM Pulsed Drain Current P A = 25 C Maximum Power Dissipation 2.0 P A = 70 C Maximum Power Dissipation 1. AUTOMOTIVE GRADE Features Advanced Planar Technology Ultra Low On-Resistance Logic Level Gate Drive Dual N and P Channel MOSFET Surface Mount Available in Tape & Reel 5 C Operating Temperature Lead-Free,