I block CLK 1 CLK 2. Oscillator - Delay block. circuit. US Al. Jun.28,2011 P21 P11 P22 P12. PlN P2N. (19) United States

Transcription

1 (19) United States c12) Patent Application Pblication Wang et al US Al (1) Pb. o.: US 212/27143 A1 (43) Pb. Date: Feb. 2, 212 (54) CLOCK GEERATOR FOR GEERATG OUTPUT CLOCK HAVG O-HARMOC RELATOSHP WTH PUT CLOCK AD RELATED CLOCK GEERATG METHOD THEREOF (76) nventors: (21) Appl. o.: (22) Filed: Chi-Hseh Wang, Kaohsing City (TW); Robert Bogdan Staszewski, Delft (L) 13/17,197 Jn.28,211 Related U.S. Application Data (6) Provisional application o. 61/368,15, filed on Jl. 27, 21. Pblication Classification (51) nt. Cl. H4L 71 (26.1) (52) U.S. Cl.. 375/354 (57) ABSTRACT One clock generator incldes an oscillator block, a delay circit, and an otpt block. The oscillator block provides a first clock of mltiple phases. The delay circit delays at least one of said mltiple phases of said first clock to generate a second clock of mltiple phases. The otpt block generates a third clock by selecting signals from said mltiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator incldes an oscillator block and an otpt block. The oscillator block incldes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The otpt block generates a third clock by selecting signals from said mltiple phases, wherein said third clock has non-harmonic relationship with said first clock. 11 CLK ( ( P11 -- P Oscillator - Delay block. circit Pl P21 CLK 2 16 ( P22 -_ Otpt CL K3. block P2 --

2 Patent Application Pblication Feb. 2, 212 Sheet 1 of 13 US 212/27143 A1 /1 CLK 1 CLK ( P11 _ ( P P22 P12 _ - CL. circit. block K3 Oscillator. -- Delay. -- Otpt block Pl P ( FG. 1

3 l , r - { , { r : Xl : +: : X2: '.,., Freqency : Xl : Q+: T1/12 divider ' X 2. -' L L _J FG. 2 sc 232 L MUX OUT Controller Toggle circit x3 _j '"= ('D = 'e (') - = '"= " (') - = ""f'j ('D?' rfj ('D = ('D (.H c rfj..._ -l.j;o. (.H >

4 Patent Application Pblication Feb. 2, 212 Sheet 3 of 13 US 212/27143 A1 X1: + < TJ/12 > :s T! > X :Q+ L 1<T1/6 X: r-1 :>1 X2 : Q+' J X2 : 1- '------, < ' '1 MUX OUT Q+' 1-' + Q+'l 1-' + Q+' 1-' + Q+' 1-' + X3 sc Tiine t1 t2 t3 t4 ts t6 t7 ts t9 t1 t11 t12 FG. 3

5 block -----, Oscillator x, : l ' 2 MUX_OUT_; Togge T circit Second Control : nit : ii--+-j 2\..., T!/4 SC t : T!/4 : L- _-_...J '----- : X4 : D' MUX OUT2 434 FG. 4 First Control nit 1\ J 436 J ----================================== X3 '"= ('D = 'e (') - = '"= " (') - = ""f'j ('D?' rfj ('D = ('D.j;o. (.H c rfj..._ -l.j;o. (.H >

6 .. Patent Application Pblication Feb. 2, 212 Sheet 5 of 13 US 212/27143 A1 '< Tl > > < X1: + _j : Xt: 1- X2: A T 2 li '----i ' >: < Tt/4 _j L..! X2:B X2: D X4: A' X4: C' X4: B' X4: D' > :< J,A Mx_oTU Tt/4 ><j A.. B U >< >< B' >< C' MUX OUT2 : ' Time t4 ts FG. 5 c><' D L..! >' L : D': ' ts

7 ( 62 - L - Xt: + Xt :Q+ Freqency divider Xt : tt:+ : r l, : r------l , 632 (6 ' =:;:;.X3 '"= ('D = 'e (') - = '"= " (') - = ""f'j ('D?' Xt: Q- L FG. 6 sc 636 Controller L J rfj ('D = ('D \ (.H c rfj..._ -l.j;o. (.H >

8 Patent Application Pblication Feb. 2, 212 Sheet 7 of 13 US 212/27143 A1 X1: + X1:Q+ X1: - X1: Q- n n!< E:: >!< 1-E:: >! Q- Q+ Q- Q+ Q X2: n mrn Ft:J T1/12 :<E:: LJ X2: ' X2: Q' X3 Q' ' 1-E:: <E:: :<E:: n Time t 1 t2 t3 FG. 7

9 Patent Application Pblication Feb. 2, 212 Sheet 8 of 13 US 212/27143 A r ,1 """" --.,. lo _.j - lo - -l >< co -l >< (/) E- 1 >< +-'.. :::::l ;... Q..) -bj) bj) E- '- C' >< """"

10 Patent Application Pblication Feb. 2, 212 Sheet 9 of 13 US 212/27143 A1 c -----, co c -----, co ' , co E- co 1 X X X X X :E CV) X

11 Patent Application Pblication Feb. 2, 212 Sheet 1 of 13 US 212/27143 A1 r ,1 >< (Y) D,..;,..; l l >< o::l l """'"',..; --r--1 1,..; C\..11 D,..;,..; C\ !,..;,..; D,..;,..; >< <( >< <( l >< U) l co l C' >< J \.--. Q),, \ '. ) """'"',..;

12 Patent Application Pblication Feb. 2, 212 Sheet 11 of 13 US 212/27143 A1 <r: l co l <r: <r: co l. <r: l <r: l co l <r: l l l + <r: co <r: co (V) C'.] >< >< >< >< >< >< >< >< >< <r:

13 12\ Channel FCW FREF (f R) fr Digital loop filter r i ADJ 1 'r _- l : Oscillator 1 Q+ > block L , rr=---- =.-_- =.-- =-- =-- =-- =.-_- =.-_- =-- =.--l-- l : 1244 :: ADJ_2 : Selector 1 121, , OFF ',' 1 CKR CKV'(fv'), J : 1223 : :S,j sc \ 1,.>t> T_ogge 1:: ---x 3 CirCUit L : Controller, CKR 1242 : L J --- _j ; 8 i ' f ADJ 1 ADJ 2: FG '"= ('D = 'e (') - = '"= " (') - = ""f'j ('D?' rfj ('D = ('D (.H c rfj..._ -l.j;o. (.H >

14 Patent Application Pblication Feb. 2, 212 Sheet 13 of 13 US 212/27143 A1 Delay error (T t/6) Calibration time FG. 13 (26MHz cycle) Delay error (Tt/12) L L '+--' FG. 14 Calibration time (26MHz cycle)

15 US 212/27143 A 1 Feb.2,212 CLOCK GEERATOR FOR GEERATG OUTPUT CLOCK HAVG O-HARMOC RELATOSHP WTH PUT CLOCK AD RELATED CLOCK GEERATG METHOD THEREOF Cross Reference To Related Applications [1] This application claims the benefit of U.S. provisional application o. 61/368,15, filed on Jl. 27, 21 and incorporated herein by reference. BACKGROUD [2] The disclosed embodiments of the present invention relate to generating a clock signal, and more particlarly, to a clock generator for generating an otpt clock having nonharmonic relationship with an inpt clock and related clock generating method thereof. [3] With the development of the semicondctor technology, more and more fnctions are allowed to be spported by a single electronic device. For example, a mlti-radio combo-chip prodct may spport a plrality of commnication protocols. All of the radio-freqency (RF) oscillators shold be properly designed to avoid conflicting with each other. Specifically, good isolation is reqired, and injection plling among oscillators of different radios shold be prevented. For example, the plling of one LC-tank oscillator de to the strong harmonic of the power amplifier (PA) otpt shold be avoided; besides, the plling of one LC-tank oscillator de to a local oscillator (LO) signal or PA signal of another integrated radio shold be avoided. Ths, it reslts in a complicated freqency plan and difficlt local oscillator design, especially in analog circits. n a case where the analog approach is employed, it reqires conventional analog blocks sch as freqency divider( s) and mixer(s) which limit the freqency offset ratio to a rational nmber, and reqires an LC-tank for nwanted side-band spr sppression which inevitably consmes large area and crrent. [4] Ths, there is a need for an innovative non-harmonic clock generator design which may employ a digital realization for generating an otpt clock having non-harmonic relationship with an inpt clock throgh freqency translation that tilizes an edge rotator operating on mltiple phases of an oscillator, and may also employ an atonomos calibration process to compensate for phase errors by calibrating timing mismatch of the edge rotator. SUMMARY [5] n accordance with exemplary embodiments of the present invention, a clock generator for generating an otpt clock having non-harmonic relationship with an inpt clock and related clock generating method thereof are proposed. [6] According to a first aspect of the present invention, an exemplary clock generator is disclosed. The exemplary clock generator incldes an oscillator block, a delay circit, and an otpt block. The oscillator block is arranged to provide a first clock of mltiple phases. The delay circit is arranged to delay at least one of said mltiple phases of said first clock to generate a second clock of mltiple phases. The otpt block is arranged to receive said second clock and generate a third clock by selecting signals from said mltiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. [7] According to a second aspect of the present invention, an exemplary clock generator is disclosed. The exemplary clock generator incldes an oscillator block and an otpt block. The oscillator block is arranged to provide a second clock of mltiple phases. The oscillator block incldes oscillator arranged to provide a first clock, and a delay locked loop (DLL) arranged to generate said second clock according to said first clock. The otpt block is arranged to receive said second clock and generate a third clock by selecting signals from said mltiple phases, wherein said third clock has non-harmonic relationship with said first clock. [8] According to a third aspect of the present invention, an exemplary clock generating method is disclosed. The exemplary clock generating method incldes: providing a first clock of mltiple phases; delaying at least one of said mltiple phases of said first clock to generate a second clock of mltiple phases; and generating a third clock by selecting signals from said mltiple phases of said second clock. Said third clock has non-harmonic relationship with said first clock. [9] According to a forth aspect of the present invention, an exemplary clock generating method is disclosed. The exemplary clock generating method incldes: providing a second clock of mltiple phases, comprising providing a first clock, and tilizing a delay locked loop (DLL) to generate said second clock according to said first clock; and generating a third clock by selecting signals from said mltiple phases, wherein said third clock has non-harmonic relationship with said first clock. [1] These and other objectives of the present invention will no dobt become obvios to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illstrated in the varios figres and drawings. BREF DESCRPTO OF THE DRAWGS [11] FG. 1 is a block diagram illstrating a generalized clock generator according to an exemplary embodiment of the present invention. [12] FG. 2 is a diagram illstrating a clock generator according to a first exemplary embodiment of the present invention. [13] FG. 3 is a diagram illstrating a first clock, a second clock, a mltiplexer otpt, a third clock, and a control signal shown in FG. 2. [14] FG. 4 is a diagram illstrating a clock generator according to a second exemplary embodiment of the present invention. [15] FG. 5 is a diagram illstrating a first clock, a second clock, a forth clock, a first mltiplexer otpt, a third clock, and a second mltiplexer otpt shown in FG. 4. [16] FG. 6 is a diagram illstrating a clock generator according to a third exemplary embodiment of the present invention. [17] FG. 7 is a diagram illstrating a first clock, mltiplexer otpts, a second clock, and a third clock shown in FG. 6. [18] FG. 8 is a diagram illstrating one implementation of a delay-locked loop (DLL) based non-harmonic clock generator according to an exemplary embodiment of the present invention. [19] FG. 9 is a diagram illstrating a first clock, a second clock, a mltiplexer otpt, and a third clock shown in FG. 8.

16 US 212/27143 A 2 Feb.2,212 [2] FG. 1 is a diagram illstrating another implementation of a DLL based non-harmonic clock generator according to an exemplary embodiment of the present invention. [21] FG. 11 is a diagram illstrating a first clock, a second clock, and a third clock shown in FG. 1. [22] FG.12 is a diagram illstrating an all-digital phaselocked loop (ADPLL) employing a non-harmonic clock generator and with delay calibration according to an exemplary embodiment of the present invention. [23] FG. 13 is a diagram illstrating an exemplary delay calibration simlation reslt of a delay vale set to one adjstable delay cell. [24] FG. 14 is a diagram illstrating an exemplary delay calibration simlation reslt of a delay vale set to another adjstable delay cell. DETALED DESCRPTO [25] Certain terms are sed throghot the description and following claims to refer to particlar components. As one skilled in the art will appreciate, manfactrers may refer to a component by different names. This docment does not intend to distingish between components that differ in name bt not fnction. n the following description and in the claims, the terms "inclde" and "comprise" are sed in an open-ended fashion, and ths shold be interpreted to mean "inclde, bt not limited to... ".Also, the term "cople" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is electrically connected to another device, that connection may be throgh a direct electrical connection, or throgh an indirect electrical connection via other devices and connections. [26] n accordance with exemplary embodiment of the present invention, the freqency translation sed for generating an otpt clock having non-harmonic relationship with an inpt clock is realized sing an edge synthesizer based on edge selection and delay adjstment. For example, the new edge may be created by certain delay mechanism, sch as a delay line or a delay-locked loop. The offset freqency may be programmable by selecting the edge transversal pattern and properly adjsting the delay vales. Besides, the phase error/delay mismatch reslted from an incorrect delay vale setting or other factor( s) may be detected and calibrated by the proposed atonomos calibration process. The proposed non-harmonic clock generator has a flexible freqency plan for spr avoidance, and is sitable for any freqency ratio needed. Moreover, the proposed non-harmonic clock generator has a simple circit design de to the fact that an edge synthesizer for selection of varios clock phases is employed to replace the analog mixer of the conventional analog approach that reqires additional filtering to remove mixing sprios prodcts and consmes large crrent and circit area. The proposed non-harmonic clock generator may be employed in a wireless commnication application, sch as a mlti-radio combo-chip prodct. However, this is not meant to be a limitation of the present invention. Any application sing the proposed non-harmonic clock generator for providing an otpt clock having non-harmonic relationship with an inpt clock falls within the scope of the present invention. Technical featres of the proposed non-harmonic clock generator are detailed as below. [27] FG. 1 is a block diagram illstrating a generalized clock generator according to an exemplary embodiment of the present invention. The clock generator 1 incldes an oscillator block 12, a delay circit 14, and an otpt block 16. The oscillator block 12 is arranged to provide a first clock CLK1 of mltiple phases P 1 P w..., P 1 " The delay circit 14 is copled to the oscillator block 12, and arranged to delay at least one of the mltiple phases P 11 -P 1 of the first clock CLK1 to generate a second clock CLK2 of mltiple phases P 2 P 22,..., P 2 " The otpt block 16 is copled to the delay circit 14, and arranged to receive the second clock CLK2 and generate a third clock CLK3 by selecting signals from the mltiple phases P 21 -P 2 of the second clock CLK2. t shold be noted that the third clock CLK3 has non-harmonic relationship with the first clock CLKl. By way of example, bt not limitation, the non-harmonic relationship means clock edges of the third clock CLK3 are not statically aligned with that of the first clock CLK1, or the clock freqencies of the third clock CLK3 and the first clock CLK1 have a non-integer ratio. With the delay circit 14 inserted between the oscillator block 12 and the otpt block 16 for delaying at least one of the phases provided by the oscillator block 12, desired phases needed by the otpt block 16 are generated. The oscillator block 12 may be implemented by any available oscillator that is capable of providing a mlti -phase clock otpt. n one exemplary design, the oscillator block 12 may be implented by an LC-tank oscillator core followed by an edge djvjder. For example, the oscillator block 12 can comprise an oscillator circit prodcing a differential signal followed by a divideby-two circit prodcing a qadratre clock otpt. Alternatively, the LC-tank oscillator can be followed by one or more delay cells. t needs to be emphasized that, in general, a delay can be achieved either by reclocking a signal (edge division falls into this category) or throgh propagation delay (delay elements, sch as inverters, bffers, delay lines fall into this category). Ths, at least one of the mltiple phases of the first clock is generated by clock edge division or by delaying another of the mltiple phases of the first clock with a phase offset, where the phase offset is determined by a relationship between a freqency of the first clock CLK1 and a freqency of the third clock CLK3. Frther details of the clock generator 1 are described as below. [28] Please refer to FG. 2, which is a diagram illstrating a clock generator according to a first exemplary embodiment of the present invention. The implementation of the exemplary clock generator 2 is based on the strctre shown in FG. 1, and therefore has an oscillator block 22, a delay circit 224, and an otpt block 26. n this exemplary embodiment, the oscillator block 22 is realized by an oscillator core 212 sch as a digitally-controlled oscillator (DCO) with a tning word inpt (not shown), and a freqency divider 214 arranged to provide a first clock X 1 with mltiple phases according to an otpt of the oscillator core 212. As shown in the figre, the first clockx 1 incldes qadratre clock signals +, Q+, and -, where the clock signals + and Q+ have a 9-degree phase difference therebetween, and the clock signals + and - have a 18-degree phase difference therebetween. t shold be noted that the implementation of the oscillator block 22 is not limited to a combination of the oscillator core 212 and the freqency divider 214. n an alternative design, the oscillator block 22 may be implemented by the oscillator core 212 for generating the clock signal + with a period eqal to T 1, and a plrality of delay cells with predetermined delay vales (e.g.,!!_ and "!i) 4 2

17 US 212/27143 A 3 Feb.2,212 applied to the clock signal + to thereby generate the clock signals Q+ and -. The same objective of providing a mltiphase clock otpt is achieved. [29] The delay circit 24 incldes a first delay cell 222 and a second delay cell224. Spposing that the period of the first clockx 1 is T the first delay cell222 is arranged to apply a delay vale to the incoming clock signal Q+, and the second delay cell 224 is arranged to apply a delay vale to the incoming clock signal -. Therefore, the second clock X 2 incldes clock signals +, Q+', and -' with different phases. [3] The otpt block 26 incldes a mltiplexer 232, a toggle circit 234, and a controller 236. The mltiplexer 232 is arranged to generate a mltiplexer otpt MUX_OUT by mltiplexing the mltiple phases of the second clock X 2 according to a control signal SC. The controller 236 is arranged to receive the mltiplexer otpt MUX_OUT and generate the control signal SC according to the mltiplexer otpt MUX_OUT. For example, the controller 236 in this exemplary embodiment may be implemented by a modlo-3 conter. Therefore, de to the conter vale seqence prodced by the modlo-3 conter as the control signal SC, the mltiplexer 232 wold otpt the clock signals +, Q+', and -' as its otpt, cyclically. The toggle circit 234 is arranged to receive the mltiplexer otpt MUX_OUT and generate a third clock X 3 according to the mltiplexer otpt MUX_ OUT. More specifically, the third clock X 3 is toggled (i.e., change its otpt logic level from "" to "1" or vice versa) when the toggle circit 234 is triggered by the mltiplexer otpt MUX_OUT. For example, the toggle circit 234 may be implemented by at flip-flop which is triggered by rising edges of the mltiplexer otpt MUX_OUT. [31] Please refer to FG. 3 in conjnction with FG. 2. FG. 3 is a diagram illstrating the first clock X the second clock X 2, the mltiplexer otpt MUX_ OUT, the third clock X 3, and the control signal SC. As can be seen from FG. 3, there is a phase difference between the clock signals Q+ and Q+' de to the intentionally applied delay vale and there is a phase difference between the clock signals l and -' de to the intentionally applied delay vale plexer otpt MUX_ OUT. At time t 2, the clock signal Q+' has a rising edge which triggers both of the toggle circit 234 and the controller 236. Therefore, the third clock X 3 has a transition from a low logic level "" to a high logic level "1", and the control signal SC is pdated by a conter vale "2". As a reslt, the mltiplexer 232 otpts the clock signal -' as the mltiplexer otpt MUX_OUT. At time t 3, the clock signal -' has a rising edge which triggers both the toggle circit 234 and the controller 236. Therefore, the third clock X 3 has a transition from the high logic level "1" to the low logic level "", and the control signal SC is pdated by a conter vale "". As a reslt, the mltiplexer 232 otpts the clock signal + as the mltiplexer otpt MUX_OUT. As the following operation can be easily dedced by analogy, frther description is omitted here for brevity. Considering a case where the freqency of the first clockx 1 is MHz (i.e., T=6ps), the freqency of the generated third clockx 3 wold be 25. MHz (i.e., T 3 =4 ps). To pt it another way, the delay-line based non-harmonic clock generator shown in FG. 2 is capable of making the freqencies of the inpt clock (e.g., first clockx 1 ) and the otpt clock (e.g., third clock X 3 ) have a non-integer ratio eqal to 2/3. [32] As shown in FG. 2 and FG. 3, when switching between two clock signals fed into the mltiplexer 232 occrs, a transition from one logic level to another logic level occrs de to the clock signals having different logic levels, which may reslt in a switching glitch in the mltiplexer otpt MUX_OUT nder certain condition. To avoid this switching glitch isse, the present invention therefore proposes a modified non-harmonic clock generator with a mltiplexer which is controlled to switch from one clock signal to another clock signal when the clock signals both have the same logic level. Please refer to FG. 4, which is a diagram illstrating a clock generator according to a second exemplary embodiment of the present invention. The implementation of the exemplary clock generator 4 is also based on the strctre shown in FG. 1, and therefore has an oscillator block 42, a delay circit 44, and an otpt block 46. The oscillator block 42 is arranged to generate a first clock X 1 inclding clock signals + and -that have a 18-degree phase difference therebetween. The delay circit 44 incldes a first delay nit 412 and a second delay nit 414, wherein the first delay nit 412 has delay cells 413_1 and 413_2 inclded therein, and the second delay nit 414 has delay cells 41 5_1 and 41 5_2 inclded therein. The first delay nit 412 is arranged to delay the mltiple phases (e.g., differential phases) of the first clock X 1. n this exemplary embodiment, each of the delay cells 413_1 and 413_2 is employed to apply a delay vale T 2 to the incoming clock signal. Accordingly, the first delay nit 412 otpts clock signals +' and -' to the following signal processing stage (i.e., the second delay nit 414). [33] The second delay nit 414 is arranged to delay at least one of the mltiple delayed phases generated from the first delay nit 412. n this exemplary embodiment, each of the delay cells 415_1 and 415_2 is employed to apply a delay vale At time t the control signal SC is pdated to a conter vale "1" de to the rising edge of the clock signal +. Therefore, the mltiplexer 232 otpts the clock signal Q+' as the mlti- to an incoming clock signal. Accordingly, the second delay nit 414 otpts a second clock X 2 inclding clock signals A, B, C, D with different phases. As can be seen from FG. 4, the

18 US 212/27143 A 4 Feb.2,212 mltiple phases of the second clock X 2 inclde delayed phases (e.g., clock signals B and D) generated from delay cells 415_1, 415_2 of the second delay nit 414 and delayed phases (e.g., clock signals A and C) generated from delay cells 413_1, 413_2 of the first delay nit 412. [34] The otpt block 46 is arranged to control selection of the mltiple phases of the second clockx 2 by referring to at least the mltiple phases of the first clock X 1. As shown in FG. 4, the otpt block 46 incldes a first mltiplexer 422, a toggle circit 424, and a controller 426. The first mltiplexer 422 is arranged to generate a first mltiplexer otpt MUX_OUT1 by mltiplexing the mltiple phases of the second clock X 2 according to a first control signal SCl. The toggle circit 424 is arranged to receive the first mltiplexer otpt MUX_OUT1 and generate a third clock X 3 according to the first mltiplexer otpt MUX_OUTl. More specifically, the third clock x3 is toggled when the toggle circit 424 is triggered by the first mltiplexer otpt MUX_ OUTl. For example, the toggle circit 424 may be implemented by at flip-flop which is triggered by rising edges of the first mltiplexer otpt MUX_OUTl. [35] n this exemplary embodiment, the controller 426 is arranged to receive the first mltiplexer otpt MUX_OUT1 and the mltiple phases of the first clockx 1, and generate the first control signal SCl. As shown in FG. 4, the controller 426 incldes a third delay nit 432, a second mltiplexer 434, a first control nit 436, and a second control nit 438. The third delay nit 432 is arranged to delay at least one of the mltiple phases of the first clock X 1. n this exemplary embodiment, the third delay nit 432 incldes delay cells 433_1 and 433_2 each applying a delay vale intentionally applied delay vale T 2, there is a phase difference between the clock signals + and B de to the intentionally applied delay vale there is a phase difference between the clock signals - and C de to the intentionally applied delay vale T 2, and there is a phase difference between the clock signals - and D de to the intentionally applied delay vale Regarding the forth clock X 4, the clock signal A' is the same as the clock signal +, and the clock signal C' is the same as the clock signal -; however, there is a phase difference between the clock signals A' and B' de to the intentionally applied delay vale and there is a phase difference between the clock signals C' and D' de to the intentionally applied delay vale to an incoming clock signal. Therefore, the third delay nit 432 otpts a forth clock X 4 inclding clock signals A', B', C', D' with different phases. The second mltiplexer 434 is arranged to generate a second mltiplexer otpt MUX_ OUT2 by mltiplexing the mltiple phases of the forth clock X 4 according to a second control signal SC2, wherein the mltiple phases received by the second mltiplexer 434 inclde delayed phases (e.g., clock signals B' and D') generated from delay cells 433 _1, 433 _2 of the third delay nit 432 and the mltiple phases (e.g., A' and C') of the first clock X 1. [36] The first control nit 436 is arranged to receive the second mltiplexer otpt MUX_OUT2 and accordingly generate the first control signal SC1 to the first mltiplexer 422. Similarly, the second control nit 438 is arranged to receive the first mltiplexer otpt MUX_OUT1 and accordingly generate the second control signal SC2 to the second mltiplexer 434. For example, the first control nit 436 and the second control nit 438 may be implemented by modlo-4 conters, which otpt conter vales as the desired control signals. [37] Please refer to FG. 5 in conjnction with FG. 4. FG. 5 is a diagram illstrating the first clock Xv the second clock X 2, the forth clock X 4, the first mltiplexer otpt MUX_OUT1, the third clock X 3, and the second mltiplexer otpt MUX_OUT2. As can be seen from FG. 5, there is a phase difference between the clock signals +and A de to the [38] Sppose that the first control signal SC1 is initialized by a conter vale "", and the second control signal SC2 is initialized by a conter vale "". Ths, before time t 1, the first mltiplexer 422 otpts the clock signal A as the first mltiplexer otpt MUX_OUT1, and the second mltiplexer 434 otpts the clock signal D' as the second mltiplexer otpt MUX_OUT2. At time tv the second control nit 438 and the toggle circit 424 are both triggered by the rising edge of the clock signal A. Therefore, the third clock X 3 has a transition from a low logic level "" to a high logic level "1", and the second control signal SC2 is pdated by a conter vale" 1 ".Therefore, the second mltiplexer 434 now otpts the clock signal A' as the second mltiplexer otpt MUX_ OUT2. Please note that both of the clock signals D' and A' have the same logic level "1" at the mltiplexer switching timing (i.e., t 1 ) sch that the nwanted switching glitch is avoided. [39] At time t 2, the first control nit 436 is triggered by the rising edge of the clock signal A'. Therefore, the first control signal SC1 is pdated by a conter vale "1", and the first mltiplexer 422 now otpts the clock signal Bas the first mltiplexer otpt MUX_ OUT1. Please note that both of the clock signals A and B have the same logic level "" at the mltiplexer switching timing (i.e., t 2 ) sch that the nwanted switching glitch is avoided. At time t 3, the second control nit 438 and the toggle circit 424 are both triggered by the rising edge of the clock signal B. Therefore, the third clockx 3 has a transition from the high logic level "1" to the low logic level "", and the second control signal SC2 is pdated by a conter

19 US 212/27143 A 5 Feb.2,212 vale "2". The second mltiplexer 434 now otpts the clock signal B' as the second mltiplexer otpt MUX_OUT2. Please note that both of the clock signals A' and B' have the same logic level "1" at the mltiplexer switching timing (i.e., t 3 ) sch that the nwanted switching glitch is avoided. As the following operation can be easily dedced by analogy, frther description is omitted here for brevity. [4] As can be seen from FG. 5, the delay-line based non-harmonic clock generator shown in FG. 4 is capable of making the freqencies of the inpt clock (e.g., the first clock X 1 ) and the otpt clock (e.g., the third clock X 3 ) to be a non-integer ratio eqal5/2. t shold be noted that1: 2 <T 1, and the vale oh 2 may comfortably separate the timing of the first and second control nits 436 and 438. As the first mltiplexer otpt MUX_OUTl of the first mltiplexer 422 is sed to control the inpt selection of the second mltiplexer 434 and the second mltiplexer otpt MUX_OUT2 of the second mltiplexer 434 is sed to control the inpt selection of the first mltiplexer 422, the switching glitch isse is solved. [41] The clock generator configration shown in FG. 4 is capable of avoiding occrrence of the switching glitch. However, this is for illstrative prposes only, and is not meant to be a limitation of the present invention. Using other clock generator configration to solve the switching glitch isse is also feasible. Please refer to FG. 6, which is a diagram illstrating a clock generator according to a third exemplary embodiment of the present invention. The implementation of the exemplary clock generator 6 is also based on the strctre shown in FG. 1, and therefore has an oscillator block 62, a delay circit 64, and an otpt block 66. n this exemplary embodiment, the oscillator block 62 is realized by an oscillator core (e.g., a DCO) 612, a freqency divider 614, and a swapping circit 616. The freqency divider 614, which cold be realized as an edge divider, is arranged to provide a first clock xl with mltiple (e.g., qadratre) phases according to an otpt of the oscillator core 612. As shown in the figre, the first clock xl incldes clock signals +, Q+, -, and Q-, where the clock signals + and Q+ have a 9-degree phase difference therebetween, the clock signals and Q- have a 9-degree phase difference therebetween, the clock signals + and - have a 18-degree phase difference therebetween, and the clock signals Q+ and Q- have a!sodegree phase difference therebetween. [42] The swapping circit 616 is arranged to otpt selected phases by alternately selecting a first set of phases from the mltiple phases of the first clockx 1 and a second set of phases from the mltiple phases of the firstclockx 1. n this exemplary embodiment, the swapping circit 616 incldes a toggle circit 617 and a plrality of mltiplexers 618 and 619. The toggle circit 617 may be implemented by a T flip-flop, which is triggered by rising edges of the clock signal +. Therefore, dring one period of the clock signal +, the mltiplexers 618 and 619 otpt selected phases by selecting the clock signals + and Q+ as respective mltiplexer otpts and Q, and dring another period of the clock signal +, the mltiplexers 618 and 619 pdate the selected phases by selecting the clock signals - and Q- as respective mltiplexer otpts and Q. [43] The swapping circit 616 otpts the selected phases of the mltiple phases of the first clock xl to the following delay circit 64. n this exemplary embodiment, the delay circit 64 incldes a first delay cell 622 and a second delay cell 624. Spposing that the period of the first clock X 1 is T 1, the first delay cell 622 is arranged to apply a delay vale to the incoming mltiplexer otpt, and the second delay cell 624 is arranged to apply a delay vale to the incoming mltiplexer otpt Q. As shown in FG. 6, the second clock X 2 incldes clock signals, ', and Q' with different phases. [44] The otpt block 66 incldes a mltiplexer 632 and a controller 636. The mltiplexer 632 is arranged to generate a third clock X 3 by mltiplexing the mltiple phases of the second clock X 2 according to a control signal SC. The controller 636 is arranged to receive the third clock X 3 and generatethe control signal SC according to thethirdclockx 3. For example, the controller 636 in this exemplary embodiment may be implemented by a modlo-3 conter. Therefore, de to the conter vale seqence prodced from the modlo-3 conter, the mltiplexer 632 wold otpt the clock signals Q', ', and as its otpt, cyclically. [45] Please refer to FG. 7 in conjnction with FG. 6. FG. 7 is a diagram illstrating the first clock X 1, the mltiplexer otpts and Q, the second clock X 2, and the third clock Xy As can be seen from FG. 7, the mltiplexer otpt is set by the clock signals - and +, alternately; and the mltiplexer otpt Q is set by the clock signals Q- and Q+, alternately. Besides, there is a phase difference between the clock signals Q and Q' de to the intentionally applied delay vale and there is a phase difference between the clock signals and ' de to the intentionally applied delay vale The controller 636 may be a modlo-3 conter triggered by rising edges of the third clock X 3. Ths, the mltiplexer 632 otpts the clock signals Q', ' and, cyclically. [46] nitially, the mltiplexers 618 and 619 otpt clock signals + and Q+, respectively; and the mltiplexer 632 otpts the clock signal Q' as the third clock x3 de to the control signal SC set by a conter vale "". At time t 1, the toggle circit 617 is triggered by the rising edge of the clock signal +. Therefore, the mltiplexers 618 and 619 otpt clock signals - and Q-, respectively. At time t 2, the third clock x3 has a transition from the low logic level "" to the high logic level" 1 ", and the controller 636 is triggered by the rising edge of the clock signal Q'. Therefore, the control

20 US 212/27143 A 6 Feb.2,212 signal SC is pdated by a conter vale "1". Accordingly, the clock signal ' is selected by the mltiplexer 632 to act as its otpt. As shown in FG. 7, both of the clock signals Q' and ' have the same logic level "1" at the mltiplexer switching timing (i.e., jst after t 2 ) sch that the nwanted switching glitch is avoided. At time t 3, the third clock X 3 has a transition from the low logic level "" to the high logic level" 1 ", and the controller 636 is triggered by the rising edge of the clock signal '. Therefore, the control signal SC is pdated by a conter vale "2". Accordingly, the clock signal is selected by the mltiplexer 632 to act as its otpt. As shown in FG. 7, both of the clock signals ' and have the same logic level "1" at the mltiplexer switching timing (i.e., jst after t 3 ) sch that the nwanted switching glitch is avoided. As the following operation can be easily dedced by analogy, frther description is omitted here for brevity. [47] As can be seen from FG. 7, the delay-line based non-harmonic clock generator shown in FG. 6 is capable of making the freqencies of the inpt clock (e.g., the first clock X 1 ) and the otpt clock (e.g., the third clock X 3 ) have a non-integer ratio eqal to 2/3 which is different from that of the aforementioned clock generators 2 and 4. n other words, with a proper design of the clock generator, any noninteger ratio of inpt clock's freqency to otpt clock's freqency can be realized. [48] n above exemplary embodiments, varios designs of a delay-line based non-harmonic clock generator for generating an otpt clock having non-harmonic relationship with an inpt clock are proposed. However, this is for illstrative prposes only, and is not meant to be a limitation of the present invention. That is, sing other clock generator configrations for generating an otpt clock having non-harmonic relationship with an inpt clock is feasible. Please refer to FG. 8, which is a diagram illstrating one implementation of a delay-locked loop (DLL) based non-harmonic clock generator according to an exemplary embodiment of the present invention. The clock generator 8 incldes an oscillator circit 812, a delay circit (e.g., a DLL 814) that niformly interpolates between the oscillator circit edges, and an otpt block 84. ote, the oscillator circit 812 and delay circit 814 can be conveniently arranged to form an oscillator/interpolator block 82. The oscillator/interpolator block 82 is arranged to provide a second clock X 2 of mltiple phases. n this exemplary embodiment, the second clock X 2 incldes clock signals A, B, and C with different phases. As shown in FG. 8, the oscillator/interpolator block 82 incldes the oscillator circit (e.g., a DCO) 812 arranged to provide a first clock X 1, and the D LL 814 arranged to generate the second clock X 2 according to the first clock X 1. The DLL 814 incldes a plrality of delay elements 815_1, 815_2, and 815_3, and a phase detector (PD) 816 arranged to compare the phase of one DLL otpt (e.g., the clock signal A) to the inpt clock (e. g., the first clock X 1 ) to generate an error signal which is then fed back as the control to all of the delay elements 815 _1-815 _3. Please note that the nmber of delay elements implemented in the DLL 814 is adjstable, depending pon the actal design reqirement/consideration. As a person skilled in the art shold readily nderstand details of the DLL 814, frther description is omitted here for brevity. [49] The otpt block 84 is arranged to receive the second clock x2 and generate a third clock x3 by selecting signals from the mltiple phases of the second clock X 2. t shold be noted that the third clock X 3 has non-harmonic relationship with the first clockx 1. n this exemplary embodi- ment, the otpt block 84 incldes a mltiplexer 822, a controller 824, and a toggle circit 826. The mltiplexer 822 is arranged to generate a mltiplexer otpt MUX_OUT by mltiplexing the mltiple phases of the second clock X 2 according to a control signal SC. The controller 824 is arranged to receive the mltiplexer otpt MUX_OUT and generate the control signal SC according to the mltiplexer otpt MUX_OUT. The toggle circit 826 is arranged to receive the mltiplexer otpt MUX_OUT and generate the third clock X 3 according to the mltiplexer otpt MUX_ OUT. More specifically, the third clock X 3 is toggled when the toggle circit 826 is triggered by the mltiplexer otpt MUX_OUT. For example, the toggle circit 826 may be implemented by a T flip-flop which is triggered by rising edges of the mltiplexer otpt MUX_OUT. ote that the toggle circit can conveniently inclde circitry to generate mltiple phases of its otpt clock. [5] Please refer to FG. 9 in conjnction with FG. 8. FG. 9 is a diagram illstrating the first clock X the second clock X 2, the mltiplexer otpt MUX_OUT, and the third clock X 3. As shown in the figre, the mltiplexer otpt MUX_ OUT is cyclically set by the clock signals A, B, and C nder the control of the controller (e.g., a modlo-3 conter) 824. As a person skilled in the art can readily nderstand the generation of the third clock X 3 shown in FG. 9 after reading above paragraphs directed to FG. 3, frther description is omitted here for brevity. Considering a case where the freqency of the first clock X 1 is 3.2 GHz, the freqency of the generated third clock X 3 wold be 2.4 GHz. To pt it another way, the DLL based non-harmonic clock generator shown in FG. 8 is capable of making the freqencies of the inpt clock (e.g., the first clock X 1 ) and the otpt clock (e.g., the third clock X 3 ) have a non-integer ratio eqal to 4/3. [51] Please refer to FG. 1, which is a diagram illstrating another implementation of a DLL based non-harmonic clock generator according to an exemplary embodiment of the present invention. The clock generator 1 incldes an oscillator circit 112, a delay circit (e.g., a DLL 114) that generates mltiple edges throgh interpolation of its inpt clock, and an otpt block 14. The oscillator block 112 and the delay circit (e.g., the DLL 114) are conveniently combined into a single oscillator/interpolator block 12. The oscillator/interpolator block 12 is arranged to provide a second clock X 2 of mltiple phases. n this exemplary embodiment, the second clock X 2 incldes clock signals A, -A, B, -B, C, and -C with different phases. More specifically, the clock signals A and -A are ot of phase, the clock signals Band-Bare ot of phase, and the clock signals C and-care ot of phase. As shown in the figre, the oscillator/interpolator block 13 incldes the oscillator circit (e.g., a DCO) 112 arranged to provide a first clock x1 inclding clock signals + and - that are ot of phase (i.e., 18 degrees apart), and the DLL 114 arranged to generate (throgh interpolation) the aforementioned second clock X 2 according to the first clock X 1, wherein the DLL 114 incldes a plrality of delay elements 115_1, 115_2, and 115_3, and a phase detector (PD) 116 arranged to compare the phase of one DLL otpt (e.g., the clock signal C) to the inpt clock (e.g., the clock signal +) to generate an error signal which is then fed back as the control to all of the delay elements 115_1-115_3. As a person skilled in the art shold readily nderstand details of the DLL 114, frther description is omitted here for brevity.

21 US 212/27143 A 7 Feb.2,212 [52] The otpt block 14 is arranged to receive the second clock x2 and generate a third clock x3 by selecting signals from the mltiple phases of the second clock X 2. t shold be noted that the third clock X 3 has non-harmonic relationship with the first clockx 1. n this exemplary embodiment, the otpt block 14 incldes a mltiplexer 122 and a controller 124. The mltiplexer 122 is arranged to generate the third clockx 3 by mltiplexing the mltiple phases of the second clock X 2 according to a control signal SC. The controller 124 is arranged to receive the first clock X 1 and generate the control signal SC according to the first clock X 1. For example, the controller 124 pdates the control signal SCat rising edges of the clock signals + and -. [53] Please refer to FG. 11 in conjnction with FG. 1. FG. 11 is a diagram illstrating the first clockx 1, the second clock X 2, and the third clock X 3. As shown in the figre, the mltiplexer otpt (i.e., the third clock X 3 ) is cyclically set by the clock signals A, A, -C, B, -A, -A, C, and -B nder the control of the controller 124. As a person skilled in the art can readily nderstand the generation of the third clock X 3 shown in FG. 11 after reading above paragraphs, frther description is omitted here for brevity. Considering a case where the freqency of the first clock X 1 is 3.2 GHz, the freqency of the generated third clock X 3 wold be 2.4 GHz. To pt it another way, the DLL based non-harmonic clock generator shown in FG. 8 is capable of making the freqencies of the inpt clock (e.g., the first clock X 1 ) and the otpt clock (e.g., the third clock X 3 ) have a non-integer ratio eqal to 4/3. [54] As mentioned above, the intentionally applied delay vales are sed to create the desired phases/edges needed by the following otpt block. However, the clock signals to be mltiplexed may have phase errors which wold affect the actal waveform of the otpt clock generated from the exemplary non-harmonic clock generator proposed in the present invention. Ths, there is a need for calibrating the delay vales to compensate for the delay mismatch. Please refer to FG. 12, which is a diagram illstrating an all-digital phase-locked loop (ADPLL) employing a non-harmonic clock generator and with delay calibration according to an exemplary embodiment of the present invention. TheADPLL 12 with delay calibration incldes a digital phase detector 122, a digital loop filter 124, a delay-line based non-harmonic clock generator 126, a calibration apparats 128, and ad flip-flop (DFF) 121. For clarity and simplicity, only the components pertinent to the technical featres of the present invention are shown in FG. 12. That is, in another exemplary embodiment, the ADPLL 12 may have additional components inclded therein. The general ADPLL architectre is well known in the art. [55] By way of example, bt not limitation, the delayline based non-harmonic clock generator 126 may be implemented sing the configration shown in FG. 2. Therefore, the delay-line based non-harmonic clock generator 126 incldes an oscillator block 1212 and an edge synthesizer 1214 having an edge rotator 1216 and a toggle circit 1218, wherein the edge rotator 1216 incldes a plrality of adjstable delay cells 1221 and 1222 controlled by calibration signals ADM andadj_2, a mltiplexer 1223, and a controller (e.g., a modlo-3 conter) As a person skilled in the art can readily nderstand the operation of the delay-line based non-harmonic clock generator 126 after reading above paragraphs directed to the clock generator 2 shown in FG. 2, frther description is omitted here for brevity. [56] The DFF 121 is implemented for generating a clock signal CKR sed by internal components of the AD PLL 12 according to a freqency fr of a clock reference FREF and a freqency f v' of a feedback clock CKV'. The digital PD 122 otpts phase error samples derived from a variable phase corresponding to an otpt of the edge rotator 1216 and a reference phase. For example, the reference phase is derived from the channel freqency command word (FCW) and the clock reference FREF fed into the digital PD 122, and the variable phase is derived from the feedback clock CKV' and the clock reference FREF fed into the digital PD 122. The digital loop filter 124 refers to the phase error samples generated from the digital PD 122 to generate a tning word signal to the oscillator block 1212, which may have a DCO inclded therein. As a person skilled in the art shold readily nderstand details of the digital PD 122, the digital loop filter 124, and the DFF 121, frther description is omitted here for brevity. [57] The calibration apparats 128 is implemented for calibrating timing mismatch of the edge rotator 1216 operating on mltiple phases of an oscillator (e.g., the oscillator block 1212, which may be implemented by a combination of an oscillator core and a freqency divider or a combination of an oscillator core and delay cells). The calibration apparats 128 incldes a captring block 1232 and a calibrating block The captring block 1232 is arranged to captre phase error samples generated by the digital PD 122. The calibrating block 1234 is arranged to adjst timing of the edge rotator 1216 by generating the calibration signal ADM/ ADj_2 to the adjstable delay cell1221/1222 according to the phase error samples. t shold be noted that theadpll might need to be configred to operate nder restricted FCW vales. More particlarly, the fractional part of FCW vale needs to correspond to an inverse of the period of the edge rotator. For example, the mltiplexer 1223 has three inpts and its rotational period is three. Hence, the fractional vale of FCW shold be 1/3 or 2/3. [58] n this exemplary embodiment, the captring block 1232 incldes a selector 1242, a demltiplexer (DEMUX) 1244, and a storage The nmber of phase error samples to be captred is eqal to periodicity of the edge rotator For example, the mltiplexer 1223 selects a clock inpt with no delay vale intentionally applied thereto, a clock inpt with a first delay vale intentionally applied thereto, and a clock inpt with a first delay vale intentionally applied thereto, cyclically. As the switching seqence of the mltiplexer 1223 is known beforehand, the occrrence of the phase error samples generated from the digital PD 122 is predictable. Based on sch an observation, when the control signal SC is set by a conter vale "", the selector 1242 controls the DEMUX 1244 to store a crrent phase error sample PO corresponding to the clock inpt with no delay vale applied thereto into the storage 1245; when the control signal SC is set by a conter vale "1", the selector 1242 controls the DEMUX 1244 to store a crrent phase error sample P1 corresponding to the clock inpt with the first delay vale intentionally applied thereto into the storage 1245; and when the control signal SC is set by a conter vale "2", the selector 1242 controls the DEMUX 1244 to store a crrent phase error sample P2 corresponding to the clock inpt with the second delay vale intentionally applied thereto into the storage 1245.

22 US 212/27143 A 8 Feb.2,212 [59] Regarding the calibrating block 1234, it incldes a calclating circit 1247 and an adjsting circit The calclating circit 1247 is arranged to estimate the timing mismatch of the edge rotator 1216 according to the phase error samples bffered in the storage 1245, and has a plrality of sbtractors 1246_1 and 1246_2 implemented for estimating phase errors. As the clock inpt with no delay vale intentionally applied thereto may be regarded as a clock inpt having a correct delay vale, the phase error sample PO may serve as an ideal one. Ths, the sbtractor 1246_1 calclates a difference between the phase error samples P1 and PO to represent a phase error of the clock inpt with the first delay vale intentionally applied thereto, and the sbtractor 1246_2 calclates a difference between the phase error samples P2 and PO to represent a phase error of the clock inpt with the second delay vale intentionally applied thereto. To pt it another way, the calclating circit 1247 estimates the timing mismatch of the edge rotator 1216 by calclating a difference between a phase error sample (e.g., PO) of the phase error samples and each of remaining phase error samples (e.g., P1 and P2). [6] The adjsting circit 1248 is arranged to adjst the timing of the edge rotator 1216 according to an otpt of the calclating circit More specifically, the adjsting circit 1248 controls the adjstable delay cells 1221 and 1222 to adjst the delay vales by generating the calibrating signals ADj_1 and ADj_2 to the adjstable delay cells 1221 and Please note that the calibrating signal ADj_l/ADj_2 generated from the adjsting circit 1248 does not change the delay vale set to the adjstable delay cell when the estimated phase error is zero or negligible. Moreover, the adjsting circit 1248 may be eqipped with accmlation fnctionality and follow a least mean sqare (LMS) or steepest descent algorithm, which is generally well known in the art. Ths, the estimated phase errors generated from the sbtractor 1246_1 are accmlated to alleviate the noise interference, and an accmlated phase error is referenced for controlling the calibration signal ADM. Similarly, the estimated phase errors generated from the sbtractor 1246_2 are also accmlated to alleviate the noise interference, and an accmlated phase error is referenced for controlling the calibration signal ADj_2. This also obeys the spirit of the present invention. [61] n a case where the clock signal + generated from the oscillator block 1212 may have no phase error presented therein, the corresponding captred phase error sample may eqal zero. Therefore, the calclating circit 1247 may be omitted, and the adjsting circit 1248 directly refers to the phase error samples P1 and P2 to set the calibration signals ADM andadj_2. This alternative design also falls within the scope of the present invention. [62] The calibrating block 128 does not stop adjsting/ calibrating the delay vale(s) ntil the phase errors are fond negligible. As the delay calibration is based on the actally captred phase error samples rather than predicted phase errors, the calibrating block 128 therefore stochastically redces the timing mismatch of the edge rotator 1216 throgh the adaptive delay mismatch calibration, as shown in FG. 13 and FG. 14 illstrating exemplary delay calibration simlation reslts of delay vales respectively set to the adjstable delay cells 1222 and n the exemplary delay calibrations shown in FG. 13 and FG. 14, an offseted freqency is 2451 *(4/3) MHz, a central freqency is 2451 MHz, and a reference clock freqency is 26 MHz. Ths, the FCW vale may be set by , where an integer part (i.e., 125) is derived from a floor vale of 2451 *( 4/3)/26 (i.e., l2451 *( 4/ 3)/26 J=125), and a fractional part (i.e.,.6667) is derived from 2/3. [63] Please note that the proposed atonomos calibration mechanism is not limited to theadpll application. For example, the atonomos calibration mechanism may be implemented in any PLL application which employs the proposed clock generator (e.g., the delay-line based non-harmonic clock generator 126) as long as the phase error information generated from the phase detector of the PLL circit is available to the calibration apparats. [64] Those skilled in the art will readily observe that nmeros modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosre shold be constred as limited only by the metes and bonds of the appended claims. What is claimed is: 1. A clock generator, comprising: an oscillator block, arranged to provide a first clock of mltiple phases; a delay circit, arranged to delay at least one of said mltiple phases of said first clock to generate a second clock of mltiple phases; and an otpt block, arranged to receive said second clock and generate a third clock by selecting signals from said mltiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. 2. The clock generator of claim 1, wherein said otpt block comprises: a mltiplexer, arranged to generate a mltiplexer otpt by mltiplexing said mltiple phases of said second clock according to a control signal; a controller, arranged to receive said mltiplexer otpt and generate said control signal according to said mltiplexer otpt. 3. The clock generator of claim 2, wherein said otpt block frther comprises: a toggle circit, arranged to receive said mltiplexer otpt and generate said third clock according to said mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said mltiplexer otpt. 4. The clock generator of claim 1, wherein said oscillator block comprises: an oscillator core; and a freqency divider, arranged to provide said first clock with said mltiple phases according to an otpt of said oscillator core. 5. The clock generator of claim 1, wherein said delay circit comprises: a first delay nit, arranged to generate mltiple delayed phases by delaying said mltiple phases of said first clock; and a second delay nit, arranged to generate said at least one delayed phase by delaying at least one of said mltiple delayed phases generated from the first delay nit; wherein said mltiple phases of said second clock inclde said at least one delayed phase generated from the second delay nit and at least one of said mltiple delayed phases generated from the first delay nit, and said otpt block is arranged to control selection of said mltiple phases of said second clock according to at least said mltiple phases of said first clock.

23 US 212/27143 A 9 Feb.2, The clock generator of claim 5, wherein said otpt block comprises: a first mltiplexer, arranged to generate a first mltiplexer otpt by mltiplexing said mltiple phases of said second clock according to a first control signal; a controller, arranged to receive said first mltiplexer otpt and said mltiple phases of said first clock, and generate said first control signal according to said first mltiplexer otpt and said mltiple phases of said first clock; and a toggle circit, arranged to receive said first mltiplexer otpt and generate said third clock according to said first mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said first mltiplexer otpt. 7. The clock generator of claim 6, wherein said controller comprises: a third delay nit, arranged to generate at least one delayed phase by delaying at least one of said mltiple phases of said first clock; a second mltiplexer, arranged to generate a second mltiplexer otpt by mltiplexing mltiple phases according to a second control signal, wherein said mltiple phases received by said second mltiplexer inclde said at least one delayed phase generated from said third delay nit and at least one of said mltiple phases of said first clock; a first control nit, arranged to receive said second mltiplexer otpt and generate said first control signal according to said second mltiplexer otpt; and a second control nit, arranged to receive said first mltiplexer otpt and generate said second control signal according to said first mltiplexer otpt. 8. The clock generator of claim 1, wherein said oscillator block comprises: a swapping circit, arranged to otpt selected phases to the delay circit by alternately selecting a first set of phases from said mltiple phases of said first clock and a second set of phases from said mltiple phases of said first clock. 9. The clock generator of claim 8, wherein said otpt block comprises: a mltiplexer, arranged to generate said third clock by mltiplexing said mltiple phases of said second clock according to a control signal; and a controller, arranged to receive said third clock and generate said control signal according to said third clock. 1. The clock generator of claim 1, wherein said at least one of said mltiple phases of said first clock is generated by delaying another of said mltiple phases of said first clock with a phase offset. 11. A clock generator, comprising: an oscillator block, arranged to provide a second clock of mltiple phases, comprising: an oscillator, arranged to provide a first clock; and a delay locked loop (DLL), arranged to generate said second clock according to said first clock; and an otpt block, arranged to receive said second clock and generate a third clock by selecting signals from said mltiple phases, wherein said third clock has non-harmonic relationship with said first clock. 12. The clock generator of claim 11, wherein said otpt block comprises: a mltiplexer, arranged to generate a mltiplexer otpt by mltiplexing said mltiple phases according to a control signal; and a controller, arranged to receive said mltiplexer otpt and generate said control signal according to said mltiplexer otpt. 13. The clock generator of claim 12, wherein said otpt block frther comprises: a toggle circit, arranged to receive said mltiplexer otpt and generate said third clock according to said mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said mltiplexer otpt. 14. The clock generator of claim 11, wherein said otpt block comprises: a mltiplexer, arranged to generate said third clock by mltiplexing said mltiple phases according to a control signal; and a controller, arranged to receive said first clock and generate said control signal according to said first clock. 15. A clock generating method, comprising: providing a first clock of mltiple phases; delaying at least one of said mltiple phases of said first clock to generate a second clock of mltiple phases; and generating a third clock by selecting signals from said mltiple phases of said second clock; wherein said third clock has non-harmonic relationship with said first clock. 16. The clock generating method of claim 15, wherein said step of generating said third clock comprises: generating a mltiplexer otpt by mltiplexing said mltiple phases of said second clock according to a control signal. 17. The clock generating method of claim 16, wherein said step of generating said third clock frther comprises: generating said control signal according to said mltiplexer otpt. 18. The clock generating method of claim 16, wherein said step of generating said third clock frther comprises: tilizing a toggle circit to receive said mltiplexer otpt and generate said third clock according to said mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said mltiplexer otpt. 19. The clock generating method of claim 15, wherein said step of providing said first clock of mltiple phases comprises: providing said first clock with said mltiple phases by freqency-dividing an otpt of an oscillator core circit. 2. The clock generating method of claim 15, wherein said step of delaying at least one of said mltiple phases of said first clock comprises: generating mltiple delayed phases by delaying said mltiple phases of said first clock; and generating said at least one delayed phase by delaying at least one of said mltiple delayed phases; wherein said mltiple phases of said second clock inclde said at least one delayed phase and at least one of said mltiple delayed phases, and said step of generating said third clock comprises controlling selection of said mltiple phases of said second clock according to at least said mltiple phases of said first clock.

24 US 212/27143 A 1 Feb.2, The clock generating method of claim 2, wherein said step of generating said third clock comprises: generating a first mltiplexer otpt by mltiplexing said mltiple phases of said second clock according to a first control signal; generating said first control signal according to said first mltiplexer otpt and said mltiple phases of said first clock; and tilizing a toggle circit to receive said first mltiplexer otpt and generate said third clock according to said first mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said first mltiplexer otpt. 22. The clock generating method of claim 21, wherein said step of generating said first control signal according to said first mltiplexer otpt and said mltiple phases of said second clock comprises: generating at least one delayed phase by delaying at least one of said mltiple phases of said first clock; generating a second mltiplexer otpt by mltiplexing mltiple phases according to a second control signal, wherein said mltiple phases that are mltiplexed inclde said at least one delayed phase and at least one of said mltiple phases of said first clock; generating said first control signal according to said second mltiplexer otpt; and generating said second control signal according to said first mltiplexer otpt. 23. The clock generating method of claim 15, wherein said step of providing the first clock of mltiple phases frther comprises: otptting selected phases by alternately selecting a first set of phases from said mltiple phases of said first clock and a second set of phases from said mltiple phases of said first clock. 24. The clock generating method of claim 15, wherein said step of generating the third clock comprises: generating said third clock by mltiplexing said mltiple phases of said second clock according to a control signal; and generating said control signal according to said third clock. 25. The clock generating method of claim 15, wherein said at least one of said mltiple phases of said first clock is generated by delaying another of said mltiple phases of said first clock with a phase offset. 26. A clock generating method, comprising: providing a second clock of mltiple phases, comprising: providing a first clock; and tilizing an interpolator circit to generate said second clock according to said first clock; and generating a third clock by selecting signals from said mltiple phases, wherein said third clock has non-harmonic relationship with said first clock. 27. The clock generating method of claim 26, wherein said step of generating said third clock comprises: generating a mltiplexer otpt by mltiplexing said mltiple phases according to a control signal. 28. The clock generating method of claim 27, wherein said step of generating said third clock frther comprises: tilizing a toggle circit to generate said third clock according to said mltiplexer otpt, wherein said third clock is toggled when said toggle circit is triggered by said mltiplexer otpt. 29. The clock generating method of claim 27, wherein said step of generating said third clock frther comprises: generating said control signal according to said mltiplexer otpt. 3. The clock generating method of claim 27, wherein said step of generating said third clock frther comprises: generating said control signal according to said first clock. * * * * *