Ideal Tx-Line Reflection

Transcription

1 Ideal Tx-Line Reflecion 吳瑞北 Rm. 34, Deparmen of Elecrical Engineering google: rbwu S. H. Hall e al., High-Speed Digial Design, Chap.3 N. N. Rao, Elemens of Engineering Elecromagneics, Chap. 6 1

2 Wha will you learn? How o solve circuis wih ideal lossless x-line? Is here easier analyic equ. circui model. How o solve analyically x-line circuis wih R, L, and C loading/disconinuiies? How does reflecion come from? How o deal wih muliple reflecion phenomenon? How o measure? Operaion principle of TDR. How o exrac x-line parameers & disconinuiies from TDR measuremen? How o miigae reflecion?

3 Conens Analyic Tx-Line Analysis Reflecions from Resisive Loads Reflecion from Reacive Loads Time Domain Reflecomery Terminaion Designs 3

4 Analyic Tx-Line Analysis 4

5 Disribued Elemen Tx-line is also called a disribued elemen v S () v A () i A () i(z,) + v(z,) _ i B () v B () i(z,) vs. lumped elemens Z S, Z L. Noe he reference of V(z,). Where is he ground of x-line? I(z,) mus accompany he reurn-pah curren. How o inerpre a negaive I(z,)? GROUND How o solve circuis wih a disribued circui elemen? 5

6 Eq. Circui Model for SPICE Simulaion Rule of Thumb: 1. Decide # of Noe: TD segmen segmens. Choose R, L, C,Gsegmen 1 r v p R, L, C,G* r 1 # 1 max freq. #

7 Equivalen Circui Seen from Boh Ends V V Z I I V V V V A A 1 ) (, ) ( ) (, ) ( T V T V Z I I T V T V V V B B 1 ), ( ) ( ), ( ) ( p p p p v z v z v z v z V V Z z I V V z V 1 ), ( ), ( Ref.: F. H. Branin, Jr., Transien analysis of lossless ransmission lines, Proc. IEEE, vol. 55, pp. 1-13, Nov ( ) ( ) (, ) (, ) A A V Z I V z V z T ( ) ( ) (, ) (, ) B B V Z I V z V z T ; B A V V V V V V 7

8 Circui Modeling A Z ; T B Z V A Z V B Equivalen circui Time delay Impedance Rem: Only 4 lumped elemens, even for very long x-line. E A E B * volage conrolled volage source E ( ) v ( T ) E ( T ) A B B E ( ) v ( T ) E ( T ) B A A 8

9 Time Marching A source end A load end Z s Z Z V s () V A () E A () E B () V B () Z L T T 3T V ( ) V () E () V (,) V (,) E () V () S A A B B x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 9

10 Reflecions from Resisive Loads 1

11 Time-Domain Sol. w/o Simulaor 1. Deermine launch volage & final DC or = volage. Calculae load reflecion coefficien and volage delivered o he load 3. Calculae source reflecion coefficien and resulan source volage 11

12 Deermine Launch Volage TD R g V + I + Vs Vs Rs A Zo B R V Z = I + (iniial volage) =, V=Vi R g V Z V + Z V i = V S Z + R S R V f = V S R + R S Z = Sep 1: deermine launch volage Simply a volage divider! 1

13 Volage Delivered o Load Vs Vs Rs A TD Zo B R Z V B E i R L (iniial volage) =, V=Vi (signal is refleced) =TD, V=Vi + r B (Vi ) r R Zo V B refleced = r B (V inciden ) R Zo V V V B = V inciden + V refleced I V Z V B for V d RL Z R B V L ; Sep : deermine V B a = TD Tx-line delays he arrival of launched volage unil = TD. V B for < < TD is a quiescen volage ( in his case) Volage wavefron will be refleced a x-line end V B = V inciden + V refleced a = TD 13

14 Volage Refleced back o Source Vs Vs Rs A r A Zo r B B R I A V A Z (iniial volage) =, V=Vi TD R g E r V Z = =TD, V=Vi + r B (Vi) + r A r B )(Vi ) (signal is refleced) =TD, V=Vi + r B (Vi ) 14

15 Volage Refleced Back o Source Rs r Zo V refleced = r A A (V inciden ) Rs Zo V A = V launch + V inciden + V refleced Sep 3: Deermine V A a = TD Tx-line delays he arrival of volage refleced from load unil = TD. V A a ime < < TD is a launch volage Volage wavefron will be refleced a source V A = V launch + V inciden + V refleced a = TD In seady sae, sol. converges o V B = V S [R /(R + R s )] 15

16 Laice (Bounce) Diagram 16

17 1 s Reflecion vs. 1 s Inciden Swiching Open-circuied line Γ 1 ( V V ) Terminaion by Z Γ ( V V ) Applicaions R R B B Firs reflecion swiching Firs inciden swiching 17

18 Vols v Vs Over Driven Tx-Line (Under Damped) V(source) Zo Zs TD = 5 ps V(load) r source r load 1 Time V(source) V(load) 5 ps 1 ps 15 ps ps 1.33v.v 5 ps v 1.33v -.443v -.443v.148v.148v v.66v 1.77v Assume Zs=5 ohms Zo =5ohms Vs=- vols V iniial r r source load Zo Vs Zs Zo Zs Zo Zs Zo Zl Zo Zl Zo ( ) Response from laice diagram Time, ps Source Load.7 18

19 Vols Under Driven Tx-Line (Over Damped) Vs V(source) Zo Zs TD = 5 ps V(load) Time V(source) V(load) v 5 ps.8v r. 1 source.8v.8v r load v Assume Zs=75 ohms Zo=5ohms Vs=- vols V r r iniial source load Zo 5 Vs ().8 Zs Zo 755 Zs Zo 755. Zs Zo 755 Zl Zo 5 1 Zl Zo 5 1 ps.16v 1.6v Response from laice diagram 15 ps 1.76v.16v ps.3v 1.9v 1.5 Source Load 5 ps Time, ps 19

20 Effecs of Rise Time overdriven case

21 Effecs of Rise Time underdriven case 1

22 Reflecion and Transmission Inciden 1r Transmied r Refleced Reflecion Coefficien r Z Z Z Z Transmission Coefficien =1+ r 1 Z Z Z Z Z Z Z

23 Muliple line impedance 3

24 4

25 Muli Receivers Topology -V R s =Z s l 1 Z l Z Eig 3-35 Receiver 1 l 3 > l Receiver Z T Z R s l l 5 ps; Z l 15 ps; 1 3 Z Z Z 1 1; 1 v v v ; T v v A B

26 Effecs of Non-symmery R s =Z s l 1 l Z Receiver 1 Z l 3 > l Receiver -V Z 6

27 Volage(V) Volage(V) Ringing Noise on Address Lines of DDR Z v p -1.5V Tr=ps /.5; Rs s m and.; TD L / v 1ps T L / v 14p s; l / v L 3 3 p p Z, v p, R s, and 3 p L 1 =(L -Δl)/ L =(L +Δl)/ Shor End Long End Ringing Effec Ringing Effec l/l = l/l =., Shor End 1 l/l =.6, Shor End l/l =.6, Long End.5 l/l =., Long End l/l =.4, Shor End l/l =.4, Long End.5 l/l =.8, Shor End l/l =.8, Long End ime(ns) ime(ns)

28 Volage(V) v sep (-TD) Z RLC Resonance Model of Ringing Noise The oal response can be divided ino he balanced response and he ringing noise response. The ringing noise response can be fied as a RLC resonance response T -1.5V Tr=ps -1.5V Tr=ps TD=L 3 /v p l sin L A l sin L L eq Z, L 3 Z / L v n v sin b Av n v v v l L v T 1 j Equivalen response Balanced response.884m n v eq p v Ringing noise response Sep Response, l/l =.1 Balanced Precise, shor end Model, shor end Precise, long end Model, long end Ringing ime(ns) 8

29 Eye Heigh Bi rae Influence Wors case occurs a UI/T is odd. UI/T =4, Δl/L =.1 Eye Heigh/V h % UI/T =3, Δl/L =.1 % UI/T l/l 9

30 Eye Heigh Leg Difference Influence Wors case occurs a where he max of A occurs. l L L. 1 UI/T UI/T =3, Δl/L = Eye Heigh/V h l/l UI/T =3, Δl/L =.6 % Ref: K.-Y. Yang, e al., Modeling and fas eye- diagram esimaion of ringing effecs on branch line srucures, IEEE T-CPMT, Apr % 3

31 Effec of a Long Sub 31

32 Reflecions from Reacive Loads 3

33 Inducive Terminaion = for T l u R V V / z = z = z 1 R z = l L L dil LL R i v V d L il( ) 1e vl( ) v( l, ) Ve V ( T ) R L R L ( T ) R L L v (, ) V for v(l,) v + (, -T) R v(l,) i L () L L v(l,) V v ( l, ) v( l, ) V for T T z l u T 1 V V / T L L R z = z 1 z = l z

34 Capaciive Terminaion = for T R V R C L v(z, 1 ) v ( l, ) v( l, ) V z 1 l u 1 T z = z = z 1 z = l V i L () V / v (, ) V for R v(l,) C L v(z 1,) z = z 1 z = l z v(l,) v + (, -T) V V V / T T 1

35 Time Domain Reflecomery 36

36 Time-Domain Reflecomery Key advanages over frequency measuremen Abiliy o exrac elecrical daa relevan o digial sysems Can exrac impedance, velociy, x-line parameers, and model parameers of disconinuiies. Basic heory Z DUT V r V Z o refleced inciden 1 r ; 1 r Z Z DUT DUT Z Z o o 37

37 a node A Impedance & Velociy 38

38 Peeling Idea for Reflecions Muliple reflecions. Need minimize reflecions prior o DUT & TDR Use a conrolled-impedance, low-loss cable bw TDR & probe Use a low-loop-inducance, conrolled-impedance probe J. M. Jong and V. K. Tripahi, IEEE T-CHMT, pp , Aug. 199 J. M. Jong, B. Janko and V. K. Tripahi, IEEE T-CHMT, pp , Feb

39 Inducive Load in Middle of a Line r max L Z r 1e L Z r v s A ind vl Z s 4 v s : exciaion volage ; 4

40 Capaciive Load in Middle of a Line C D V B -E i V r T w,5 A v Z C 4 s cap ; 43

41 Disconinuiy Loading 44

42 Equally Spaced Capaciive Loads Z 49.7 d.573ns CL pf.35ns r 45

43 FLY-BY Topology in DIM and Modeling A B C Simulaion Model hin race (race widh: 4mil) f= 8 MHz Tr=15 ps Volage = 1.5v + A _ R1= 4 ohm Microsrip (1 mil) hick race (1mil) Sripline (1 mil) + B _ sripline (4 mil) R R R R R R R R L L L L L L L L Package + C _ R= 4 ohm C C C C C C C C TDR a A and TDT a B will be considered under DDR3 o discuss effecs of FLY-BY race design (widh 1mil vs. 4mil). 46

44 Volage (V) Volage (V) Simulaion A race widh Resuls R1= 4 ohm Microsrip (1 mil) f= 8 MHz Tr=15 ps Sripline (1 mil) sripline (4 mil) + B _ R L C R L C R= 4 ohm TDR 1 VA TDT 1 VB Trace Widh = 4 mil Trace Widh = 1 mil. Trace Widh = 4 mil Trace Widh = 1 mil Time (nsec) Time (nsec) Suiable race widh (hin race) improves impedance mach. H.-H. Chuang, e al., Signal/power inegriy modeling of high-speed memory modules using chip-package-board co-analysis, IEEE T-EMC, May 1. 47

45 Inducance Measuremen by TDR Z Z L vs,dut ( ) vs,ref ( ) d V oc Rem.: differen formula if mached a righ end 48

46 Capaciance Measuremen by TDR Z 1 C vo,ref ( ) vo,dut ( ) d ZV oc 49

47 Terminaion Design 5

48 Terminaion Schemes o minimize reflecion noise Decrease sysem frequency Shoren PCB races Terminaion wih mached impedance Source erminaion On-die source erminaion Series source erminaion Parallel erminaion (Load erminaion) Load erminaion wih a resisive load AC load erminaion Acive erminaion Ref.: H. Johnson & M. Graham, High-Speed Digial Design, Sec

49 On-die source erminaion Source Terminaion Series source erminaion Difficul o guaranee mached buffer impedance! Add cos o board, and consumes board area! 5

50 SI is abou Finding & Fixing Problems 3 inch long PCB Trace 3 inch long PCB Trace Series erminaion (~4 Ohms) 53

51 Source Terminaion suggesed : R R Z s op overshoo T1-9. RC. ZC VDD E f Power 1 R (Pulse Freq.) R 54 f V DD

52 Load Terminaion Load erminaion wih a resisive load Power delivery and hermal problems! AC load erminaion Capacior value need be opimized for specific design Capaciive loading increases signal delay! 55

53 Load Terminaion Eq. ck C D T erm.. RC.C ( R ne riseime : L // Z erm ) 1.1Z T r C Too much power consumpion! 56

54 Spli Terminaion mach R1 // R Z P load ( V ( V HI CC V ( V ) Z V EE HI ) ( V R ) ( V R 1 LO CC V V EE LO ) ) 57

55 Load Terminaion for Muliple Lines Bifurcaed line wih mached race impedance Daisy-chain configuraion Cap. of each shor sub adds o cap. load of receiver End erminaion 58

56 AC Load Terminaion R1C clock ime Power saving (in DC-balanced circui) P R 1 Z 4 ( V / ) ( V ) Z 59

57 Mach by Series/Parallel Terminaion Parallel erminaion 6

58 Acive Terminaion 5 Ω V L H V H L 1 5 Ω /3 5 Ω TTL / CMOS L L L Clamp o -1V on HIGHo-LOW (limi signal undershoo) R L L L Suiable for any Z Power saving V oo ECL V bb.1 μf 61

59 Comparisons Rise ime of an end-erminaed circui, when capaciively loaded, is half of a series-erminaed line driving same load. Mos TTL or CMOS gaes can source enough curren o drive end erminaors. Spli erminaion or capaciive erminaion can be a remedy. One can daisy-chain receivers on an end-erminaed line. A low-pulse repeiion raes, source erminaions dissipaes lile power. Peak drive power for source-erminaed line is V 1 R same as end-erminaed line (biased a halfway poin) 6

60 Did you learn? Wha s diff. of disribued from lumped circuis? How o solve analyically x-line circuis wih R, L, and C loading/disconinuiies? Load & source reflecion coeff. & bounce diagram. Operaion principle of ime domain reflecomery. How o exrac x-line parameers & disconinuiies from TDR measuremen? How o miigae reflecion? 63

61 References & Furher Reading F. H. Breanin, Jr., Transien analysis of lossless ransmission lines, IEEE Proc. Le., pp.1-13, J. M. Jong, B. Janko, and V. K. Tripahi, Equivalen circui modeling of inerconnecs from ime-domain measuremens, IEEE T-CHMT, vol. 16, pp , Feb M.-H. Wang and R.-B. Wu, Measuring mehod for equivalen circuiry, USA Paen 6,137,93, Oc.. H.-H. Chuang, e al., Signal/power inegriy modeling of high-speed memory modules using chip-package-board coanalysis, IEEE T-EMC, vol. 5, pp , May 1. K.-Y. Yang, e al., Modeling and fas eye-diagram esimaion of ringing effecs on branch line srucures, IEEE T-CPMT, Apr. 14. A. Bouar, e al., "An efficien analyical mehod for elecromagneic field o ransmission line coupling ino a recangular enclosure excied by an inernal source", IEEE T-EMC, pp. 1-9,

62 References & Furher Reading A. Beygi and A. Dounavis, "Analysis of excied muli-conducor ransmission lines based on he passive mehod of characerisics macro-model," IEEE T-EMC, vol. 54, pp , Dec. 1. F. Capolino, e al., "Equivalen ransmission line model wih a lumped X-circui for a mea-layer made of pairs of planar conducors, IEEE T-AP, vol. 61, pp , Feb. 13. G. Lugrin, e al., "High-frequency elecromagneic coupling o muliconducor ransmission lines of finie lengh, IEEE T-EMC, vol. 57, pp , Dec. 15. M. Chernobryvko, D. De Zuer, and D. Vande Ginse, "Nonuniform muli-conducor ransmission line analysis by a wo-sep perurbaion echnique", IEEE T-CPMT, vol. 4, pp , Nov. 14. G. Anonini, e al., "Review of Clayon R. Paul sudies on muliconducor ransmission lines", IEEE T-EMC, vol. 55, pp , Aug