MC14569B. Programmable Divide By N Dual 4 Bit Binary/BCD Down Counter

Transcription

1 M14569B Programmable ividebyn ual 4Bit Binary/B own ounter The M14569B is a programmable dividebyn dual 4bit binary or B down counter constructed with MOS Phannel and Nhannel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the M14568B phase comparator/counter in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. Features Speedup ircuitry for Zero etection Each 4Bit ounter an ivide Independently in B or Binary Mode an be ascaded With M14526B for Frequency Synthesizer Applications All Outputs are Buffered Schmitt Triggered lock onditioning PbFree Packages are Available* MAXIMUM RATINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit V Supply Voltage Range 0.5 to V V in, V out Input or Output Voltage Range ( or Transient) 0.5 to V V I in, I out P Input or Output urrent ( or Transient) per Pin Power issipation, per Package (Note 1) ± ma 500 mw T A Ambient Temperature Range 55 to +125 T stg Storage Temperature Range 65 to +0 T L Lead Temperature (8Second Soldering) 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature erating: Plastic P and /W Packages: 7.0 mw/ From 65 To 125 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V ). Unused outputs must be left open. A WL, L YY, Y WW, W PIP16 P SUFFIX ASE 648 TSSOP16 T SUFFIX ASE 948F SOI16 W SUFFIX ASE 751G MARKING IAGRAMS M14569BP AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet B ALYW 14569B AWLYYWW *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. Semiconductor omponents Industries, LL, 2005 February, 2005 Rev. 5 1 Publication Order Number: M14569B/

2 M14569B PIN ASSIGNMENT ZERO ETET TL V P P7 P P6 P P5 P P4 ASAE FEEBAK 7 TL 2 V SS 8 9 LOK BLOK IAGRAM TL = Low for Binary ount TL = High for B ount P0 P1 P2 P3 TL 1 TL 2 P4 P5 P6 P V = PIN 16 V SS = PIN 8 LOK 9 BINARY/B OUNTER #1 LOK LOA BINARY/B OUNTER #2 ASAE FEEBAK 7 ZERO ETET ENOER 1 ZERO ETET ORERING INFORMATION evice Package Shipping M14569BP PIP Units / Rail M14569BPG PIP16 (PbFree) 500 Units / Rail M14569BW SOI16 WB 47 Units / Rail M14569BWG SOI16 WB (PbFree) 47 Units / Rail M14569BWR2 SOI16 WB 00 Units / Tape & Reel M14569BWR2G SOI16 WB (PbFree) 00 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8011/. 2

3 M14569B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELETRIAL HARATERISTIS (Voltages Referenced to V SS ) haracteristic Output Voltage V in = V or 0 0 Level Symbol V OL V in = 0 or V 1 Level V OH Input Voltage 0 Level (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or 1.0 Vdc) (V O = 13.5 or 1.5 Vdc) (V O = 0.5 or 4.5 Vdc) 1 Level (V O = 1.0 or 9.0 Vdc) (V O = 1.5 or 13.5 Vdc) Output rive urrent (V OH = 2.5 Vdc) Source (V OH = 4.6 Vdc) (V OH = 9.5 Vdc) (V OH = 13.5 Vdc) (V OL = 0.4 Vdc) Sink (V OL = 0.5 Vdc) (V OL = 1.5 Vdc) V IL V IH I OH I OL V Vdc Min Max Min Typ Max Min Max Unit (Note 2) Input urrent I in ±0.1 ± ±0.1 ±1.0 Adc Input apacitance (V in = 0) in 7.5 pf Vdc Vdc Vdc Vdc madc madc uiescent urrent (Per Package) Total Supply urrent (Notes 3 & 4) (ynamic plus uiescent, Per Package) ( L = 50 pf on all outputs, all buffers switching) I I T I T = (0.58 A/kHz) f + I I T = (1.20 A/kHz) f + I I T = (1.95 A/kHz) f + I 2. ata labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. 3. The formulas given are for the typical characteristics only at To calculate total supply current at loads other than 50 pf: I T ( L ) = I T (50 pf) + ( L 50) Vfk where: I T is in A (per package), L in pf, V = (V V SS ) in volts, f in khz is input frequency, and k = Adc Adc 3

4 M14569B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITHING HARATERISTIS ( L = 50 pf, T A = 25 ) haracteristic Symbol V Vdc Output Rise Time t TLH Output Fall Time t THL TurnOn elay Time Zero etect Output t PLH Output TurnOff elay Time Zero etect Output t PHL Output lock Pulse Width t WH lock Pulse Frequency f cl lock Pulse Rise and Fall Time t TLH, t THL Min All Types Typ (Note 5) NO LIMIT 5. ata labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. Max Unit ns ns ns ns ns ns ns MHz s SWITHING WAVEFORMS 20 ns LOK % 90% 50% 20 ns f in = f max 20 ns LOK % 90% 50% 20 ns t WH t PLH t PHL t WH t PLH t PHL % 50% 90% ZERO ETET % 90% t TLH t THL t TLH t THL Figure 1. Figure 2. 4

5 M14569B PIN ESRIPTIONS INPUTS P0, P1, P2, P3 (Pins 3, 4, 5, 6) Preset Inputs. Programmable inputs for the least significant counter. May be binary or B depending on the control input. P4, P5, P6, P7 (Pins 11, 12, 13, 14) Preset Inputs. Programmable inputs for the most significant counter. May be binary or B depending on the control input. lock (Pin 9) Preset data is decremented by one on each positive transition of this signal. OUTPUTS Zero etect (Pin 1) This output is normally low and goes high for one clock cycle when the counter has decremented to zero. (Pin ) Output of the last stage of the most significant counter. This output will be inactive unless the preset input P7 has been set high. ONTROLS ascade Feedback (Pin 7) This pin is normally set high. When low, loading of the preset inputs (P0 through P7) is inhibited, i.e., P0 through P7 are don t cares. Refer to Table 1 for output characteristics. TL 1 (Pin 2) This pin controls the counting mode of the least significant counter. When set high, counting mode is B. When set low, counting mode is binary. TL 2 (Pin ) This pin controls the counting mode of the most significant counter. When set high, counting mode is B. When set low, counting mode is binary. SUPPLY PINS V SS (Pin 18) Negative Supply Voltage. This pin is usually connected to ground. V (Pin 16) Positive Supply Voltage. This pin is connected to a positive supply voltage ranging from 3.0 V to 18 V. ORATING HARATERISTIS The M14569B is a programmable dividebyn dual 4bit down counter. This counter may be programmed (i.e., preset) in B or binary code through inputs P0 to P7. For each counter, the counting sequence may be chosen independently by applying a high (for B count) or a low (for binary count) to the control inputs TL 1 and TL 2. The divide ratio N (N being the value programmed on the preset inputs P0 to P7) is automatically loaded into the counter as soon as the count 1 is detected. Therefore, a division ratio of one is not possible. After N clock cycles, one pulse appears on the Zero etect output. (See Timing iagram.) The output is the output of the last stage of the most significant counter (See Tables 1 through 5, Mode ontrols.) When cascading the M14569B to the M14526B, the ascade Feedback input,, and Zero etect outputs must be respectively connected to 0, lock, and Load of the following counter. If the M14569B is used alone, ascade Feedback must be connected to V L = 50 pf f, FREUENY (MHz), TYPIAL V = V V V T A, AMBIENT TEMRATURE ( )

6 M14569B Table 1Mode ontrols (ascade Feedback = Low) ounter ontrol Values ivide Ratio TL 1 TL 2 Zero etect NOTE: ata Preset Inputs (P0P7) are on t ares while ascade Feedback is Low. Table 2Mode ontrols (TL 1 = Low, TL 2 = Low, ascade Feedback = High) Preset Inputs ivide Ratio P7 P6 P5 P4 P3 P2 P1 P0 Zero etect omments Max ount X X Illegal State X Min ount X X X X X X Output Active Bit Value ounter #2 Binary X = No Output (Always Low) ounter #1 Binary ounting Sequence 6

7 M14569B Table 3Mode ontrols (TL 1 = High, TL 2 = Low, ascade Feedback = High) Preset Inputs ivide Ratio P7 P6 P5 P4 P3 P2 P1 P0 Zero etect omments Max ount X X Illegal State X Min ount X X X X X X X X X X Output Active Bit Value ounter #2 Binary X = No Output (Always Low) ounter #1 B ounting Sequence 7

8 M14569B Table 4Mode ontrols (TL 1 = Low, TL 2 = High, ascade Feedback = High) Preset Values ivide Ratio P7 P6 P5 P4 P3 P2 P1 P0 Zero etect omments Max ount X X Illegal State X Min ount X X X X X X X X X Output Active Bit Value ounter #2 B X = No Output (Always Low) ounter #1 Binary ounting Sequence 8

9 M14569B Table 5Mode ontrols (TL 1 = High, TL 2 = High, ascade Feedback = High) Preset Values ivide Ratio P7 P6 P5 P4 P3 P2 P1 P0 Zero etect omments Max ount X X illegal state X Min ount X X X X X X X Output Active Bit Value ounter #2 B X = No Output (Always Low) ounter #1 B ounting Sequence TIMING IAGRAM M14569B LOK IVIE BY 2 ZERO ETET OUTPUT IVIE BY 3 IVIE BY 4 IVIE BY 12 9

10 M14569B TL 1 2 LOGI IAGRAM P P0 3 P P1 4 P P P2 5 P3 6 P P P P IU V ASAE 7 FEEBAK V 9 LOK 11 P4 P 1 ZERO ETET P5 12 P P6 13 P 14 P7 TL 2 P

11 M14569B TYPIAL APPLIATIONS f in F M14569B ZERO ETET F M14522B OR M14526B 4 0" F M14522B OR M14526B 4 0" 1/2 M14568B 0" P0 P3 P0 P3 P0 P3 LS MS f out Figure 3. ascading M14568B and M14522B or M14526B with M14569B (40 khz) V SS P in 1 T1 0" P out G F 1/2 V SS V SS VO f out ( MHz) P0 P3 M14011 V F M14569B ZERO ETET 2 k MIXER Frequencies shown in parenthesis are given as an example 2 M RYSTAL OSILLATOR (143.5 MHz) Figure 4. Frequency Synthesizer with M14568B and M14569B Using a Mixer (hannel Spacing khz) 11

12 M14569B PAKAGE IMENSIONS PIP16 P SUFFIX PLASTI IP PAKAGE ASE ISSUE T 16 A B NOTES: 1. IMENSIONING AN TOLERANING R ANSI Y14.5M, ONTROLLING IMENSION: INH. 3. IMENSION L TO ENTER OF LEAS WHEN FORME PARALLEL. 4. IMENSION B OES NOT INLUE MOL FLASH. 5. ROUNE ORNERS OPTIONAL. H G F 16 PL S K 0.25 (0.0) M T SEATING T PLANE A M J L M INHES MILLIMETERS IM MIN MAX MIN MAX A B F G 0.0 BS 2.54 BS H 0 BS 1.27 BS J K L M 0 0 S TSSOP16 T SUFFIX PLASTI TSSOP PAKAGE ASE 948F01 ISSUE A 0. (0.006) T 0. (0.006) T 0. (0.004) T SEATING PLANE L U PIN 1 IENT. U S S 2X L/2 16X K REF 0. (0.004) M T U S V S A V G B U N H N J J1 F ETAIL E ETAIL E K K1 ÇÇÇ ÉÉ SETION NN 0.25 (0.0) M W NOTES: 1. IMENSIONING AN TOLERANING R ANSI Y14.5M, ONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXEE 0. (0.006) R SIE. 4. IMENSION B OES NOT INLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXEE 0.25 (0.0) R SIE. 5. IMENSION K OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K IMENSION AT MAXIMUM MATERIAL ONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INHES IM MIN MAX MIN MAX A B F G 0.65 BS BS H J J K K L 6.40 BS BS M

13 M14569B PAKAGE IMENSIONS SOI16 WB W SUFFIX PLASTI SOI PAKAGE ASE 751G03 ISSUE 8X H 0.25 M B M A 16 9 E X B B 0.25 M T A S B S A h X 45 NOTES: 1. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TOLERANES R ASME Y14.5M, IMENSIONS AN E O NOT INLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0. R SIE. 5. IMENSION B OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXESS OF THE B IMENSION AT MAXIMUM MATERIAL ONITION. MILLIMETERS IM MIN MAX A A B E e 1.27 BS H h L q X e A1 T SEATING PLANE L 13

14 M14569B ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution enter for ON Semiconductor P.O. Box 61312, Phoenix, Arizona USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Japan: ON Semiconductor, Japan ustomer Focus enter 291 Kamimeguro, Meguroku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. M14569B/

15 This datasheet has been download from: atasheets for electronics components.