Charge Steering: A Low-Power Design Paradigm

Transcription

1 Charge Seering: A Low-Power esign Paradigm Behzad Razavi Elecrical Engineering eparmen Universiy of California, Los Angeles Absrac iscree-ime charge-seering circuis consume less power han heir coninuous-ime curren-seering counerpars even a high speeds. This advanage can be exploied in he design of semi-analog circuis such as laches, demuliplexers, and CR circuis as well as mixed-mode sysems such as ACs. Employing charge seering in 65-nm CMOS echnology, a 5-Gb/s CR/deserializer consumes 5 mw and a 1-bi 8-MHz pipelined AC draws 19 mw. I. INTROUCTION The hrus for low-power circui design coninues unabaed, presening especially ough challenges as high speeds are sough. The power-speed rade-off associaed wih any circui funcion becomes nonlinear as he frequency of operaion exceeds a cerain limi, moivaing effors oward developing new echniques. This paper presens he concep of charge seering as a candidae for low-power, high-speed design. Applicable o boh digial and analog circuis, he concep offers a facor of o 4 power saving for a given se of design consrains, and i has been demonsraed in he conex of a 5-Gb/s clock and daa recovery (CR)/deserializer circui [1] and a 1-bi 8-MHz analog-o-digial converer (AC) []. Secion II inroduces he basic idea and Secion III deals wih charge-seering logic. Secion IV applies he concep o CR and deserializer design, describing how charge seering issues can be resolved a he archiecure level. Secion V presens charge-seering op amps and heir use in pipelined ACs. II. BASIC IEA A coninuous-ime curren-seering circui can be ransformed o a discree-ime charge-seering opology as depiced in Fig. 1: he ail curren source is replaced wih a charge source, and he load resisors wih capaciors. iscree-ime operaion requires wo swiches in he ail pah and wo a he oupu nodes. Shown here for a simple differenial pair, he ransformaion can be applied o oher circui opologies as well. Figure illusraes he operaion of he charge-seering sage. The circui begins in he rese mode, wih C T discharged o ground and he oupu nodes precharged o. When goes high, he circui eners he amplificaion mode, R Vou I SS R C Vou CT C Fig. 1. Transformaion from curren seering o charge seering. Rese Mode C C C C X Y X Y P M 1 M B C T VX, V Y V B Amplificaion Mode P M 1 M B C T Fig.. Operaion of charge-seering sage. C T pulls curren from M 1 and M, and nodes X and Y are released. The wo ransisors coninue o draw differenial and common-mode (CM) currens from he load capaciors unil C T charges o approximaely one hreshold below he higher inpu level. As explained below, wih proper choice of device parameers, he charge-seering sage can provide volage gain. The discree-ime naure of his opology offers hree advanages over is coninuous-ime counerpars. Firs, he circui can serve as a lach wih moderae, conrolled oupu swings, poenially running faser han rail-o-rail (CMOS) logic. Second, he sage seers curren for a fracion of he clock period, hereby consuming less power han coninuous-ime opologies such as curren-mode logic (CML) circuis. Third, since he average power consumpion of he sage scales wih fre /13/$ IEEE 1

2 quency, he same design can be reused a differen clock raes wih no modificaion. For example, he AC described in Secion V has been esed wih clock frequencies ranging from 1 MHz o 8 MHz, wih is power consumpion varying from.4 mw o 19 mw. This aribue is paricularly aracive for applicaions ha require a wide range of clock frequencies and ypically dicae exensive programmabiliy in he design. Charge seering faces wo issues. Firs, in conras o convenional CML circuis, he swiches in Fig. mus be driven by rail-o-rail clock swings. Noneheless, he power savings afforded by his echnique ypically ouweigh he clock power consumed in a CML environmen. Second, as wih any precharged circui, charge-seering opologies produce a reurn-o-zero (RZ) oupu. This issue manifess iself in daa communicaion sysems, e.g., CR circuis, bu no in inherenly discree-ime applicaions such as ACs. The charge-seering sage of Fig. forms he foundaion for he digial and analog circuis described in his paper. We will employ his building block o develop phase deecors (Ps), CRs, and demuliplexers (MUXes) for wireline design as well as op amps for AC design. I is imporan o disinguish his opology from oher differenial dynamic logic syles. In he differenial precharged sage of Fig. 3, he absence of a ail capacior allows he Fig. 3. Examples of differenial dynamic circuis: precharged, dynamic amplifier. oupus o collapse o zero, leading o a slow response. Also, in he logic syle of Fig. 3 [3], he circui draws curren from for half a clock cycle and, more imporanly, suffers from a lower speed because is ail curren mus flow from boh he PMOS loads and he load capaciances. 1 III. CHARGE-STEERING LOGIC A. Gain and Power Consumpion For use in high-speed digial design, he charge-seering circui of Fig. mus operae wih moderae inpu and oupu volage swings while providing some volage gain so as o resore he logical levels. I can be shown ha, for a small differenial inpu,, he volage gain is relaively independen of he inpu CM level, V CM, and is given by [1] A v C T C : (1) 1 Bu one advanage of his syle is ha i produces an NRZ oupu. For moderae o large inpus, on he oher hand, he differenial oupu volage depends on V CM and is equal o = C T (V CM, V TH) + 3V in 4 C V CM, V TH + V ; () in (mv) where V TH denoes he hreshold volage of M 1 and M [1]. erived using simple, rough approximaions, hese expressions are ploed in Fig. 4 agains simulaion resuls, exhibi (mv) Simulaion Predicion Fig. 4. Simulaed and calculaed characerisics of charge-seering sage. ing modes accuracy. In his example, he circui provides a small-signal gain of abou and an oupu swing of abou 35 mv. In order o appreciae he power swings, we perform a comparison wih a coninuous-ime CML sage. Suppose he wo opologies in Fig. 1 operae a he same rae, r b, and deliver equal volage swings o equal load capaciances, C. Noe ha C is no an explici capacior and simply models he parasiics a each node and he inpu capaciance of he following sage. The CML circui mus provide a bandwidh of abou :7r b, i.e., (R C ),1 = :7r b, while producing a singleended oupu swing of V = I SS R. In he charge-seering configuraion, only one load capacior charges o and discharges o, each bi period, yielding an average supply curren equal o I = C r b V: (3) Eliminaing r b and R from he foregoing expressions, we obain I = 1 I SS 1:4 ; (4) predicing a facor of 4.4 reducion in power. B. Regeneraive Lach The concep of charge seering can be applied o regeneraive laches as well. Le us conemplae a discree-ime version of a sandard CML lach [Fig. 5], assuming ha M 1 -M and M 3 -M 4 are enabled by complemenary clocks. Unforunaely, his circui requires hree phases for precharge, amplificaion, and regeneraion. We insead consider only he cross-coupled

3 M 1 M CT M 3 M 4 C T S 1 Y X S C M 1 M Fig. 5. Charge-seering implemenaion of a CML lach, single regeneraive lach. pair and conver is precharge mode o a sampling mode [Fig. 5]. The circui now racks he inpu for half a clock cycle and regeneraes for he oher half, hus producing a non-reurno-zero (NRZ) oupu. The NRZ lach of Fig. 5 can provide volage gain. If he ransisors operae in weak o moderae inversion, he gain can be approximaed as [1] V XY 1 V XY = exp S 3 S 4 C T C CT V CM, V GS ; (5) C V T where he lef-hand side represens he raio of he final and iniial volages, V GS is assumed relaively consan, and denoes he subhreshold nonidealiy facor and is given by 1 + C d =C ox,wherec d is he depleion capaciance under he channel. Figure 6 plos Eq. (5) wih V GS = 45 mv along wih simulaion resuls, indicaing good agreemen. (mv) Simulaion Predicion (mv) Fig. 6. Simulaed and calculaed characerisics of NRZ lach. C. Cascading Issues In order o implemen flipflops and more complex funcions, charge-seering laches mus be cascaded. We consider he opologies in Figs. and 5 for his purpose, noing ha one permuaion, Fig. 5, has no proved pracical. Figure 7 shows anoher permuaion consising of wo cascaded RZ laches driven by 1 and. This arrangemen faces an issue if he wo clocks are simply complemenary: when he slave begins o sense, he maser eners he precharge mode X Maser Maser is rese Y 1 Slave is rese Maser is evaluaed X (c) T Slave is evaluaed Y V X1 V X Slave Fig. 7. Cascade of wo RZ laches, use of quadraure clocks, (c) cascade of wo NRZ laches. and is differenial oupu begins o collapse. The slave may herefore generae a small oupu swing in some corners of he process. To avoid his race condiion, one can employ quadraure phases for 1 and so ha he maser oupu is held consan when he slave eners he evaluaion mode [Fig. 7] - bu a he cos of power and complexiy in clock generaion. Figure 7(c) shows anoher cascading permuaion using wo NRZ laches. In his case, he circui conains no inernal pah from and hence provides no charge amplificaion. Tha is, only he charge deposied by mus produce he volage swings as he signal propagaes down he chain, leading o subsanial corrupion of random daa. As illusraed in Fig. 7(c), if he saes on X and Y are opposie of hose on X 1 and Y 1,whenS 3 and S 4 urn on, he maser and slave capaciances experience severe charge sharing, heavily aenuaing he daa swings. Even if he maser devices are scaled up by a facor of 5, his memory effec sill produces significan inersymbol inerference (ISI). The las permuaion of he RZ and NRZ laches is shown in Fig. 8. Here, he maser consiss of he passive sampling 3

4 Vin (5 Gb/s) (1.5 GHz) µ m X 1 1 µ m Y 1 µ m 8 µ m X 4 µ m µ m 8 µ m 4 µ m 1 ff ff Y in (NRZ aa) L 1 L X 1 X G 1 V ERR L 3 L 5 Y 1 Y L 4 L 6 G Z 1 Z G3 V REF1 Fig. 8. Cascade of NRZ and RZ laches. V REF nework, S 1 and S, while he slave is formed by M 1 -M and M 3 -M 4. The charge amplificaion provided by he laer pair avoids corrupion of he sae sored by he former. Clocked simulaneously, he wo sages amplify he sampled signal a X 1 and Y 1, generaing a single-ended swing of abou 4 mv a X and Y wih a power consumpion of 158 W aadaa rae of 5 Gb/x and a clock rae of 1.5 GHz. However, he oupu is sill in RZ form IV. CR AN MUX ESIGN The conceps developed above can be applied o he design of high-speed CRs and (de)muliplexers. In his secion, we presen some examples for 5-Gb/s operaion, assuming a half-rae archiecure bu wihou quadraure clock phases. A. Half-Rae Phase eecor A half-rae P ha does no require quadraure clocks can be realized as four laches and wo exclusive-or (XOR) gaes [4]. Unforunaely, his opology does no lend iself o charge seering circuis wih RZ oupus [1]. Forunaely, i is possible o modify he P so as o operae wih RZ daa [Fig. 9]. Here, laches L 5 and L 6 are added o inser half a cycle delay, and XOR gaes G and G 3 are respecively used o compare Y 1 wih a delayed version of Y and Y wih a delayed version of Y 1. The average difference beween V ERR and V REF = V REF 1 + V REF represens he phase difference beween he random daa and he clock [Fig. 9]. In he circui of Fig. 9, he lach pairs L 1 -L 3 and L - L 4 are consruced as shown in Fig. 8. Laches L 5 and L 6 employ he RZ opology of Fig.. The reimed half-rae daa is available a Y 1 and Y bu sill in RZ form. B. emuliplexer In order o furher demuliplex he daa, we cascade RZ laches bu ensure ha when one is being rese, he nex does no begin o sense. This is possible because he half-rae (1.5- GHz) clock can be divided by so as o produce quadraure phases a 6.5 GHz. Figure 1 depics such an arrangemen and is iming diagram, where 1=;I and 1=; represen he quadraure phases of he 6.5-GHz clock. We noe ha a = 1, L 3 (one of he laches wihin he P) eners he evaluaion mode and, afer one divider delay, so does L 7.Nex, V REF V ERR (mv) Phase error (ps) Fig. 9. P using charge-seering laches, simulaed inpu-oupu characerisic. 1/,I 1/, Phase eecor L 3 L 4 L 3 evaluaed 1 L 7 evaluaed Y 1 Y L 9 evaluaed L 7 L 8 L 9 L 1 L 8 evaluaed Fig. 1. MUX realizaion. 1/,I 1/, a =, L 3 eners he evaluaion mode again and so does L 8. 4

5 The boom MUX pah consising of L 9 and L 1 operaes in a similar manner bu wih 1=;. The four laches consume 183 W a 6.5 GHz. According o simulaions, for a given power consumpion, charge-seering laches running a 6.5 GHz sill ouperform rail-o-rail logic in erms of he oupu ISI. C. RZ-NRZ Conversion The low-swing RZ waveforms produced by charge-seering circuis can be convered o NRZ daa by means of a rail-o-rail RS lach. However, he amplificaion of he RZ waveform o achieve rail-o-rail swings demands subsanial power. A more efficien approach incorporaes a clocked dynamic comparaor for amplificaion [1]. Exemplified by he SrongArm opology, such a comparaor oo produces RZ oupus when i is rese and hence resembles he dynamic circui in Fig. 3. If cascaded wih a charge-seering lach, he comparaor hus suffers from he race condiion described for he flipflop in Fig. 7. Since he demuliplexed daa is now available a he quarer rae, we may reconsider he scenario in Fig. 7 and uilize he quadraure phases of he quarer-rae (6.5-GHz) clock. Figure 11 depics he MUX/RZ-NRZ conversion chain. MUX E. Experimenal Resuls A 5-mW 5-Gb/s CR/deserializer using an LC VCO has been fabricaed in 65-nm CMOS echnology. The die phoograph is shown in Fig. 1, he recovered clock phase noise in Fig. 1, and he jier olerance for wo differen supply volages in Fig. 1(c) [1]. Exhibiing an rms jier of 1.5 ps wih a 15, 1 PRBS, he prooype consumes abou a facor of less power han he prior ar [5, 6] and demonsraes he advanages of charge seering. L 7 RZ aa Charge Seering Lach RS Lach NRZ aa 1/,I 1/, Fig. 11. RZ-o-NRZ conversion. As menioned earlier, L 7 is driven by 1=;I. We choose 1=; o clock he comparaor, applying he resul o a CMOS RS lach. The comparaor and he RS lach draw 13 W a 6.5 GHz, far less han ypical CML-CMOS converers do.. Clock Generaion and isribuion As poined ou in Secion II, charge-seering circuis dicae rail-o-rail clock swings, a condiion afforded by LC oscillaors. However, he imporan quesion is wheher he VCO should drive he laches, he frequency divider(s), and he wiring capaciance direcly or hrough a buffer. The oal load capaciance presened by his nework is abou 7 ff in our work, demanding a power of fcv 8mWifwo inverers follow he differenial VCO oupus. I is herefore beneficial o omi he buffers and absorb his capaciance in he VCO ank even a he cos of a lower ank inducance and hence a greaer bias curren. In his case, he higher VCO power dissipaion also ranslaes o a lower phase noise. The criical poin here is ha a given power budge is more efficienly uilized in a VCO han in buffers, suggesing ha buffers are generally redundan [1]! One excepion is a case where he loss associaed wih he inerconnecs significanly lowers he VCO ank. Jier Ampliude (UI pp ) =1.1 V =1. V Jier Frequency (Hz) Fig. 1. CR/deserializer s die phoo, recovered clock phase noise, and (c) jier olerance. (c) V. CHARGE-STEERING ACS A. Charge-Seering Op Amps A pracical one-sage charge-seering amplifier can achieve a gain of o 4, poining o a wo-sage configuraion if a gain commensurae wih pipelined AC design is desired. Figure 5

6 13 shows a basic opology, where he ail capaciors are CF C in Vou C L C 1 C 3 C 4 VX1 VY1 VX VY C M 1 M M 3 M 4 V XY Vin Cin V CM KV V REF CM CF Op Amp V x g V m x r O CL Vou V X1Y1 Fig. 13. Charge-seering op amp, and is waveforms. removed o allow a large amoun of charge o flow. Here, he wo sages simulaneously amplify unil he oupus of he firs sage collapse and he second sage urns off. uring his ransien, V X1Y 1 rises o a peak and falls back o zero whereas V XY monoonically increases o an amplified copy of he inpu [Fig. 13]. This wo-sage design can provide an open-loop gain of abou 1. The values of C 1 -C 4 are dicaed by kt=c noise requiremens. The charge-seering op amp exhibis a unique behavior in a closed-loop configuraion [] such as he muliplying digialo-analog converer (MAC) of Fig. 14. Owing o he large load capaciors and he absence of load resisors, each sage behaves as an inegraor, incurring loss only due o he oupu resisance of he ransisors. Simplified as shown in Fig. 14, he wo-inegraor feedback loop hus produces an underdamped oupu ha is frozen when he second sage urns off a = 1 [Fig. 14(c)]. As a resul of his overshoo, he closed-loop gain can be greaer han C in =C F. I is possible o design he firs sage such ha is CM level falls o one hreshold above ground by he ime reaches is peak value a p. Freezing he oupu in is zero-slope regime, such a choice minimizes PVT-induced variaions in he final value of. The gain, noise, speed, power dissipaion, and lineariy of he above op amp can be compared wih hose of coninuousime opologies. In a pipelined AC environmen, he MAC sage depiced in Fig. 14 exercises all of hese properies. We design he op amp of Fig. 13 as well as he wo configuraions shown in Fig. 15 for C in = 48 ff, C F = 4 ff, C L = 5 ff, = 1 V, a differenial oupu swing of.6 V pp, an open-loop gain of 1, a power dissipaion of.5 mw, and a clock rae of 1 GHz. The simulaed seling ime, disorion, and inpu-referred noise of he MAC are Alhough no idenified as a charge-seering op amp, a similar opology wihou explici load capaciors has been used in [7] for 6-bi resoluion. 1 p Fig. 14. MAC environmen for charge-seering op amp, simplified closed-loop model, self-imed underdamped behavior. M 1 M V M 1 M M 3 M 4 in (c) Fig. 15. One-sage and wo-sage op amps sudied for quaniaive comparisons. lised in Table 1, revealing he bes of all worlds for he Seling Time 56 ps 37 ps 8 ps SR 48 db 53 db 54 db Inpu Ref. Noise One Sage Op Amp Two Sage Op Amp 67 nv 138 nv Charge S. Op Amp 65 nv Table 1. Simulaed performance of MAC using each op amp opology. charge-seering opology. The resuls depiced in Table 1 imply ha, due o heir low open-loop gain, charge-seering op amps do no provide adequae lineariy for a 1-bi AC, dicaing nonlineariy 6

7 (and gain error) calibraion. For example, an accurae onchip ladder can be uilized o calibrae he AC in he digial domain by means of an LMS machine [8]. However, he characerisics of hese op amps are somewha sensiive o he inpu and oupu CM levels. In paricular, if he oupu CM level, ;CM, shifs from is opimum value by more han 1 mv, he open-loop lineariy degrades, making calibraion difficul. I is difficul o apply CM feedback o charge-seering op amps in he analog domain because he oupu CM level reaches is final value afer he sages have urned off. Alernaively, he opimum value of ;CM can be viewed as ha which maximizes he MAC lineariy. Tha is, during calibraion, he LMS machine can adjus ;CM along wih he digial coefficiens so as o minimize he nonlineariy []. Illusraed in Fig. 16, his approach unes ;CM in discree Second Sage of Op Amp Vin R CM AC AC Sage 1 Sage R CM Residue To Sages 5 13 M 1 M Vou (V) M 3 M 4 M 3 M Time (ns) Fig. 17. Three-sage charge-seering op amp, and is response in an MAC environmen. closed-loop ransfer funcion is given by Error LMS CM crl β Polynomial β Polynomial igial Oupu H(s)= 1 + A 3 (1 + s! ) 3 A 3 (1 + s! ) 3 ; (6) cal From Precision Ladder igial Nonlineariy Correcion Fig. 16. Common-mode conrol by LMS machine. seps by conrolling he ail resisance, R CM, in he second sage of each op amp. B. Three-Sage Op Amps The self-imed naure of charge-seering op amps suggess ha more han wo sages can be cascaded so as o increase he open-loop gain. Consider he arrangemen shown in Fig. 17, where he oupus of he firs and second sages collapse o zero a abou he same ime, allowing he hird sage o mainain an amplified oupu. According o simulaions, his circui can achieve a gain of. To sudy he circui s behavior in a closed-loop configuraion, we approximae he ransfer funcion of each lossy inegraor by A =(1 + s=! ),wherea = g m r O and! = g m =C. [The load capaciors, C s, are no shown in Fig. 17 for simpliciy.] Wih uniy-gain negaive feedback, he and he poles are compued from (1 + s! ) 3 + A 3 = : (7) The loop conains one real pole locaed a,(a + 1)! and wo complex poles a (A =, 1)! j( p 3=)A!,which for A >, fall in he righ half plane and yield a growing sinusoid - jus as in a hree-sage ring oscillaor. However, he las wo sages urn off afer a brief period of ime, sopping he growh and producing an amplified oupu. Figure 17 plos he simulaed sep response of he hree-sage op amp in he MAC environmen of Fig. 14, revealing a seling ime of abou 7 ps. The foregoing sudy indicaes ha he design of chargeseering op amps markedly depars from he convenional wisdom. The closed-loop circui is allowed o be unsable so long as he sages urn off before or a he (firs) peak value of he oupu. I is conceivable ha a larger number of sages can also be used o furher increase he gain. C. Experimenal Resuls A 1-bi 8-MHz pipelined AC using wo-sage chargeseering op amps has been designed and fabricaed in 65-nm CMOS echnology []. Figure 18 shows he die phoograph 7

8 perform in complex circuis. Issues associaed wih his design paradigm have been discussed and soluions have been proposed. Providing a fourfold power advanage over CML circuis, charge seering has been exploied in a 5-Gb/s CR/deserializer dissipaing 5 mw and a 1-bi 8-MHz AC consuming 19 mw. Acknowledgmens This work was suppored by he ARPA HEALICS program, Texas Insrumens, and Realek Semiconducor. The auhor is graeful o he TSMC Universiy Shule Program for chip fabricaion. NL (LSB) NL (LSB) 3 1 Before Calibraion Code Afer Calibraion Code INL (LSB) Before Calibraion Code Afer Calibraion INL (LSB) Code Fig. 18. AC die phoograph, measured NL and INL before and afer calibraion. and Fig. 18 he NL and INL before and afer calibraion. Figure 19 plos he SNR as a funcion of he inpu frequency, SNR (db) REFERENCES [1] J.W. Jung and B. Razavi, A 5-Gb/s 5-mW CMOS CR/eserializer, IEEE J. Solid-SaeCircuis, vol. 48, pp , Mar. 13. [] S.-H. Chiang, H. Sun, and B. Razavi, A 1-Bi 8-MHz 19-mW CMOS AC, o be presened a Symposium on VLSI Circuis, Kyoo, June 13. [3] A. Ghilioni e al, A 4.8mW Inducorless CMOS Frequency ivider-by-4 wih more han 6% Fracional Bandwidh up o 7 GHz, Proc. CICC, Sepember 1. [4] J. Savoj and B. Razavi, A 1-Gb/s CMOS clock and daa recovery circui wih a half-rae linear phase deecor, IEEE J. Solid-Sae Circuis, vol. 36, pp , May 1. [5] C. Kromer e al., A 5-Gb/s CR in 9-nm CMOS for high-densiy inerconnecs, IEEE J. Solid-Sae Circuis, vol. 41, pp , ec. 6. [6] K. Yu and J. Lee, A x5-gb/sreceiver wih :5 MUX for 1-Gb/s Eherne, IEEE J. Solid-SaeCircuis, vol. 45, pp , Nov. 1. [7] B. Verbruggen e al, A.6mW 6b.GS/s 4-imes inerleaved fully dynamic pipelined AC in 4nm digial CMOS, ISSCC ig. Tech. papers, pp , Feb. 1. [8] A. Verma and B. Razavi, A 1-Bi 5-MS/s 55-mW CMOS AC, IEEE J. of Solid-Sae Circuis, vol. 44, pp , Nov Inpu Frequency (MHz) Fig. 19. Measured SNR of he AC a a sampling rae of 8 MHz. exhibiing a value of 5. db a Nyquis rae. The AC draws 19 mw from a 1-V supply and provides an FOM of 53 fj per conversion sep. VI. CONCLUSION Charge seering holds promise for high-speed analog and mixed-signal circuis wih low power consumpion. The discree-ime naure of his design echnique enables digial laching as well as mui-sage, nominally unsable op amps o 8