Learning Objectives: Practice designing and simulating digital circuits including flip flops Experience state machine design procedure

Transcription

1 Lab 4: Synchronous Sae Machine Design Summary: Design and implemen synchronous sae machine circuis and es hem wih simulaions in Cadence Viruoso. Learning Objecives: Pracice designing and simulaing digial circuis including flip flops Experience sae machine design procedure Resources and Supplies: Engineering PC wih PuTTY and Xming Lab4A.x & Lab4B.x* Sae Machine Inroducion* All documens* are available on he class websie Imporan Noe Spring 203: We have made a change o he 33 Viruoso library. Before using Viruoso again, you mus re-run he seup scrip below in your ECE33/viruoso direcory o insall he new library. source $SOFT/cadence-auo Pre-lab Assignmen: Each suden mus complee his/her own pre-lab before coming o he lab. Pre-lab checkoff shees mus be urned in o he TA before saring he lab assignmen.. Read he Background secions of his lab. 2. Prin he Pre-lab 4 Check-off Shee near he end of his documen and perform he required asks. Show he compleed shee o he TA a he beginning of your lab. 3. Read hrough he enire Laboraory Assignmen secion so you know wha o expec in he lab. Background: D-ype Flip Flop Flip flops (FF) are daa sorage elemens for synchronous circuis ha have circui blocks riggered simulaneously and periodically by a clock signal. FFs are used o sore he logic sae of a signal unil he nex rising (or falling) edge of he clock signal when he oupu is reevaluaed and sored again. FFs are conrolled by a clock signal and one or wo daa inpu signals, and hey ypically have differenial (invered) oupus Q and Q. There are several variaions of FFs including JK and SR ype FFs. However, he mos common FF used in digial inegraed circuis is he D-ype FF (DFF). In a DFF, he value of inpu D is ransferred o he oupu Q a he rising (or falling) clock edge and held here unil he nex rising (or falling) edge. The sandard schemaic symbol for a DFF is shown below along wih a iming diagram for a posiive edge riggered DFF. In his lab you will use a DFF o creae sae machines. The DFF cell provided in your Viruoso cell library is a posiive edge riggered circui. Refer o ECE33 Handou 0: 230 Review for addiional background informaion on flip flops. p.

2 Synchronous sae sequencer: Unless you are very familiar wih sae machine design, you firs need o carefully read he Sae Machine Inroducion documen for a horough descripion of he implemenaion of sae machines using flip flops. Once you are familiar wih he sae machine design process, reurn here for informaion on implemening sae machines using DFFs. Figure illusraes he sae ransiions for an example 2-bi sequencer. Synchronous sae machines are ypically implemened using flip-flop circuis. In his lab you will be asked o design and implemen a sae machine using D-ype flip flops (DFF). Figure. Saes in an example 2-bi synchronous sae sequencer. To consruc he Figure sae sequencer using DFFs, you would follow he same seps as shown in he Sae Machine Inroducion documen for an SR flip flop. However, because he DFF is funcionally differen han he SR or JK flip flops, i has a differen ruh able and exciaion able resuling in a differen sae machine implemenaion. Table shows he ruh able and exciaion able for a DFF. Because he DFF only has one daa inpu, i has fewer funcions and is exciaion able is less complex han he SR or JK. This feaure generally resuls in more complex glue logic needed o implemen a sae sequencer. ruh able exciaion able D Q + acion Q Q + acion D 0 0 hold 0 0 hold 0 se 0 se 0 rese 0 rese 0 hold hold Table. Truh able and exciaion able for a DFF. Table shows he operaion of he DFF is really quie simple; he nex sae oupu, Q +, is always he same as he inpu D a he ime of he clock edge rigger. The following seps provide an example of how he sae sequencer in Figure could be designed using DFFs. p. 2

3 Sep : nex-sae exciaion able Table 2 shows each curren sae of he Figure sequencer and is associaed nex sae ha defines he sequencing of he sae machine. Using he DFF exciaion able (Table ), he required inpu values for each sae can hen be deermined, as shown in Table 2. As you should expec for a DFF implemenaion, he required inpus are simply he nex sae oupu values. I is imperaive ha you undersand how Table 2 was generaed because you will be repeaing his in he pre-lab for a more complex sequencer. curren sae nex sae Bi inpu Bi 0 inpu Q + Q + D D Table 2. Nex-sae exciaion able for Fig. sequencer. Sep 2: Inpu ruh ables The daa in Table 2 can be rearranged o show he ruh able for each inpu bi (D, D 0 ) based on he curren-sae oupu values. Table 3 shows he ruh ables for all inpus, uniquely defining he inpus needed o mach he sequence in Figure. I is imporan ha you undersand how Table 3 was generaed because you will be repeaing his in he pre-lab for a more complex sequencer. Q D Q D Table 3. Inpu ruh ables based on curren-sae oupus of Fig. sequencer. Sep 3: Minimize logic expression for all inpus Table 3 defines each flip flop inpu as a funcion of he 2-bi sae oupus (Q - ). We mus nex minimize his expression o define he simples logic circui possible for each inpu. The K-maps in describe he relaionship for each inpu and can be used o deermine he minimized logic expression shown below each K-map. Again, you mus be able o perform his sep in he pre-lab for a more complex sequencer. D Q 0 D 0 Q 0 0 D =, D 0 = Q --- p. 3

4 Sep 4: Circui implemenaion Based on he equaions from sep 3, you should now be able o skech he schemaic of he Figure 2-bi sequencer using he DFF and, as necessary, basic logic gaes. This ask will be compleed as a pre-lab exercise. Noe ha he DFF provides Q and Q oupus, so you do no need an INV gae o complemen he Q oupu. Sae machine: non-sequenced saes: Figure 2 shows he sae model of a specific 3-bi sequence generaor ha operaes only in he 00, 00, 0, 0 saes. Any of he remaining non-sequenced saes (000, 00, 0, ) should reurn o 0 so he sequencer can coninue o operae wihin he four sequenced saes. Figure 2. 3-bi sae sequencer. Laboraory Assignmen: This lab consiss of wo pars. A check-off shee is included a he end of his lab documen o record your design work and resuls. Afer you successfully finish each par of he lab, show he TA your resuls and ask him/her o sign he check-off shee. Prin he check off shee. Ask he TA o check your Pre-lab 4 workshee o ensure you have he correc design and plans for he sae sequencers. Fix any misakes and ask he TA o sign your pre-lab o indicae you have compleed he assignmen. Keep he pre-lab workshee afer he TA signs i and hen aach i o your lab repor. Imporan Noe Spring 203: We have made a change o he 33 Viruoso library. Before using Viruoso again, you mus re-run he seup scrip below in your ECE33/viruoso direcory o insall he new library. source $SOFT/cadence-auo Par : Two bi sequence generaor. In his par you will implemen he Figure 2-bi sae sequencer using D flip-flops based on your pre-lab design. p. 4

5 Implemenaion in Cadence Viruoso:. Sar Viruoso and creae a new schemaic named 2biSae in your projec library. 2. Using your design from pre-lab, insaniae he necessary gaes and DFFs o implemen your design. Make all necessary wire connecions. To make your schemaic less cluered, you can press he L key o open he label window. This allows you o label a wire. Any wires assigned o he same label as anoher wire, or an inpu pin, will ac as if he wires were conneced. This will preven you from having wires spanning he enire schemaic and cluering up he schemaic. 3. Afer you have compleed your schemaic check and save he schemaic and make sure here are no warnings or errors. Demonsraion: 4. Sar he ADE-L simulaor from he launch menu. For he 2bi sequence, use he simulus file named Lab4A.x ha you can download from he ECE 33 websie. 5. Se he run ime for 5ms. 6. Selec he CLK, Q0, and Q as he oupus o be grapghed. 7. Run he simulaion, review your resuls and answer he quesions on he check off shee. 8. Save/prin your 2biSae schemaic and simulaion plos o include in your repor. 9. Ask he TA o check your resuls and iniial your check off shee. Par 2: Sae machine design challenge. In par 2 you will design and implemen he 3-bi sae sequencer shown in Figure 2 based on your preparaion from he pre-lab. Design:. In he Lab 4 Check-off Shee, skech a schemaic showing all he circuiry needed o implemen he 3-bi sequencer from Figure 2. This circui should be based on your pre-lab preparaions and should use DFF s and any necessary basic logic gaes (included he 3-inpu AND, as noed in he pre-lab). As wih he 2-bi sequencer, he only exernal inpu o his circui should be a CLK signal. Implemenaion: 2. Creae a new schemaic named 3biSae. 3. Insaniae he necessary gaes and DFFs and add wires o implemen your pre-lab design for he 3bi sae sequencer. Remember ha you can label wires in order o keep your schemaic clear and make i easier o view. 4. Check and save he schemaic and make sure here are no errors or warnings. Demonsraion: p. 5

6 5. Sar he ADE L simulaor from he Launch menu in he schemaic window. Use he file Lab4B.x as he simulus file which you can download from he ECE33 websie. To es ha your sae machine will correcly go o sae 0 from any of he nonsequence saes, he simulus file imposes an iniial sae ha is ouside he sequence saes. 6. Se he run ime for 5ms. Selec CLK, Q0, Q, and Q2 o be graphed. 7. Run he simulaion, review your resuls and answer he quesions on he check off shee. 8. Save/prin your 3biSae schemaic and simulaion plos o include in your repor. 9. Ask he TA o check your resuls and sign your check off shee. Wrap Up Clean up your lab bench before you exi he lab. Remember, your Lab 4 repor will be due in lab nex week. Each suden mus submi his/her own lab repor. Include your check-off shee and waveform prinous wih your repor. You may wan o review he Discussion Poins below and alk o he TA abou anyhing ha is no clear o you. Discussion Poins As explained in he Lab Repor Guide, you should address hese discussion poins in a designaed secion of your repor.. How many flip flops (bis) are needed for a sequencer for 4 saes? How many are needed for 8 saes? Can you wrie a general expression relaing he number of flip flops, n, o he number of sequencer saes, m? 2. Explain why he saes 000, 00, 0 and in Par 2 mus be mapped ino a sequenial sae even hough hey are no in he desired sequence. Wha could happen if his was no done? 3. How could he 2-bi sequencer be modified o implemen an asynchronous rese, where an addiional rese signal was used o force he sae machine ino a given iniial sae (e.g., 00)? Briefly describe he required rese circuiry. 4. Oher han a sae machine, briefly describe a useful digial circui ha requires flip flops (raher han sandard logic gaes). Do you hink you have he experience need o implemen such a circui in Viruoso? If no, wha knowledge do you feel you lack? Remember o include your resuls graphs as aachmens o your repor. p. 6

7 PRE-LAB 4 Due: A he beginning of lab. Suden Name: Lab. Secion (ime): Make sure you read he Lab 4 Background before you sar he pre-lab. Afer compleing he pre-lab, please review he enire Lab 4 assignmen so you will know wha o expec when you come o lab.. To ensure you are familiar wih he basic seps of implemening a sae machine, read he Sae Machine Inroducion documen. 2. Review he example D flip flop implemenaion of he Figure sae sequencer in he Background secion. Below, record he logic expression ha define each of he sequencer inpus (D, D 0 ) as a funcion of curren-sae oupus (Q, ). D =, D 0 = 3. Based on your equaions from #2, draw a schemaic of he complee 2-sae sequencer using wo DFF cells and any necessary basic logic gaes. Noe, he only exernal inpu o his circui should be a CLK signal. You can draw your schemaic below or aach separaely. <pre-lab coninues on nex page> p. 7

8 In Par 2 of he lab, you will design and implemen he 3-bi sae sequencer shown in Figure 2. Based on he 2-bi example (from Background and earlier pre-lab quesions), complee he following seps o design he 3-bi sequencer. a. How many D flip-flops are needed for a 3-bi sequencer? b. Complee he nex-sae exciaion able below for he Figure 2 sequencer where Q 2 n Q n n are he curren saes and Q 2 n+ Q n+ n+ are he nex saes. Q 2 n Q n n Q 2 n+ Q n+ n+ D 2 D D 0 c. Complee he K-map for each flip flop inpu. Noe each K-map is assigned o a specific combinaion of D and Q 2. Q 0 D 2 Q 2 = 0 Q 0 D Q 2 = 0 Q 0 D 0 Q 2 = 0 Q 0 D 2 Q 2 = Q 0 D Q 2 = Q 0 D 0 Q 2 = d. Based on he K-maps above, deermine he minimized Boolean expressions for all inpus o he 3 flip flops. D 2 =, D =, D 0 =, Noe: A 3-inpu AND gae will be provided o simplify your design. Choose a logic funcion for each inpu ha can be implemened wih only he 3-inpu AND and he basic logic gaes used in Labs -3. You will be asked o design he schemaic o implemen hese inpu funcions during Par 2 of he in-lab assignmen. TA pre-lab sign off Iniial p. 8

9 LAB 4 CHECK-OFF SHEET Suden Name: Lab. Secion (ime): Complee his shee as you complee he lab. Remember o have he TA check off each secion of he assignmen. This shee mus be included in your lab repor. Par : Two bi sequence generaor Sep 7. Is he sae value changing wih he clock? Record he observed sae sequence (e.g., 0 0 ) Does i agree wih he correc sae sequence? Par : TA sign off Iniial Par 2: Sae machine design challenge Sep 7 Record he observed iniial sae value (Q 2,Q, ). Is he sae value changing wih he clock? Sep 7. Wha sae follows he iniial non-sequenced sae? Is his correc? Sep 7. Record he observed sae sequence (e.g., 0 0 ) Does i agree wih he desired sequence? Par 2: TA sign off Iniial p. 9